Final Thesis - ADC

HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY
SCHOOL OF ELECTRONICS AND TELECOMMUNICATIONS
A GRADUATION THESIS FOR
BACHELOR OF ENGINEERING
Topic:
DESIGN OF LOW POWER HIGH LINEARITY SAR

ADC WITH REDUNDANCY AND DIGITAL
BACKGROUND CALIBRATION
Student:
NGUYEN VIET TAN 20092354
Class:
Microelectronics Advance Program K54
Supervisor:
Dr. NGUYEN VU THANG
Committee member:
Hanoi, 6-2014
MINISTRY OF EDUCATION AND TRAINING
SOCIALIST REPUBLIC OF VIETNAM
HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY
Independence-Freedom-Happiness
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HANOI UNIVERISITY OF SCIENCE AND TECHNOLOGY
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Abstract
Smart devices such as smart phone, smart watch, tablet are booming over
the last few years. One of the most important things that make these devices become
so popular is that they use different way from traditional ones to interface with user:
the touchscreen. With the touchscreen, the user can interact directly with what is
displayed, rather than using a mouse, touchpad, or any other intermediate device.
Every time, to know command from user, the analog signal from the touch panel (a
part of touch screen) will always be converted to digital signal by Analog to Digital
Converters (ADCs) and then sent to the CPU. Therefore, the ADC here plays a key
role in the sensitivity and energy-saving of the touch panel.
All smart devices are handheld device so the problem of saving power is one
of the most important one. So, up to now, Successive Approximation Register
(SAR) ADC is always chosen in the touch panel because of its low power
consumption. However, the resolution of SAR ADC is medium compare to other
kinds of ADC, this makes it become not suitable for the demand of high sensitivity
and accuracy touch panel. In order to solve the problem, this thesis describes the
design of a high linearity low power 12-bit synchronous successive approximation
register (SAR) ADC for touch panel.
The prototype has been implemented in TSMC 0.18m Mixed-Signal CMOS
technology, the simulated effective number of bits (ENOB) at near Nyquist
frequency is 12.3-bit. The total power consumption of 15.7W is achieved at
100ksps results in figure of merit (FoM) of only 30.9fJ/conversion-step.
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Acknowledgment
Five years studying in Hanoi University of Science and Technology is a
wonderful time in my life that I will never forget. It is not a long time, but not a
short time either. Throughout this time, I have been so happy and lucky to be
surrounded by family, friends, professors and classmates who have provided cheers
and support. I am indebted to all of them. Without their constant and unconditional
support, this would have never been accomplished.
I would like to express my sincere gratitude to my advisor Dr. Nguyen Vu
Thang for the continuous support of my Bachelor study and research, for his
patience, motivation, enthusiasm, and immense knowledge. There are a lot of thing
that I have learned from him: how to do research, to write a paper, give a coherent
talk, work in a group He gave me smart and valuable advises for problems in my
research as well as in my life whenever I needed.
I would like to thank my labmates in IC Design Lab: Nguyen Minh Duc, Dao
Ba Anh, Mai Tuan Anh, Do Minh Phu, Nguyen Tien Dat and my friends in Hanoi
University of Science and Technology for the stimulating discussions, for the
sleepless nights we were working together before deadlines, and for all the fun we
have had in the last five years.
I would like to thank Duong Viet Duc, Teaching Assistant and Research
Assistant at IC Design Lab, National Tsing Hua University, Hsinchu, Taiwan for his
valuable advises, support and experiment sharing through my Bachelor.
Last but not least, I would to thank my family who always has faith in me,
for their tremendous encouragement and unconditional support throughout my life.
Contents
Chapter 1
Introduction .............................................................................................. 1
1.1. Structure of Projected Capacitive Touch technology with mutual capacitive

approach ....................................................................................................................... 1
1.2. Architecture Selection ........................................................................................ 2
1.3. Performance Metrics of SAR ADCs .................................................................. 3
1.3.1.
Resolution ................................................................................................. 4
1.3.2.
Quantization Noise ................................................................................... 4
1.3.3.
Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) .......... 4
1.3.4.
Signal-to-Noise Ratio (SNR).................................................................... 4
1.3.5.
Effective Resolution ................................................................................. 5
1.3.6.
Figure of Merit (FoM) .............................................................................. 5
1.4. Motivation .......................................................................................................... 5

1.5. Target Specifications .......................................................................................... 6
1.6. Thesis contributions ............................................................................................ 6
Chapter 2
Overview of Traditional SAR ADCs ...................................................... 9
2.1. Binary Successive Approximation Algorithm.................................................... 9

2.2. The SAR Architecture ...................................................................................... 11
2.3. Static Error Sources in SAR ADCs .................................................................. 15
2.3.1.
Capacitor Mismatches ............................................................................ 15
2.3.2.
Offset Errors ........................................................................................... 17
2.4. Dynamic Error Sources in SAR ADCs ............................................................ 18

Chapter 3
Redundancy SAR ADCs ......................................................................... 21
3.1. Redundancy Overview ..................................................................................... 21

3.1.1.
Error tolerance windows for redundancy ............................................... 25
3.1.2.
Dynamic Threshold Comparison............................................................ 26
3.2. Digital calibratability ........................................................................................ 27

3.2.1.
Condition of digital calibratability ......................................................... 27
3.1.2.2.
Amount of redundancy........................................................................ 28
3.1.2.3.
Radix and number of steps .................................................................. 29
Chapter 4
Digital Background Calibration of SAR ADCs ................................... 32
4.2. Overview of digital calibration in SAR ADC .................................................. 32

4.1. Superposition Principle..................................................................................... 34
4.2. Perturbation-Based Calibration Algorithm....................................................... 35

Chapter 5 Design and Implementation of a Redundancy SAR ADCs with
Digital Background Calibration ................................................................................. 40
5.1. Architecture ...................................................................................................... 40
5.1.1.
SAR ADC architecture ........................................................................... 41
5.1.2.
Calibration architecture .......................................................................... 42
5.2. Key circuit building block ................................................................................ 43

5.2.1.
Capacitive DAC Design ......................................................................... 43
5.2.1.1.
Monotonic Capacitor DAC Switching Operation ............................... 43
5.2.1.2.
Main DAC design ............................................................................... 47
5.2.2.
Sampling Network Design ..................................................................... 49
5.2.3.
Dynamic comparator design ................................................................... 50
5.2.4.
Preamplifier design ................................................................................. 51
5.2.5.
Control logic design ............................................................................... 52
5.2.5.1.
Flip flop design ................................................................................... 52
5.2.5.2.
Clock generator ................................................................................... 53
5.2.5.3.
Comparator control logic .................................................................... 53
5.2.5.4.
Switch control logic ............................................................................ 55
5.2.5.5.
Dynamic threshold comparison .......................................................... 56
5.2.5.6.
Digital calibration circuits ................................................................... 57
Chapter 6
Simulation results ................................................................................... 60
6.1. Prototype Performance ..................................................................................... 60

6.1.1.
Dynamic performance ............................................................................ 60
6.1.2.
Static performance .................................................................................. 61
6.1.3.
Performance summary and comparison ................................................. 61
Chapter 7
Conclusion and future work .................................................................. 64
7.1. Conclusion ........................................................................................................ 64

7.2. Future work....................................................................................................... 65
Bibliography ................................................................................................................. 66
List of figure
Figure 1-1. Basic construction of a projected capacitive touch panel [1] ........................ 2
Figure 1-2. Block diagram of touch panel ....................................................................... 2
Figure 1-3. FoM versus sampling frequency of state-of-the-art ADCs published at
ISSCC and VLSI Symposium [3] .................................................................................... 3
Figure 1-4. A plot of the resolution versus the input sampling frequency for recent
published analog-to-digital converters in ISSCC and VLSI [3] ...................................... 3
Figure 2-1. An example of 5-bit quantization using a binary search algorithm [3]....... 10
Figure 2-2. Basic block diagram of a SAR ADC [3] ..................................................... 12
Figure 2-3. Schematics of the charge redistribution SAR implementation [3].............. 12
Figure 2-4. Switching scheme of a conventional SAR ADC [3] ................................... 13
Figure 2-5. An example ADC transfer function for SAR ADCs with/without
capacitor mismatches [3]................................................................................................ 16
Figure 2-6. Effective number of bits (ENOB) versus normalized capacitor mismatch
in a 12-bit binary weighted SAR ADC [3]...................................................... 17
Figure 2-7. Schematic of a SAR ADC with offset errors [3] ......................................... 18
Figure 3-1: Binary search algorithm without redundancy. The search step sizes in
this example are binary weighted with values equal to 8, 4, 2 and 1 [3] ....................... 22
Figure 3-2: Comparison of using a traditional binary search algorithm (4-bit 4-step)
and a sub-binary search algorithm (4-bit 6-step) [3]...................................................... 24
Figure 3-3: Digital error correction using redundancy in SAR ADCs [3] ..................... 24
Figure 3-4: Highlighted error tolerance windows (
) for a sub-binary search SAR
ADC [3] .......................................................................................................................... 26

Figure 3-5: Transfer functions for SAR designs with step sizes that are binary,
subradix-2 and super-radix-2 weighted [3] .................................................................... 25
Figure 3-6: Illustration of Dynamic Threshold Comparison technique ......................... 26
Figure 3-7: Effective number of bits (N) versus number of steps (M) for different
radices () [3] ................................................................................................................. 28
Figure 3-8: The maximum radix and the minimum number of conversion steps [3] . 30
Figure 4-1. The superposition property of linear system [27] ....................................... 34
Figure 4-2: The perturbation of a linear SAR ADC (with optimal bit weights). [27] ... 36
Figure 4-3: The perturbation of a nonlinear ADC (with error in the MSB bit weight
only). [27] ....................................................................................................................... 36
Figure 5-1: The architecture of overall ADC ................................................................. 41
Figure 5-2: SAR ADC architecture ................................................................................ 42
Figure 5-3: The block diagram of the perturbation-based background digital
calibration. ...................................................................................................................... 42
Figure 5-4: Conventional SAR switching algorithm, showing energy consumption
related to capacitor switching transitions [3] ................................................................. 44
Figure 5-5: The top-plate waveform when using the conventional switching
algorithm [3]................................................................................................................... 44
Figure 5-6: The top-plate waveform when using the monotonic switching algorithm
[3] ................................................................................................................................... 46
Figure 5-7: Monotonic switching algorithm [3] ............................................................ 47
Figure 5-8: Comparing energy consumption of different switching algorithms [3] ...... 48
Figure 5-9: Bootstrap switch in [38] .............................................................................. 50
Figure 5-10: Dynamic comparator with a current source. ............................................. 51
Figure 5-11: The schematic of the preamplifier............................................................. 52
Figure 5-12: Split-output True Single Phase Clock (TSPC) Flip Flop .......................... 53
Figure 5-13: Clock generator a) Schematic. b) Timing diagram ................................... 54
Figure 5-14: Comparator control circuit a) Schematic. b) Timing diagram .................. 55
Figure 5-15: DAC Control Logic ................................................................................... 56
Figure 5-16: Dynamic threshold comparison circuit ..................................................... 57
Figure 5-17: Block diagram of the inner product block................................................. 58
Figure 5-18: Block diagram of LMS bloc ...................................................................... 58
Figure 6-1: The measured output spectra of the SAR ADC .......................................... 61
Figure 6-2: The measured DNL and INL of the SAR ADC .......................................... 62
List of table
Table 1-1. Current state-of-the-art SAR ADCs ............................................................... 7
Table 5-1: Comparison of different switching schemes in terms of various figures of
merit [3] .......................................................................................................................... 48
Table 5-2: DAC capacitors value ................................................................................... 49
Table 6-1: Comparison of the state-of-the-art works ..................................................... 62
Introduction
Chapter 1
Introduction
In this chapter, the structure of touch panel and all the metrics of an ADC
will be discussed. After studying carefully about these things, the design target will
be created. The chapter is organized as follow. In section 1.1, the structure and
operation of a most common capacitive touchscreen will be described. Section 1.2
will discuss the reason why the SAR architecture is selected. Section 1.3 describes
the fundamentals and performance metrics. The motivation of the proposed ADC
will be explained in section 1.4, and finally, the target specifications will be
described in section 1.5.
1.1. Structure of Projected Capacitive Touch technology with

mutual capacitive approach
Projected Capacitive Touch (PCT; also PCAP) technology is a variant of
capacitive touch technology. All PCT touch screens are made up of a matrix of rows
and columns of conductive material as in Figure 1-1.
There is a capacitor at every intersection of each row and each column. A
voltage is applied to the rows (or columns) periodically. Bringing a finger or
conductive stylus close to the surface of the touch panel changes the local
electrostatic field which reduces the mutual capacitance. This will result in the
decrease of the voltage of the column. The capacitance change at every individual
point on the grid can be measured by measuring the voltage in the other axis. This
voltage will be digitalized by an ADC and the output code will be sent to processor
to accurately determine the touch location. Mutual capacitance allows multi-touch
operation where multiple fingers, palms or styli can be accurately tracked at the
same time. [2]
1
Introduction
Figure 1-1. Basic construction of a projected capacitive touch panel [1]

Grid
TX Drive
Processor
ADC
RX Sense
Figure 1-2. Block diagram of touch panel
1.2. Architecture Selection

At very first step of the design process, a survey on performance of various
types of ADC is necessary for determining the most suitable type of ADC for the
target application. The typical requirements of an ADC in touch panel applications
in resolution, speed and power consumptions are 10-12 bits, few hundred kS/s and
few microwatts, respectively. A widely survey of recent published analog-to-digital
converters in ISSCC and VLSI [3] is used to compare the resolution, energy
efficiency and sampling frequency range among various types of ADC. From
Figure 1-3 and Figure 1-4, with high energy efficiency, medium to high resolution
and low to medium sampling frequency, successive approximation register (SAR)
ADC is the best candidate for the target application.
Introduction
Figure 1-3. FoM versus sampling frequency of state-of-the-art ADCs published

at ISSCC and VLSI Symposium [3]
Figure 1-4. A plot of the resolution versus the input sampling frequency for
recent published analog-to-digital converters in ISSCC and VLSI [3]
1.3. Performance Metrics of SAR ADCs

After ADC architecture is selected, to determine the target specification, it is
important to understand the fundamentals of the technical terms that define the
performance of a SAR ADC.
Introduction
1.3.1. Resolution
The resolution represents the number of digital output code, N, of the ADC.
Resolution determines the step size of the least significant bit as in Equation 1.1,
where N is the resolution of the ADC, and
represents reference voltage.

(1.1)
1.3.2. Quantization Noise

In a SAR ADC, the full scaled analog input is quantized by a total of
steps, each step is equal to 1 LSB. Due to rounding error, the difference between the
actual analog input and the quantized digital output is defined as the quantization
noise (error) which is derived as Equation 1.2.
(
(1.2)
1.3.3. Differential Nonlinearity (DNL) and Integral Nonlinearity (INL)

In SAR ADC, the magnitude of each analog output step of the DAC is equal
to one LSB. The differential nonlinearity (DNL) expressed in Equation 1.3 is the
deviation of each analog step away from one LSB. Integral nonlinearity (INL)
represents the linearity of the ADC by measuring the distance of the code centers in
the A/D converter characteristic from the ideal line (drawn from zero point to full
scale point of the transfer function). INL can be calculated as the cumulative sum of
DNL from
code (
) to (
), as shown in Equation 1.4.
code (
((
)
( ))
(1.3)
(1.4)
1.3.4. Signal-to-Noise Ratio (SNR)

Signal-to-noise ratio (SNR) is the ratio of rms value of the full scaled
sinusoid input signal to the rms value of quantization noise. It is calculated by
Equation 1.5, where N is the resolution. For an ideal 12-bit ADC, the maximum
SNR is 74dB.
4
Introduction
(1.5)
1.3.5. Effective Resolution

Not only quantization noise, other non-idealities and practical errors also
degrade the SNR which is represented by the term of effective number of bits
(ENOB), as defined in Equation 1.6.
(
)
(1.6)
1.3.6. Figure of Merit (FoM)

The Figure of Merit (FoM) defined as Equation 1.7 is the widely adopted
term to evaluate the overall performance of different types of ADC by normalizing
power consumption (
) with input frequency (
) and ENOB.
(1.7)
1.4. Motivation
As describe in section 1.1., the change in mutual capacitance at every
individual point can be measured by determining the voltage change at the other
axis. To make this voltage change large enough about several millivolts, the voltage
that is apply in one axis must be quite large, about 18 volts. This make the power
consumption of the touch panel become very large. To deal with this problem, there
is one way that if the resolution of the ADC becomes large enough, the voltage
change that we need can be reduced and the applied voltage will be not so high as a
result.
The biggest challenge in designing a high linearity is the DAC capacitors
mismatch error, which is the typical dominant factor that limits static linearity in a
switched-capacitor SAR ADC. To overcome this problem, the implementation
utilizes sub-radix-2 redundant architecture combined with digital background
calibration engine. The redundancy gives chances to reduce area of the DAC circuit
as well as improve the performance of switched-capacitor SAR ADC. It does not
only guarantee digitally correctable static nonlinearities of the converter but also
5
Introduction
offer means to combat dynamic errors in the conversion process. A perturbationbased digital calibration technique is also applied to accomplish simultaneous
identification of multiple capacitor mismatch errors of the ADC, enabling the
downsizing of all sampling capacitors to save power and silicon area.
1.5. Target Specifications

Before defining the target specifications, it is worthwhile to visit some of
other state-of-the-art SAR ADCs (shown in Table 1.1), which have quite the same
typical specification requirements of an ADC in touch panel applications (operate
with sampling frequency range of several hundred kS/s, resolution around 10 bits or
larger and power consumption in the range of few microwatts to few tens of
microwatts).
The target specifications for the SAR ADC are to operate with a voltage
supply of 1.8V at sampling rate of 100kS/s, the ENOB needs to be greater than 11
bit while total power consumption less than 60 W. This leads to a FoM of
293fJ/Conversion step.
1.6. Thesis contributions

This work focuses on design of high precision and power efficient SAR
ADC. The materials in chapter 2, chapter 3 and chapter 4 are mainly taken form [3]
and [4]. The main contributions are the proposed calibration circuit to save
hardware resource and power, the reuse of main DAC to implement Dynamic
Threshold Comparison (DTC) to save the area and increase the error tolerance of
the circuit.
This thesis is organized as follows. In chapter 2, the overview of traditional
SAR ADC will be presented. Chapter 3 and chapter 4 will introduce about
redundancy SAR ADC and perturbation based calibration algorithm respectively.
The design implementation will be discussed in details in Chapter 5. Chapter 6 will
demonstrate the simulation results. Finally, the conclusion, and future work will be
drawn in Chapter 7.
Introduction
Ref
[4]
[5]
[6]
[7]
This work
Year
2011
2013
2007
2013
--
Source
JSSC
TCAS2
JSSC
JSSC
--
Technology
0.13m
0.35m
0.18m
65nm
0.18m
Supply (V)
1.2V
2.3V
1V
1.2V
1.8V
Resolution (bit)
12
12
12
14
12
Fs (MS/s)
22.5
0.25
0.1
80
0.1
ENOB (bit)
11.3
11
10.5
11.9
11
Total Power (mW)
0.107
0.025
31.1
0.06
FOM (fJ/C-S)
51.3
209
165
164.7
293
Table 1-1. Current state-of-the-art SAR ADCs
Overview of Traditional SAR ADCs
Chapter 2
In previous chapter, the structure of projected capacitive touch technology was

introduced. Depend on the requirement (high resolution but low power
consumption) of the ADC for touch panel, the SAR architecture was selected
among various types of ADC due to its energy-efficient switching and digital
scalability with technology. After presenting about performance metrics of SAR
ADC, the motivation of this work and studying some of other state-of-the-art SAR
ADCs performance, the target specification was determined.
In this chapter, the operation of a traditional SAR ADC will be analyzed.
First, the Binary Successive Approximation Algorithm search algorithm for
Nyquist-rate ADCs is introduced. The implementation and operation of a SAR
ADC will be discussed in the second part of this chapter. Due to the non-idealities
of the circuit components, errors will occur during the conversion process; these
errors limit the achievable speed and accuracy of a SAR ADC. The final part of this
chapter focuses on analyzing these errors. Based on the sources of these errors, they
are broken down into static and dynamic parts.
2.1. Binary Successive Approximation Algorithm

In binary successive approximation algorithm, one bit is resolved at a
time. The first bit is generated by comparing the input to the mid-full-scale-level of
the current search range. Depend on the comparison result, half of the search range
is eliminated and the same process continues until the entire conversion is
completed. Instead of using one clock cycle per conversion, this algorithm requires
N clock cycles and thus, N comparisons to complete a conversion.
9
10
An example of a 5-bit quantization of input 6.2 using binary successive

approximation search is shown in Figure 2-1. The mid decision level of the current
search range is represented by the solid black lines while the solid red line indicates
the location of the input level. At the beginning of the process, the search range is
full scale from 0 to 31. During the first comparison,
(equal to 6.2) is compared
with the mid-full-scale level of the initial search range. Since 6.2 is less than 16, the
first output bit of ADC is '0' and the upper half of previous search range is
eliminated. The searching process continues until the final binary output 00110 is
produced after five clock cycles. In the last search, the range of uncertainty is
reduced to one LSB, resulting in quantization error within
Figure 2-1. An example of 5-bit quantization using a binary search algorithm

[3]
Binary conversion is quite sensitive to errors made during the conversion
process. In an ideal binary implementation, none of the search ranges overlap.
Therefore, once a search range is eliminated from the search process, it can never be
reentered, so if an error is made, the correct search range cannot be recovered or
returned and thus the digital output can never be corrected. As a result, to produce
correct digital outputs, each conversion step need to be accurate and correct, this is
so difficult to accomplish in practice. Traditional SAR ADCs use the binary search
10
11
algorithm; however, in a later chapter, it will be shown that digital error correction
(or redundancy) can be used to greatly alleviate this problem.
2.2. The SAR Architecture

The SAR architecture performs the A-to-D conversions over multiple clock
cycles by using the value of the previous determined bit to assist in finding the next
significant bit. A typical block diagram of a SAR ADC is shown in Figure 2-2. It
involves four basic building blocks: sample and hold (S&H), DAC, SAR control
and comparator. In the conversion process, each block plays a different role: the
S&H samples one instance of the continuous analog input signal during the first
clock period and holds this value for the remaining conversion process, the
comparator generates each bit by comparing
with
and depend on the
output bits of the comparator, the SAR control reconfigures and updates the DAC.
An effective implementation of the DAC is the so-called charge
redistribution or capacitor array scheme [8, 9]. In this implementation, the
capacitive DAC performs both sample/hold function and subtractions in the charge
domain using capacitors. At the end of the conversion process, the charge is
properly re-distributed such that the top plate voltage on the DAC is approximately
the same as the voltage on the other input of the comparator ,which is zero in case
depicted in Figure 2-3. The SAR consists of an N-bit binary-weighted capacitive
DAC, a SAR control logic block and a comparator. Each capacitor within the DAC
can be re-configured by connecting it to either the input or the plus/minus reference
voltages. The total capacitance sums up to
, where
(2.1)
During the sample and hold phase, the input signal is sampled at the bottom
plates of the DAC array by connecting them to the input and the top plate of the
array to ground (Figure 2-4(a)). The total charge stored in the array is
(
(2.2)
11
12
Figure 2-2. Basic block diagram of a SAR ADC [3]
Figure 2-3. Schematics of the charge redistribution SAR implementation [3]

The conversion phase is begun after the sampling phase. During the first
step, the most-significant-bit (MSB) capacitor is connected to
remaining capacitors are connected to
while the
(Figure 2-4(b)). For simplicity, in this
example, it is assumed that
and
. Using the charge
conservation principle, the voltage on the top plate of the array,
, becomes
(2.3)
In Equation 2.3, the first input sampling contributes to the first term and the the
MSB capacitor contributes to the second term. By comparing
the first output bit
next bit calculation.
can be determined and the configuration is set for the

stays connected with
will be switched to ground for the remaining cycles if

is switched to
directly to ground,
only if
and it
. After that,
. Figure 2-4(c) and Figure 2-4(d) show two different
configurations, respectively. The top plate voltages of the two configurations can be
12
13
Figure 2-4. Switching scheme of a conventional SAR ADC [3]

calculated by Equations 2.4 and 2.5. The process of comparing and reconfiguring
continues until the last bit is obtained.
(
(2.4)
13
14
(2.5)
At the end of the conversion, the input is converted into binary-weighted bit
sequences, [
], and the final voltage on
is
(2.6)
This voltage represents the quantization error of the entire conversion

process. Note that both the top and bottom plates of the DAC can have parasitic
capacitances contributed from non-ideal layout/wiring, gate capacitance of
comparators... The parasitic capacitances on the bottom plate are driven by low
impedance reference voltage supplies,
and
. Therefore, these will not
affect the conversion process if the reference voltages are completely settled. On the
other hand, the parasitic capacitance on the top plate decreases the amplitude of
sampled input. The attenuation factor can be calculated as
(2.7)
where
is the total parasitic capacitance on the top plate. This attenuation reduces
the effective signal power, but does not change the polarity of the comparison
result, thus will not affect the correct output bits. The bottom-plate sampling
essentially enables this feature. In the sampling phase, the top plate is connected to
ground before the node becomes floating until the end of the conversion phase.
During the conversion, the voltage on the top plate changes but returns to a voltage
that is near zero at the end of the process. As a result, the total charge on
at the
beginning and at the end of the process is the same and therefore, from the
perspective of charge, capacitor
does not cause any charge error. Thus, it will not
affect the overall accuracy of the conversion process.

In summary, using a charge redistribution scheme in a SAR ADC has a lot of
advantages. It is energy efficient and only has dynamic but no DC power
consumption, if no pre-amplifier is used in the comparator design. The ADC is
robust against circuit non-idealities, such as parasitic capacitances. The architecture
is less limited by technology and supply voltage scaling compared to other
14
15
architectures since most parts of the ADC are digital, not analog. It also has the
potential to take full advantage of improved energy efficiency and speed in deeplyscaled CMOS. A correctly implemented SAR ADC typically supports full rail-torail input range, which can be advantageous for high-resolution designs. Lastly,
since the sampling capacitors are shared with the configurable DAC, SAR ADCs
can save significant areas and result in small chip area.
2.3. Static Error Sources in SAR ADCs

Even with all the architectural benefits discussed in the previous section, the
static performance of converter (measured by metrics: differential nonlinearity
(DNL), integral nonlinearity (INL), offset error and gain error) is still limited by the
matching of analog components by many ways, for example, mismatches in the
capacitive DAC can lead to incorrect charge distribution during the conversion
phase; mismatches in transistors can lead to offset errors in the comparator
2.3.1. Capacitor Mismatches

Good capacitor matching is the key for high accuracy ADCs. It is controlled
and influenced by manufacturing processes and physical design. The variation
sources can be divided into random statistical fluctuation and systematic
mismatches. Random mismatches include the difference in device dimensions, wire
sizing, doping, oxide thickness ... of practical value from desired value. These types
of mismatches cannot be completely eliminated. Typically, the solution for this is to
increase the overall dimension or to use special layout technique to improve
matching. Systematic mismatches results from temperature gradients, diffusion
interactions, mechanical stresses, biases in the processing steps... Even though some
of these mismatches sources can be combated by using careful design and layout, it
is still difficult to attain more than 10 bits of resolution.
When capacitors within the DAC are perfectly matched in a SAR ADC, the
input/output transfer function resembles a straight dotted line in Figure 2-5. This
implies linear mapping between the inputs and the outputs. Since all the steps have
equal size and they are evenly spaced over the full range, this 12-bit example is free
of any DNL and INL errors.
15
16
Figure 2-5. An example ADC transfer function for SAR ADCs with/without
capacitor mismatches [3]
On the other hand, when mismatch errors are present, the transfer function
deviates from the straight line as shown by the solid blue curve in Figure 2-5.
Misalignments occur in both the vertical and horizontal directions. Misalignment in
the vertical direction creates missing codes, which makes the DNL exceeds -1.
Misalignment in the horizontal direction creates missing levels, which implies that
some part of the original analog information is lost. Typically, missing codes are
digitally correctable while missing levels are not. As a result, ADCs should be
designed to avoid missing levels. More details on digital calibration, one effective
way to deal with capacitor mismatches, will be discussed in Chapter 3 and 4. Figure
2-6 shows the plot of ENOB versus the standard deviation of the unit capacitor [3].
It can be seen that even at 1% standard deviation in
, the ENOB can be degraded
by more than 1 bit without taking into consideration other non-idealities in the
design. Therefore, control and calibration for the mismatches in capacitors play a
key role in high-resolution design.
16
17
Figure 2-6. Effective number of bits (ENOB) versus normalized capacitor

mismatch
in a 12-bit binary weighted SAR ADC [3]
2.3.2. Offset Errors

The offset error in a SAR ADC only causes a linear shift in the transfer
function, but does not cause linearity problems since the error is signal-independent.
There are two sources of offset. The first offset comes from charge injection of the
sampling switches. At the sampling instance, the switch turns off and the charge
stored in the gate-to-channel capacitors is injected onto the top plate of the DAC.
By employing bottom-plate sampling, the amount of charge injected onto the plate
is mostly constant and independent of the input signal, at least to the first-order
estimation. The second source of offset errors in a SAR ADC is the offset of the
comparator, which is also signal-independent for two reasons. First, different from
some other architectures (the flash ADC), only one comparator is used repeatedly
during the conversion phase. Hence, only the offset of that comparator affects the
operation. Second, independent of input voltages, the top plate always returns to
zero at the end of the conversion phase. Therefore, the input common mode voltage
of the comparator at the end of the conversion phase is the same regardless of the
input signal, and thus, the offset voltage is always the same.
17
18
The residue at the end of the conversion given by Equation 2.8 shows that
the additional terms introduced by offset voltages do not depend on the input
voltage,
.
(2.8)
Figure 2-7. Schematic of a SAR ADC with offset errors [3]
2.4. Dynamic Error Sources in SAR ADCs

When analyzing the static error sources, it is assumed that during the SAR
operations, each conversion is given enough time for
to completely settle within
the necessary resolution. In reality, conversion errors can occur because the
comparator makes its decision before
settles adequately. Since traditional SAR
ADCs uses binary search in which each analog input always maps to one distinct
digital output code, errors made during the conversion process cannot be recovered
at the end of the search process. As a result, it is essential that each comparison is
made correctly during the conversion process to ensure correct operation. The RC
settling of the DAC determines the minimal time that needs to be allocated for each
conversion step and therefore also determines the maximum operation speed of the
ADC. The required time for an N -bit ADC to settle within
Equation 2.12, where
is given in
is the total resistance of the switches and
is the total capacitance of the DAC. To improve speed of SAR ADCs, small
and
should be used in the design.

18
19
(2.9)
(
(2.10)
As in defined specification in chapter 1, the sampling rate of SAR ADC in

this work is very low, only 200ks/s, therefore the dynamic error will not affect the
performance of target SAR ADC.
19
20
21
Redundancy SAR ADCs
Chapter 3
Redundancy SAR ADCs
In chapter 2, the operation as well as the structure of a traditional binary weighted
SAR ADC is discussed. Even though it has many architectural advantages, such as
its efficiency in terms of conversion steps, energy efficiency, small chip size,
amenability to digital scaling, and ease of implementation, its resolution and speed
are still limited by a few key design challenges that need to be resolved. Since the
target designed SAR ADC has the sampling frequency very low, only 100ksps, only
capacitor mismatches but not the incomplete reference voltage settling due to high
switching activities is the main linearity and performance limiting factors.
In this chapter, we introduce and analyze the redundancy algorithm in SAR
ADCs and background digital calibration to see how it can help mitigate the
limitation discussed previously. The chapter is begin by giving a conceptual
overview of SAR redundancy and discussed its benefits in terms of achievable
resolution over the traditional binary search algorithm. It will be shown that having
redundant bits provides the extra leverage during the search process so that
conversion errors in the earlier steps can be corrected later and redundancy can
provide the necessary digital calibratability to calibrate out the mismatches in the
capacitor array. The expected random mismatches within the capacitors determine
the amount of redundancy that is necessary to cover this variation. The relationship
between the two parameters is analyzed.
3.1. Redundancy Overview

As described in Chapter 2, in a binary search process, no conversion errors
can be tolerated because for every analog input value, there is a unique
corresponding digital output code. Once a decision error is made, due to its one-to21
22
Redundancy SAR ADCs
one mapping property, the ADC cannot recover and produce the correct output
codes. This is shown clearer in Figure 3-1. In the plot, the decision levels, search
range, and search sequence for a 4-bit binary-weighted SAR ADC are highlighted.
The x-axis indicates the sequences of binary search and the y -axis shows the full
search range. In the plot, since none of the ranges within the same search cycle
overlaps, once a range is eliminated during the searching process, the range is
dropped from the search procedure and it will never be reconsidered again. This
confirms the previous conclusion that errors made during the conversion process
cannot be corrected in a binary search.
Figure 3-1: Binary search algorithm without redundancy. The search step sizes
in this example are binary weighted with values equal to 8, 4, 2 and 1 [3]
Although the binary search presented in Figure 3-1 has no error tolerance
capability, it suggests that if the search ranges within the same cycle do overlap, the
already dropped search range can potentially be recovered to produce the correct
digital output. To create overlapped search ranges, a less than radix-2 (sub-radix-2)
search is needed. Essentially, a sub-radix-2 search needs more than N steps to
convert an analog input into a N-bit digital output. Even though this search
22
23
Redundancy SAR ADCs
algorithm is less efficient in terms of the number of steps required to reach a certain
resolution, it provides room for the necessary error tolerances to boost the
robustness of the overall operation. The two search algorithms is compared in
Figure 3-2. Here, s(i)'s represent the step sizes during the search process. In an N-bit
binary weighted algorithm, there are N steps s(i)'s with binary weighted values
, where i is between 0 and
. On the other hand, a redundancy SAR ADC
requires M steps to realize N-bit digital output, where M > N. For example, in
Figure 3-2, the binary case only requires four steps with binary weighted s = [8; 4;
2; 1], while the sub-binary case requires six steps with s = [8; 2; 2; 1; 1; 1] to
achieve the same resolution. The total steps s is 15 in both cases, implying that the
two algorithms have identical search range. The final digital output for an N -bit M
-step ADC can be calculated using Equation 3.1.
( )
where
()
- ()
, ( )
(3.1)
is the final digital output expressed in decimals, b[n] is the
digital
output bit, N is the effective resolution and M is the total number of steps. In this
example, the extra two steps is added to the original binary search to provide error
tolerance. An example demonstrating this error resilience is given in Figure 3-3.
The left-most plot shows an ideal example where all decisions are made correctly;
the middle plot shows an example where a decision error is made in the rst step and
finally, the right-most plot shows an example in which a decision error is made in
the second step. For
= 6.2, each of these above cases gives different digital
output bit sequences: [010010], [100010] and [100010], respectively. Their digital
outputs is calculated by using Equation 3.1 and they all result in the same Dout (=
6) as shown in Equation 3.2, 3.3 and 3.4. This demonstrates that redundancy has the
capability to digitally realize correct oputput code for at least some bit decision
errors.
,
)
(
(
)
)
(
23
(
)
)
(
(3.2)
24
Redundancy SAR ADCs
)
(
(
)
)
(
)
(
(
)
(
)
)
(
)
(
(
)
(3.3)
)
(
(3.4)
Figure 3-2: Comparison of using a traditional binary search algorithm (4-bit 4step) and a sub-binary search algorithm (4-bit 6-step) [3]
Figure 3-3: Digital error correction using redundancy in SAR ADCs [3]
24
25
Redundancy SAR ADCs
3.1.1. Error tolerance windows for redundancy

The redundancy only provide limited amount of error tolerance for SAR
algorithm. During the conversion process, if the decision errors are too large, even
with redundancy, the errors still cannot be recovered and the digital outputs will be
incorrect. For each conversion step, a range of recoverable analog voltage can be
highlighted around the decision level. This implies that during the transition, if an
analog voltage falls within this range and error is made, the ADC can recover from
the errors if there are no mistakes in the rest of the conversion process. This error
tolerance window is denoted as
. For the
output bit,
(n) can be calculated
according to Equation 3.5.

( )
()
(3.5)
As an example, Figure 3-4 shows a redundant SAR ADC with s = [8; 2; 2; 2; 1].
For the 5th output bit, the error tolerance window is given by Equation 3.6.
( )
( )
( )
( )
( )
The formula 3.5 can be intuitively understood as follows. For the
(3.6)
output
bit, the next decision level will either move up or down by the step size of s(n-1)
once a decision is made. If erroneous occurs, then the sum of the follow-on step
sizes, s(n-2); s(n-3):; s(1), must be large enough and exceed the value of the
current step size to correct this mistake. That exceeded amount is the tolerance
window for that decision level.
Figure 3-4: Transfer functions for SAR designs with step sizes that are binary,
subradix-2 and super-radix-2 weighted [3]
25
26
Redundancy SAR ADCs
Figure 3-5: Highlighted error tolerance windows ( ) for a sub-binary search

SAR ADC [3]
3.1.2. Dynamic Threshold Comparison
Error-tolerance
window
Error-tolerance
window
Middle range
Middle range
Input voltage
temporary shift
Input voltage
Figure 3-6: Illustration of Dynamic Threshold Comparison technique

From previous section, it can be seen that if an input voltage falls inside
error-tolerance window, the decision error can be corrected in later steps. To further
improve the error resilience of SAR ADC, Dynamic Threshold Comparison
technique [4] will be utilized. The main idea of this technique is if the input voltage
sits outside the error-tolerance window, it should be temporary shift into this
window to exploit the error resilience of the redundancy. Therefore, this technique
26
27
Redundancy SAR ADCs
provides extra error tolerance capability for the ADC with the input voltage outside
error window. In other words, the range of window is enlarged when DTC
technique is applied. Note that by utilized DTC technique, the error-tolerance
window does not increase unlimited, the amount of range extension will depend on
the way of implementation of this technique in SAR ADC.
3.2. Digital calibratability

The previous section discussed about how dynamic conversion error can be
resolved by using redundancy. In chapter 2, it can be seen that the dominant error
source of the target ADC is capacitors mismatches, which lead to mismatches in the
searching steps, s(n). In the section, the condition of digital calibratability in the
presence of static mismatches in capacitors will be explored.
3.2.1. Condition of digital calibratability

Figure 3-5 shown three transfer functions which represent 3 different cases.
Figure 3-5 (a) shows the ideal case of transfer function in which the analog input is
linearly mapped to digital output code. Figure 3-5 (b) shows the case that the MSB
step size smaller than its nominal value, which is referred as the sub-radix-2 search
and Figure 3-5 (c) has the MSB step size larger than its nominal value, which is
referred as the super-radix-2 search. In a super-radix-2 search, a horizontal
misalignment (missing level) appears in the transfer function. In this case, the
analog information is lost since multiple analog inputs are mapped to the same
digital output code and the errors cannot be corrected digitally. In contrast, in a subradix-2 search, vertical misalignments (missing codes) appear in the transfer
function. In this case, more than one digital output codes could potentially be
mapped to one analog input while some of the digital output codes never show up
during normal operations. In contrast to previous case, since the analog information
is not lost, the error is digitally correctable in this case. The large vertical jump is
embodied in the redundant search algorithm. By designing step size s(N)
intentionally smaller than the sum of the remaining s(n), digitally correctable codes
can be created. By extending this idea into every search step in the sub-binary
search, redundancy can be built into all decision levels
27
28
Redundancy SAR ADCs
()
( )
(3.7)
where i = 1; 2;; N . There will be no missing levels and all static errors are
digitally correctable as long as all decision levels satisfy Inequality 3.7.
3.1.2.2.
Amount of redundancy
As discussed in the previous discussion, whenever Inequality 3.7 is satisfied,

redundancy is built into the search algorithm. To achieve this inequality, one simple
way is choosing a fixed radix that is less than 2. Even though the design is
originally built to satisfy Equation 3.7, the added variation in the search steps
resulted from random manufacturing variation of capacitors can break this
relationship and create missing levels that are not digitally correctable. In this
section, a relationship that determines the amount of redundancy needed to
guarantee Inequality 3.7 with respect to different amounts of DAC capacitance
variation will be established.
Figure 3-7: Effective number of bits (N) versus number of steps (M) for
different radices () [3]
28
29
Redundancy SAR ADCs
When the ADC is designed with a fixed radix, , the following relationship
is obtained
()
(
(3.8)
where i = M-1; M-2;; 1. The effective number of bits, N, can be calculated using
Equation 3.9
(3.9)
( )
where
is the sum of all the step sizes, N is the effective number of bits and M is
the total number of conversion steps. Figure 3-7 shows that although converters
with smaller radix, , require more steps to achieve the same resolution as the
converters with larger radix, they are more resilient against both dynamic and static
conversion errors.
3.1.2.3.
Radix and number of steps
In order to incorporate redundancy to provide the capability to digitally

calibrate for static random mismatches, Inequality 3.7 must be satisfied at all times
even with the presence of variation. Due to manufacturing variation, random
variation in capacitor size is unavoidable. Since the step sizes (s(M ); s(M-1);;
s(0)) are proportional to the capacitor sizes (
;;
), Equation 3.7 can be
re-written as follows
(3.10)
where
is the desired (or designed) relationship between the
capacitances in the DAC. Manufacturing variation in
's can break this
relationship. In this section, the appropriate radix number and the number of steps
such that Inequality 3.10 is satisfied with high probability, even in the face of
variation will be found.
A plot of maximum radix and the minimum number of conversion steps
needed for a given amount of capacitor mismatches in a 12-bit ADC is shown in
Figure 3-8 [3]. From this figure, it can be seen that when the variance of capacitor
29
30
Redundancy SAR ADCs
is 0%, = 2.0 and M = 12; this corresponds to the classic non-redundant binary
search ADC case. On the other hand, in this implementation, it is estimated that
is
about 7%, then = 1.86 and M = 14 are obtained.
Figure 3-8: The maximum radix and the minimum number of conversion
steps M versus the standard deviation of the unit capacitor, in order to achieve
digital calibratability in a 12-bit ADC [3]
30
31
32
Digital Background Calibration of SAR ADCs
Chapter 4
Digital Background Calibration of SAR
ADCs
In Chapter 3, the redundancy algorithm in SAR ADC was introduced. If

implemented correctly, redundancy can provide error tolerance for the ADC during
the conversion process. To ensure digital calibratability in the presence of
capacitors mismatches, some requirements on redundancy are needed. The
requirements can be expressed in a simple relationship between the maximum radix
number, the minimum total number of conversion steps and the expected
manufacturing random variance of capacitors. From this relationship, the total
number of steps and the radix number for the target ADC were chosen.
In this chapter, to take another step towards designing higher resolution SAR
converters, a digital background calibration schemes that can utilize the redundant
information to digitally remove the nonlinearity is provided.
4.2. Overview of digital calibration in SAR ADC

Without trimming or calibration, static nonlinearities usually limit the
resolution of SAR ADC from going above 8-10 bits [10]. To alleviate effect of
nonlinearities on SAR performance, a lot of new calibration techniques to achieve
designs with higher accuracy have developed. For example, Li et al. in [11] came up
with a ratio-independent algorithmic technique, and Song et al. in [12] proposed a
capacitor error averaging technique to achieve exact multiplication by a factor of
two regardless of capacitor mismatch error in a pipelined ADC. The most common
of these techniques [11-16] is that they use analog components in the signal path to
remove static nonlinearity. Although they are quite effective in removing static
32
33
nonlinearities in the design, these techniques typically degrade conversion speed

and add circuit noise. The circuit noise based FoM degradation is roughly 12X and
9X in [11] and [12], respectively.
Besides, digital calibration techniques, which can realize the benefit of
technology scaling, have also been developed. They can be divided into two groups:
foreground calibration and background calibration. In foreground calibration, the
calibration is done during a calibration phase at startup and nonlinearity is measured
by driving the inputs with specific calibration signals to extract the mismatch
information. For example, Lee et al. in [17] developed a self-calibrated capacitor
array in a SAR ADC. The ratio errors of the capacitors will be extracted
sequentially from the MSB capacitor to the LSB capacitor during calibration. The
mismatch data stored in a RAM is used to correct matching errors of the capacitor
array during the normal operation. Other calibration schemes extract nonlinearities
by using statistically-based methods [18, 19]. These calibration schemes interrupt
the normal operation of the ADC since they require collection of measurement data
at the beginning of the operation. To minimize the effect, these calibration schemes
are typical to run during manufacturing or at startup, so they cannot track parameter
drifts.
In contrast, digital background calibration does not interrupt the normal
conversion process since it runs transparently in the background. A common
approach is to inject a known calibration signal,
, onto the signal path [4], [20-
23]. With an ideal linear transfer function, an injected calibration signal

cause a constant shift of
(the corresponding digitized output of
independent of the input signals at the output. Therefore, when
will
) which is
is subtracted
from the final digitized output, the injected signal should have no correlation with
the output signal. The calibration engine is designed to null this correlation by
adjusting the calibration parameters. Using this approach, the signal range and the
over-range protection is reduced since the signal path must accommodate the
addition of the calibration signal.
Rather than tampering with the input signal path, another approaches
estimate the static errors by using the input signal itself instead of a calibration
33
34
signal [24-26]. Adaptive equalization techniques are used to resolve nonlinearity

problems for pipelined and SAR ADCs in [24,25] and [26], respectively. In these
techniques, an accurate reference ADC is typically used to estimate and correct the
errors. Even though the reference ADC may run at a slower speed compared with
the core ADCs, these techniques will increase power consumption or reduce in
conversion speed.
In this work, the perturbation based digital background calibration [4] and
[27] is used because of its simplicity and effectiveness as demonstrated in [4]. This
calibration algorithm will be discussed carefully in the next parts.
4.1. Superposition Principle

The superposition principle of a linear system is the soul of the perturbationbased digital calibration. In Figure 4-1, the SAR ADC is represented by an
operation Q(X), which maps analog samples to output digital codes. The ADC
respectively maps its input
and Q(
and
(the perturbation signal) to the output Q(
). Assuming ideal quantization, the Q(X) is a linear operation. Therefore,
using the superposition principle

(
(4.1)
Figure 4-1. The superposition property of linear system [27]

Denote (
) as
. Then the Equation (4.1) is rewritten as

(
)
( )
(4.2)
Equation (4.2) implies that the correct quantization value of input voltage
can be obtained by subtracting the perturbation signal in digital domain in a linear
A/D conversion. Equation (4.2) can also be intuitively explained as follow: adding
and
horizontally shifts the original transfer curve as in Figure 4-2(a),
while subtracting the output codes by
and
34
in Figure 4-2(b) vertically
35
shifts the transfer curve accordingly. If transfer curve is linear and all bit weights
are optimal, the two perturbed transfer curves line up with the original one,
assuming
. In reality,
is adapted so the injected
can be precisely
removed in digital domain.

However, in a nonlinear case the superposition property does not hold. For
example, considering the MSB bit weight error where the transfer curve distorts at
the transition from the digital code 0111 to the digital code 1000 and assuming
the other bit weights are optimal. In Figure 4-3(a) and (b), the same horizontal and
vertical perturbations respectively as Figure 4-2(a) and (b) is shown. The two
perturbed transfer curves in Figure 4-3(b) form a window with a horizontal size of
2
instead of aligning with the original one in this case. Each analog input can be
digitized twice using both of the dashed and dash dotted curves in Figure 4-3(a) and
(b) respectively. Therefore, when an analog sample falls in the window, two
different digital codes are obtained. The difference between them gives a chance to
observe the bit weight error. By adjusting the bit weights to obtain optimal ones, the
error (window) diminishes and the transfer curve is linearized. The superposition
property of the linear transfer curve holds again. A large
results in a wide
window, which provides a better opportunity to observe the error.

In general, every bit weight derails from its nominal bit weight so the
transfer curve is distorted at various locations, but the perturbation detects all of
them in the same mechanism as the MSB example above. [27]
4.2.
Perturbation-Based Calibration Algorithm

The perturbation-based digital calibration for a SAR ADC with N conversion
steps can be described as follow:

A single SAR ADC digitizes each analog sample twice. However, the two
quantizations are perturbed by analog offsets of
then two N-bit raw codes,
same bit weights, W={
and
and
respectively, and
, accordingly, is given at the output. With the
}, i=0, , N-1, (these bit weights represent conversion
step in chapter 3) the weighted sums
and
35
are obtained by
36
Figure 4-2: The perturbation of a linear SAR ADC (with optimal bit weights).
[27]
Figure 4-3: The perturbation of a nonlinear ADC (with error in the MSB bit
weight only). [27]
(4.3)
(4.4)
36
37
where
is the quantized input-referred offset, and the ratio between the
capacitor ( ) and the total capacitance (
) defines the
bit weight,
Equation (4.3) and (4.4) calculate the weighted sums of all bits of
and
. With
digitally subtracted, the error between the two conversions is
obtained by Equation (4.5),
where
and
(4.5)
are quantized versions of
desired value of
and
. Similarly the
is
(
(4.6)
where Q() is ideal quantization. Assuming optimal bit weights are learnt, Equation
(4.1) holds. Putting Equation (4.1) and
into Equation (4.6), a zero error is
obtained. The superposition property of the linear transfer curve shown in Figure 39 holds in this case. Otherwise, the non-zero error indicates the nonlinearity in the
transfer curve, as depicted in Figure 3-10. Plugging Equations (4.3) and (4.4) into
Equation (4.5) gives,
[ (
)]
(4.7)
Equation (4.7) is in the form of a generalized code-domain linear equalizer. Then, to

drive that
to 0, an LMS algorithm is applied by adjusting the N individual bit
weights and the
simultaneously using Equation (4.8) and Equation (4.9):

,
, -
,
where
and
, -(
, -
, -
, -)
, -
(4.8)
(4.9)
are the step sizes of the update equations. Eventually, the
calibration engine forces the error to zero in a least-mean-square sense. In steady

state, all optimal bit weights are learnt, the mean of
averaging) yields the correct digital output of
and
cancelled in
. In the double conversion both the
quantization noise and the comparator noise are reduced by 3 dB.
37
38
The perturbation based calibration only requires an analog offset injection.

Compare to a highly linear reference ADC required by the equalization-based
digital calibration [17, 24, 25], [28-30], the hardware overhead is negligible.
Although the dynamic range of the ADC is reduced by analog offset injection, it is
typically tiny compared to the full-scale range. Unlike the splitting-based calibration
where the generation of multiple decision paths and double routing are involved
[31], by adding only a pair of injection capacitors, this calibration requires
significantly lower circuitry complexity and less design effort. The deterministic
character and the zero-error-forcing nature of this calibration result in a much
shorter convergence time than the correlation-based ones [22, 32]. Although the
calibration reduces the conversion speed by half, the sampling rate of target ADC is
quite low, so this does not affect much to the ADC performance.
38
39
40
Design and Implementation of Redundancy SAR ADC with Digital Background

Calibration
Chapter 5
Design and Implementation of
Redundancy SAR ADC with Digital
Background Calibration
In Chapter 4, the perturbation based calibration algorithm that is able to utilize the
redundancy information to digitally correct output code was introduced. The
superposition principle in which the calibration is based on was explained first.
Then the calibration algorithm was described in details. From that, its advantages
and disadvantages compare to other algorithms also was discussed.
In this chapter, the real implementation of a redundant SAR ADC is
described. In the first part, the implementation at the architectural level will be
focused on. All the circuit blocks are combined and how all these blocks work
together is analyzed carefully. The next part of the chapter describes the design at
the circuit level with discussion of several new contributions. Firstly, DAC
switching scheme that is able to achieve higher energy efficiency than conventional
switching schemes will be presented. Secondly, some circuit blocks such as
bootstrapped switch, comparator, preamplifier will be described. A new way to
implement the dynamic threshold comparison which requires less area is proposed
in this part. And the last once, an enhanced digital calibration circuit which require
less hardware resource compare to [4] is introduced.
5.1. Architecture
The architecture of overall ADC is shown in Figure 5-1. Its operation can be
described as follow. A single SAR ADC digitizes each analog sample twice, with
40
41

Calibration
two analog offsets,
and
, resulting in two 14-bit raw codes,
respectively. Depend on values of
and
, the calibration engine will calculate

*
output d and update the new value of bit weights
SAR ADC
Vin
and
+.
D +, D -
Calibration
Engine
+a, -a
Figure 5-1: The architecture of overall ADC
5.1.1. SAR ADC architecture

Figure 5-2 shows the architecture of SAR ADC. Its operation can be
described as follow. At first, the ADC samples the input signal on the top plates via
bootstrapped switches, which increases the settling speed and input bandwidth. At
the same time, the bottom plates of the capacitors are reset to
. Next, after the
ADC turns off the bootstrapped switches, a perturbation signal
is added to the
input by connecting capacitor
to the ground. After that, the comparator performs
the first comparison without switching any capacitor. Depend on the comparator
output, the largest capacitor on the higher voltage potential side is switched to
ground while the other one (on the lower side) remains unchanged. Then, the
comparator continues comparing and the switch
or
will be closed. The
procedure is repeated until the LSB is decided and the raw 14 bit of
After that, all capacitors are reset to
. The process to generate
all procedure above is repeated except the perturbation

connecting capacitor
to the ground.
41
is obtained.
is begun. The
is added to the input by
42

Calibration
Vref
S12p S 11p S 10p
C 12 C 11 C 10
S 7p
C7
S 2p S 1p S 0p
C2 C1 C0 C0
C tp
V+
V i+
V iBootstrapped
switch
SAR
Control Logic
V-
preamplifier
C 12 C 11 C 10
S12n S 11n S 10n
C7
S 7n
C tn
C2 C1 C0 C0
S 2n S 1n S 0n
clk
Vref
Dynamic
threshold
comparison
Signal
injection
Figure 5-2: SAR ADC architecture
5.1.2. Calibration architecture

The block diagram of the calibration engine is shown in Figure 5-3. The
inner product block is used to calculate the weighted sum
from 14-bit raw code
. It is also utilized to calculate the difference between

raw code
and
). From this difference and value of
and
(from 14-bit
, we can obtain all other
important parameter such as output code d, bit weights W as in Equation (3.23)

and (3.24). This way of implementation will save a lot of hardware resource as well
as power compare to the implementation in [4] (1 inner product block, 1 subtractor
).
d+
SAR ADC
Vin
d+ - d w
+a, -a
d+ - d 2
2d
LMS
error
Figure 5-3: The block diagram of the perturbation-based background digital

calibration.
42
43

Calibration
5.2. Key circuit building block

5.2.1. Capacitive DAC Design
5.2.1.1.
Monotonic Capacitor DAC Switching Operation
In this part, Monotonic Capacitor DAC Switching algorithm will be

described. Although the implemented Capacitive DAC uses sub-radix-2 monotonic
switching algorithm, we will introduce this algorithm with binary weighted
capacitor for easy to understand and compare to other switching algorithms.
Conventional switching algorithm
In a SAR ADC, the DAC is used for 2 two purposes: sampling the input
voltage and generating error residues between the input and the current digital
estimate. The conventional SAR switching algorithm for a 3-bit ADC in a fully
differential implementation is shown in Figure 5-4; the top-plate waveform for a 6bit ADC using the conventional switching algorithm is shown in Figure 5-5. Even
though this switching algorithm is able to produce the correct logic operations, it
does not move the charges among capacitors efficiently, wasting energy during
operation.
The energy consumption of each transition in conventional switching
algorithm is shown in Figure 5-4. During the first phase, the differential inputs are
sampled onto the upper and lower arrays of the DAC. After that, they are
disconnected from the DAC at the end of sampling phase. The DAC is configured
by charging the MSB capacitor to
and the remaining capacitors to ground for
the top array and, the opposite is done for the bottom array. The total energy
consumption for this operation is
. The first output bit is produced by
comparing the voltage on the plus and minus nodes of the comparator. Then the
switching scheme either takes the up or down transitions depending on whether
the bit is 0 or 1, respectively. The procedure is repeated until the LSB is
decided.
43
44

Calibration
Figure 5-4: Conventional SAR switching algorithm, showing energy

consumption related to capacitor switching transitions [3]
Figure 5-5: The top-plate waveform when using the conventional switching
algorithm [3]
Observing the first two transitions, it can be seen that energy efficiency can
be improved. In the above example, the sign bit of the input signal is generated by
comparing the magnitude of
and
in the first transition. As shown in

44
45

Calibration
Figure 5-4, depending on the values of the input signal, there are a total of four
potential transition paths that the SAR algorithm can take. Assume that the upper
most path is taken, the first step makes up more than 75% of the total energy
consumption to just generate the sign bit. Intuitively, without consuming any
energy, the sign bit can be generated by directly comparing
and
after
sampling. It implies that simpler algorithm can be developed to avoid this energy
loss.
The average switching energy of an n-bit conventional switching algorithm
can be derived as follows:
(5.1)
Monotonic Switching Algorithm

Liu et al. in [33] proposed a monotonic switching algorithm. The ADC
samples the input signal on the top plates while the bottom plates of the capacitors
are reset to
. At the end of sapling phase, the input is disconnected from the
DAC. Without switching any capacitor, the comparator directly compares
and
. Depending on the comparator output, the MSB capacitor on the higher voltage
potential side is charged to ground while the other one (on the lower side) remains
connected to
. The procedure is repeated until the LSB is decided. For each bit
generation cycle, only one capacitor is switched, which reduces both charge transfer
in the capacitive DAC network and the transitions of the control circuit, resulting in
smaller power dissipation.
Figure 5-6 shows the top-plate waveform for a 6-bit ADC using the
monotonic switching algorithm. The major differences between this algorithm and
the conventional one is that the common-mode voltage of the reference DAC
gradually decreases from half to ground but never increases. For an n-bit ADC, the
sum of all capacitors in a DAC is
, only half that of the conventional one.
Figure 5-7 shows 3-bit examples of the monotonic switching algorithm. This
switching algorithm consumes no energy before the first comparison since the
comparator directly performs the first comparison without switching any capacitor.
In contrast, the conventional one consumes
45
before the first comparison. The
46

Calibration
subsequent switching transition of the monotonic switching procedure is also more

efficient than that of the conventional one.
The average switching energy of an n-bit monotonic switching algorithm can
be derived as follows:
(5.2)
Figure 5-6: The top-plate waveform when using the monotonic switching
algorithm [3]
Summary and Comparison of the Monotonic Switching Algorithm with
conventional and other algorithms
The average energy consumption of the five switching schemes versus
different number of bits is shown in Figure 5-8 [3]. The common figures of merit
that are used to evaluate switching algorithms are shown in Table 5-1 [3]. From this
table, in terms of some figures of merit such as the total number of switches,
whether the switching scheme allowing rail-to-rail input swing, total capacitance,
common mode remaining fixed during the conversion process, and energy
consumption, the IMCS and MCS algorithm are the best. However, they require
additional voltage source to provide common mode voltage, which results in the
necessary of another circuit (which will consume quite a lot power) to generate this
voltage. Therefore, in this work, the monotonic switching algorithm will be chosen
because of its efficient and non-requirement of additional voltage source.
46
47

Calibration
Figure 5-7: Monotonic switching algorithm [3]

5.2.1.2.
Main DAC design
To achieve 12-bit accuracy, a fully differential architecture is used to

suppress the substrate and supply noise and has good common-mode noise
rejection. To implement redundancy in SAR ADC, 2 approaches have been
proposed. The first approach utilizing unit-element DACs implements the subbinary redundancy in digital control logic [34], [35]. The advantage of the technique
is digital programmability/flexibility. However, a unit-element DAC increases the
logic complexity of the ADC, i.e., it requires a binary-to-thermometer decoder,
which will increase the power of the circuit. In a more simple way, redundancy can
be built directly into the DAC, by using sub-radix-2 approach [29], [36] and [37]. In
a sub-radix-2 SAR ADC, due to the weighting of the DAC capacitors, successive
47
48

Calibration
search ranges are sub-binary, eliminating the extra decoding effort and circuit
complexity.
Figure 5-8: Comparing energy consumption of different switching algorithms

[3]
Table 5-1: Comparison of different switching schemes in terms of various

figures of merit [3]
In this work a sub-radix-2 architecture is utilized. As described in chapter 4,
to achieve an effective number of bit (ENOB) greater than 12 bits, a radix of 1.86
with 14 conversion steps was chosen. By utilizing digital background calibration, it
enables an aggressive downsizing of the sampling capacitors in the 12-bit prototype
to minimizing the power consumption and area. The value of capacitors is shown in
table 5-2.
48
49

Calibration
Capacitor
Value (fF)
1715
922
496
266
143
77
41
22
12
6
3
2
1
Table 5-2: DAC capacitors value
5.2.2. Sampling Network Design

Figure 5-9 shows the bootstrap switch [38] implemented in this work. It is a
simple solution to eliminate the signal-dependency of the channel charge injection
problem. When sampling clock (clks) is low the gate of
discharged to ground through
B) boosting capacitor (
through
When clks turns high, input signal (
turns on and charges node A to
is higher than
and
) is sampled by
which boots node C to
during sampling. Because the gate of
, and top plate
. The charge boosting path node C to node A
which is turned on and off by
, node B is charged to
(node A) are
. At the same time, the bottom plate (node
) are discharged to ground through
(node C) is charged to
is cut off by
, and
and
and
. Through
. Meanwhile,
is here to help
to keep
is
on
is also boosted, it can handle voltage that
. The gate-to-source voltage (

49
) of
is now a constant

Calibration
50
which is (
(
.). Thus, the channel charge (
) of the bootstrap switch are isolated from
) and on-resistance
. In addition, with the boosted
the sampling switch can also handle rail to rail input.

(
(5.3)
)
(
(5.4)
VDD
Clk_d+
M7
M3
C
M 10
M4
M6
Clk_d+
M9
A
M1
M5
CS
MS
V+ ( V-)
Clk_d+
V i+ ( V i-)
M8
C DAC
Figure 5-9: Bootstrap switch in [38]
5.2.3. Dynamic comparator design

As shown in Figure 5-10, a p-type dynamic latched comparator is
implemented in this work. During the conversion phase, the input voltages of the
comparator approach ground, for proper function within the input common-mode
voltage range from half
to ground, the comparator uses a p-type input pair.
Because a dynamic comparator does not consume static current, it is suitable for
energy efficient design, and is less sensitive to substrate noise. The operation of the
comparator can be described as follow. At the rising edge of the control signal sent
by SAR control (Clkc), both comparator outputs are reset to high. As Clkc goes to
low (assume that
and the current in
),
is turn on. There are current that go through

will increase more rapidly than the current in
50
and
.
51

Calibration
Therefore the current in

drives
will cause the gate-source voltage of
low and ultimately
increase. This
up. Once the comparison is done, the
differential outputs are then gated to trigger internal control signal which is
feedback to turn off the comparator for additional power saving.
VDD
VBIAS
Mb
M7
M14
M8
Vp
M1
M2
Vn
M10
M12
Out_p
Out_n
M15
M9
M5 M3
M4 M6
M11
M13
gnd
on
Figure 5-10: Dynamic comparator with a current source.
5.2.4. Preamplifier design

Figure 5-11 shows the preamplifier schematic of the prototype ADC. The
preamplifier provides around 30-dB gain to relax the noise, offset, and sensitivity
requirement of the dynamic latch. It consists of 2 stages: The first stage is a Songs
preamplifier and the second stage is a resistively loaded pseudo-differential
amplifier. The total preamplifier DC gain is given by
(5.5)
The active-load NMOS transistors M3 and M4 in the first stage also act as
the current mirror for the second stage to define its bias current. In order to
minimize the flicker noise, the input pair of the first stage is PMOS. As the
comparator is idle in the sampling phase, the signal on (Figure 5-12) is pulled
high to shut off the bias current to save power.
51
52

Calibration
VBIAS
M11
on
M7
M10
M9
V+
M8
M1
V-
M2
R1
R2
R2
Vp
Out_p
Vn
Out_n
R1
M3
M4
M5
on
M6
Figure 5-11: The schematic of the preamplifier
5.2.5. Control logic design

5.2.5.1.
Flip flop design
In this design, split-output True single Phase Clock (TSPC) flip flop as in
Figure 5-12 is used because of its low power consumption compare to other types of
flip flop. This flip flop uses only single clock and 2 clock transistors, which will
result in small dynamic power consumption. The operation of split-output TSPC
flip flop can be described as follow. When rst signal becomes high, the flip flop is
reset by pulling the gate of
and
ground. At this time
up to
and
become 0. The role of
and the gate of
and
down to
act as 2 inverters to make the output Q
is stop the current go from
through
and
to the ground (in case D=1, rst=1 and clk=0) to save power. When rst signal is low,
the flip flop operates as normal. When the clk is low,
off. The parasitic capacitor at gate of
and
is turn on while
will be charged to
is turn
or
discharged to ground depend on value of D. When clk changes from low to high,
is off and
is on. Voltage value of parasitic capacitor at gate
decide voltage at gate of

capacitor at gate of
and
and
and
and
will
. The value of input D will be stored in parasitic

and can be taken out through 2 inverters made by
.
52
53

Calibration
rst
M r1
M4
M1
Clk
M2
M7
rst
M5
M9
M r3
D
rst
rst
M r5
M r2
M6
M3
rst
M r4
M8
M10
Figure 5-12: Split-output True Single Phase Clock (TSPC) Flip Flop
5.2.5.2.
Clock generator
The role of clock generator block shown in Figure 5-13 is generating the signals
that allow the switches in the DAC work. Its operation can be described as follow.
When the comparator finishes the comparison, both output signals Out_p and Out_n
are not low anymore, but 1 output is high and the other is low. This makes the
signal Ready becomes low to indicate that comparator finish its work. The aclk
signal is pulled low also and then the series of negative edge flip flop will generate
the desire clock signal
These clock signals will be used to control the
switches of capacitor array.

5.2.5.3.
Comparator control logic
The schematic of comparator control circuit is shown in Figure 5.14 a). The
main function of this circuit is to turn off the comparator and preamplifier whenever
the comparison is completed to save power. When the comparator finishes
comparing
and
, signal ready change from low to high. This makes the on
signal become high and both comparator and preamplifier are turn off.
53
54

Calibration
Rst_local
aclk
DFF
VDD
DFF
D
clk 1
DFF
D
clk 2
DFF
D
clk 3
DFF
D
clk 4
DFF
D
clk 5
DFF
D
clk 6
DFF
D
clk 7
DFF
clk 8
DFF
D
clk 9
DFF
D
clk 10
DFF
D
clk 11
DFF
clk 12
comparator
Out_p
ready
Out_n
clk
aclk
a)
Clk_d+
Clk_main
clk
ready
aclk
Rst_local
clk 1
clk 2
clk 3
clk 4
clk11
clk 12
clk13
clk14
b)
Figure 5-13: Clock generator a) Schematic. b) Timing diagram
54
DFF
D
clk 13
clk 14
55

Calibration
preamplifier
comparator
Vcm+
Out_p
Vcm-
Out_n
ready
on
Clk_main
clks
a)
Clk_main
clk
ready
on
b)
Figure 5-14: Comparator control circuit a) Schematic. b) Timing diagram
5.2.5.4.
Switch control logic
The schematic of switch control logic is shown in Figure 5.15 At the rising
edge of
, a static flip-flop samples the comparator output. If the output is high,
the relevant capacitor is switched from
to ground. If the output is low, the
relevant capacitor is kept connected to
. At the falling edge of
capacitors are reconnected to
, all
. This work uses an inverter as a switch buffer.
To prevent unnecessary energy consumption and to keep the RC value the same, the
sizes of the first six switch buffers are scaled down according to the driven
capacitances and the buffers of the last three capacitors are unit size ones.
55
56

Calibration
Vref
Clki
Vpi
Q
buffer
Out_p
(Out_n)
D
Vcm+
(Vcm-)
Case 1
Case 2
Clki
Clki
Out_p
Out_p
Vpi
Vpi
Figure 5-15: DAC Control Logic
5.2.5.5.
Dynamic threshold comparison
As mentioned in chapter 3, to exploit the error tolerance of the sub-radix-2

architecture, the comparison threshold is pulled close to the midpoint of the
redundancy range. An additional capacitor is needed to temporarily shift the
threshold as in [4]. However, this will require additional capacitor and the area will
increase as a result. In this work, the reuse of capacitor in DAC to implement DTC
is proposed. Figure 5-16 shows the implementation of DTC. To temporary shift the
threshold, the bottom plate of an capacitor in
when the decision is in progress and is switched to
branch will be tied to ground

after the bit is resolved.
Therefore, the DTC effect is transient and (1) remains valid. The technique is only
applied to the first seven bits in this design. This ideally results in dynamic error
tolerances of 82, 44, , 2 LSBs for the first seven conversion steps.
56
57

Calibration
Vref
Clk i
Out_p
(Out_n)
Vcm+
(Vcm-)
Clk i-6
Clk i-7
Figure 5-16: Dynamic threshold comparison circuit
5.2.5.6.
Digital calibration circuits
In the block diagram of the calibration engine shown in Figure 5-3, the inner
product blocks operate at the rate of the conversion steps, which is much higher
than operation rate of the two adders and the LMS block. Therefore, the power
consumption of the inner product blocks dominates the power of the calibration
circuits. A folding structure is utilized to exploit natural serial output to implement
the inner product block in digital calibration logic, shown in Figure 5-17. The adder
and the register accumulate either
(
) and this is
or
or
depending on the polarity of
The block diagram of LMS block is shown in Figure 5-18. These block
diagram is used to implement the Equation (4.8) and (4.9). It can be seen that the
value of
and
will be update simultaneously at the rising edge of signal
Update_w.
57
58

Calibration
D
D
d+
Q
Clk_d +
w13
ready
w12
w11
d+ - d -
MUX
w2
w1
w0
bi
Figure 5-17: Block diagram of the inner product block
b i+
b iw.error
.error
b i+
b i-
Q
Wi
D Q
2 d
Wi
Update_w
Update_w
Figure 5-18: Block diagram of LMS block
58
2 d
59
60
Simulation Results
Chapter 6
Simulation Results
In Chapter 4, the implementation of SAR ADC is introduced. The circuit is present
from architecture level to circuit block level. All the improvements such as the
novel method to implement dynamic threshold comparison and calibration engine
are discussed.
In this chapter, the simulated results of prototype chip will be presented.
Since the nature of least mean square algorithm in calibration engine require a lot of
samples to obtain the optimal bit weights (about 22000 samples in [4]), the
simulation time need to obtain this amount of samples is too large. Normally, other
works fabricate the ADC first and then the calibration engine is implemented in
software or FPGA. By using hardware simulation, large amount of samples are
obtained at only about millisecond. Thus, in this chapter, only simulation results of
SAR ADC without calibration and capacitors mismatches are described. The full
results of SAR ADC with capacitor mismatches will be added later on. The
prototype 12-bit SAR ADC was implemented in a 1.8V, TSMC 0.18m Mixedsignal CMOS technology.
6.1. Prototype Performance

6.1.1. Dynamic performance
Analog to Digital Converter dynamic performance requires FFT (Fast
Fourier Transform) test method to measure ENOB (effective number of bit) and
SNDR (signal-to-noise plus distortion ratio). With the sine wave input signal, the
output digital code will be transfer to spectrum through FFT transformation method.
In this design, Matlab computing is used to simulate spectrum of output code with
FFT transformation 4096 points.
60
61
Simulation Results
With the sampling rate of 100ksps, the measured output power spectral
densities (PSDs) of the SAR ADC at Nyquist frequency input is shown in Figure 61. The dynamic performance of this ADC is quite good even at Nyquist frequency
input, results in a SNDR and ENOB of 75.8 dB and 12.3 bit, respectively.
Figure 6-1: The measured output spectra of the SAR ADC
6.1.2. Static performance

To simulate the static performance of ADC, the ramp input signal from 1.78V to 1.78V is driven at the input while the sampling rate is still 100ksps. From
Figure 6-2, the maximum DNL and INL errors are +0.8/1LSB and +2.49/
2.72LSB, respectively. This result is not so good but acceptable for the target SAR
ADC.
6.1.3. Performance summary and comparison

The overall performance of the prototype from simulation is summary and
compare with others work in Table 6-1.
61
62
Simulation Results
Figure 6-2: The measured DNL and INL of the SAR ADC
Ref
[4]
[5]
[6]
[7]
This work
Year
2011
2013
2007
2013
--
Source
JSSC
TCAS2
JSSC
JSSC
--
Technology
0.13m
0.35m
0.18m
65nm
0.18m
Supply (V)
1.2V
2.3V
1V
1.2V
1.8V
Resolution (bit)
12
12
12
14
12
Fs (MS/s)
22.5
0.25
0.1
80
0.1
ENOB (bit)
11.3
11
10.5
11.9
12.3
DNL (LSB)
N/A
0.14
0.66
N/A
0.8/-1
INL (LSB)
N/A
0.38
0.68
N/A
2.49/-2.72
Total Power (mW)
0.107
0.025
31.1
0.016
FOM (fJ/C-S)
51.3
209
165
164.7
30.9
Table 6-1: Comparison of the state-of-the-art works

.
62
63
64
Conclusion and Future Works
Chapter 7
Conclusion and Future Work
7.1. Conclusion
Touch panel for handheld device requires low-speed, high-resolution ADCs
with low-power operation. Among prevalent ADC architectures, SAR ADCs are
favored due to their high energy efficiency. However, the resolution of SAR ADC is
only medium compare to others. With low sampling speed, the nonlinearity of the
SAR ADC is static nonlinearity, which is dominant by the capacitors mismatch. To
deal with this problem, sub-radix 2 SAR ADC architecture combined with
calibration engine is utilized. This combination provides a lot of advantages such as
aggressive unit capacitor downsizing, error tolerant capability and all the
capacitors mismatch coefficients are identified with negligible hardware overhead
and minimal modification of the original ADC circuits to calculate correctly the
output code. Improvements to the calibration engine and dynamic threshold
comparison implementation have been proposed to further improve the linearity as
well as power consumption.
Since the require time for the hold ADC simulation is quite large, only the
prototype 12 bit redundant SAR ADC without capacitor mismatches and calibration
engine has been simulated. The ADC has been implemented in TSMC 0.18m
Mixed-Signal CMOS technology, archives 75.8-dB signal-to-noise-plus-distortion
ratio (SNDR) and maximum DNL and INL errors are +0.8/1LSB and +2.49/
2.72LSB, respectively, at 100ks/s, while dissipating only 15.7-W power from a
1.8-V supply.
64
65
Conclusion and Future Works
7.2. Future work

The overall performance of ADC has not been finished yet. Therefore, it
should be completed as soon as possible to evaluate the effect of digital background
calibration and redundancy on linearity of SAR ADC.
Although this SAR ADC is able to archive better linearity compare to other
works, there are still many opportunities for improvement. The main goal is to push
the SAR architecture to achieve higher resolution while still being able to achieve
lower power consumption.
Though the monotonic switching algorithm has some advantages such as
high power efficiency and non-requirement of addition power source, it is still not
the most energy efficiency algorithm. Moreover, this algorithm is sensitive to
parasitic capacitances. To solve these problems, the Inverted Merged Capacitor
Switching Algorithm [3] can be utilized.
Although the deterministic and zero-forcing nature of perturbation based
calibration algorithm results in a much shorter convergence time compared to the
correlation-based background calibration techniques [22],[32], the analog offset
injection will reduce the dynamic range of SAR ADC, and the signal to noise ratio
cannot be maximized. To deal with this problem, another way to add injection
signal will be researched.
65
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69

Final Thesis - ADC

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Final Thesis - ADC

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HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

SCHOOL OF ELECTRONICS AND TELECOMMUNICATIONS

A GRADUATION THESIS FOR

DESIGN OF LOW POWER HIGH LINEARITY SAR

NGUYEN VIET TAN 20092354

Microelectronics Advance Program K54

Dr. NGUYEN VU THANG

MINISTRY OF EDUCATION AND TRAINING

SOCIALIST REPUBLIC OF VIETNAM

HANOI UNIVERSITY OF SCIENCE AND TECHNOLOGY

GRADUATION THESIS MISSION

.................. School: ........................................................................... Subject: ...........................................

3. Content of theory and equation:

4. Graphs and drawings:

5. Supervisors full name: ........................................................................................................................................

7. Finishing date: ..........................................................................................................................................................

(signature and full name)

(signature and full name)

Student has completed and submitted this thesis in (date): .......................................................................

MINISTER OF EDUCATION AND TRAINING

GRADUATION THESIS COMMENT

Subject: ........................................................................................ Course: ......................................................................

2. Comment of committee member:

This page is intentionally left blank

1.1. Structure of Projected Capacitive Touch technology with mutual capacitive

Quantization Noise ................................................................................... 4

Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) .......... 4

Signal-to-Noise Ratio (SNR).................................................................... 4

Effective Resolution ................................................................................. 5

Figure of Merit (FoM) .............................................................................. 5

1.4. Motivation .......................................................................................................... 5

Overview of Traditional SAR ADCs ...................................................... 9

2.1. Binary Successive Approximation Algorithm.................................................... 9

Capacitor Mismatches ............................................................................ 15

Offset Errors ........................................................................................... 17

2.4. Dynamic Error Sources in SAR ADCs ............................................................ 18

Redundancy SAR ADCs ......................................................................... 21

3.1. Redundancy Overview ..................................................................................... 21

Error tolerance windows for redundancy ............................................... 25

Dynamic Threshold Comparison............................................................ 26

3.2. Digital calibratability ........................................................................................ 27

Condition of digital calibratability ......................................................... 27

Radix and number of steps .................................................................. 29

Digital Background Calibration of SAR ADCs ................................... 32

4.2. Overview of digital calibration in SAR ADC .................................................. 32

4.2. Perturbation-Based Calibration Algorithm....................................................... 35

SAR ADC architecture ........................................................................... 41

Calibration architecture .......................................................................... 42

5.2. Key circuit building block ................................................................................ 43

Capacitive DAC Design ......................................................................... 43

Monotonic Capacitor DAC Switching Operation ............................... 43

Main DAC design ............................................................................... 47

Sampling Network Design ..................................................................... 49

Dynamic comparator design ................................................................... 50

Preamplifier design ................................................................................. 51

Control logic design ............................................................................... 52

Flip flop design ................................................................................... 52

Clock generator ................................................................................... 53

Comparator control logic .................................................................... 53

Switch control logic ............................................................................ 55

Dynamic threshold comparison .......................................................... 56

Digital calibration circuits ................................................................... 57

Simulation results ................................................................................... 60

6.1. Prototype Performance ..................................................................................... 60