Sumit K Chattopadhyay and Chandan Chakraborty

Indian Institute of Technology Kharagpur

IE Tech News June 2014

 Features of level doubling network

The basic assumptions
LDN with a Generalized MLI
An example: LDN circuit with cascaded H-bridge
Analysis at steady state and transient
Simulation Results
Experimental Results
Conclusions

Almost double the number of levels of any

multilevel inverter topology.
The LDN is basically a capacitor fed half
bridge.

The proposal of the LDN opens up a new

topological variation for the existing
configurations.

 Output voltage and current waveforms will

have half wave symmetry.
There will be negligible dc component in
output current waveform under steady state
A load with back emf will also have half wave
symmetry in back emf.

LDN with a symmetric CHB MLI

ic

During negative half cycle

ic

During positive half cycle

LDN capacitor Current during negative half cycle

(8)
LDN capacitor Current during negative half cycle

(9)
Net charge exchange during two complementary
period of T

(10)

Line Voltage
Line Voltage

Phase Voltages

Phase Voltages

Line and phase voltage waveforms

for an MLI without LDN

Line and phase voltage waveforms for

same MLI with LDN

Number of levels are almost doubled

Time in seconds

(b)

Time in seconds

Energy-time waveform comparison

Red: one of the H bridges
Blue: LDN

Energy in Joule

Energy in Joule

Energy in Joule

(a)

Time in seconds
(a): Energy-time waveform of LDN dc bus with
single phase (any topology)
(b): Energy-time waveform of LDN dc bus with
three phase CHB only

Current in Ampere

Current in Ampere

Time in seconds

Current waveform at zero power factor lagging

Energy in Joule

Energy in Joule

Current waveform at unity power factor

Time in seconds

Time in seconds

Energy waveform at unity power factor

Time in seconds

Energy waveform at zero power factor lagging

Time in seconds

Initial voltage is 200% of desired voltage

Time in seconds

Initial voltage is zero

Close-up view of one phase

Output line to line voltage of all

the phases of the inverter

Close-up view of one stack

Experimental Parameters
Number of H-Bridge Per Phase 3

Number of Phases at Output

Load Connection
H-Bridge DC-Bus Capacitances
Level Doubling Circuit DC Bus
Capacitance

Details

11,000 F
33,000 F

Load time constant

500 Sec
IGBT
Modules
(Semikron SKM75GB12T4
Make)
IGBT Gate Drivers (Semikron SKHI 22AR
Make)
Cooling
Forced Air
Heat Sink (P3 type Semikron 0.14Kelvin/W
Make)

Channel 1 (Yellow): LDN voltage Channel 2,Channel 3, and Channel 4 : line-to-line voltages

Channel 1: 25 level Line-to-line voltage

Channel 2 : Line current with RL load

Channel 1 (Yellow): LDN voltage

Channel 2 (Blue): Load current with harmonic

Sudden rise of frequency

Rapid drop of frequency and
modulation index
Channel 1: LDN voltage
Channel 2,Channel 3, and Channel 4: Resultant line voltage

Load is connected here

External disturbance
is removed here

(a)
(b)
Channel 1 (Yellow): LDN voltage under disturbance

 This paper has presented a new concept to

increase the number of levels in MLI.
The proposed concept can be applied to all
form of existing MLIs to almost double the
number of levels.
The dc bus of the LDN remains in self
balancing condition in open loop.

H. Abu-Rub, J. Holtz, J. Rodriguez, and B. Ge, "Medium-voltage multilevel

convertersstate of the art, challenges, and requirements in industrial
applications," IEEE Trans. Ind. Electron., vol.57, no.8, pp.2581-2596, Aug.
2010.
M. Malinowski, K. Gopakumar, J. Rodriguez, and M.A. Perez, "A survey on
cascaded multilevel inverters," IEEE Trans. Ind. Electron. , vol.57, no.7,
pp.2197-2206, July 2010.
S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L.G. Franquelo, Bin Wu; J.
Rodriguez, M.A. Perez, and J.I. Leon, , "Recent advances and industrial
applications of multilevel converters," IEEE Trans. Ind. Electron., vol.57, no.8,
pp.2553-2580, Aug. 2010.
M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, "Hybrid multilevel power
conversion system: a competitive solution for high-power applications," IEEE
Trans. Ind. Applications., vol.36, no.3, pp.834-841, May/Jun 2000.
Y.-S.Lai and F.-S. Shyu, "Topology for hybrid multilevel inverter," Proc.
IEE Electric Power Applications, vol.149, no.6, pp. 449- 458, Nov 2002.
J. Dixon, J. Pereda, C. Castillo, and S. Bosch, "Asymmetrical multilevel inverter
for traction drives using only one DC supply," IEEE Trans. Vehicular Technology,
vol.59, no.8, pp.3736-3743, Oct. 2010.

X. Kou, K. A. Corzine, and Y. L. Familiant, "Full binary combination schema for

floating voltage source multilevel inverters," IEEE Trans. Power Electron., vol.17,
no.6, pp. 891- 897, Nov 2002.
C. N. Ng, P. J. Dhyanchand, and V. M. Nguyen, "High voltage inverter utilizing low
voltage power switches," United States Patent Application 5666278, September 9,
1997.
H. Gruning "Power electronic circuit arrangement having plural power converters,"
United States Patent Application 5805437, September 8, 1998.
A. L. Batschauer, S. A. Mussa, and M. L. Heldwein, "Three-phase hybrid multilevel
inverter based on half-bridge modules," IEEE Trans. Ind. Electron., vol.59, no.2,
pp.668-678, Feb. 2012.
M. Saeedifard, P. M. Barbosa, and P. K. Steimer, "Operation and control of a hybrid
seven-level converter," IEEE Trans. Power Electron., vol.27, no.2, pp.652-660, Feb.
2012.
P. Lezana and R. Aceiton, "Hybrid multicell converter: topology and
modulation," IEEE Trans. Ind. Electron., vol.58, no.9, pp.3938-3945, Sept. 2011.

Disclaimer

These slides are made by authors to help readers quick and

better understanding of the subject. The opinions made or
information presented here belong to the sole responsibility of
the authors.
IE Tech News (ITeN) neither endorses nor denounces any
opinions made or information presented. Part or full of these
material may be used only with written permission from the
authors.