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Culture Documents
ideas
C1 R 6 VH
,
VCC (11K1 ) + VI (K111)1VBE
and
IC1A
74HC14
R6
5.6k
OUTPUT
INPUT
VOLTAGE
VI
R3
33k
Q2
BC847C
R5
10M
C1
100 pF
+
2
R4
22k
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In this PWM circuit, adjusting the input voltage, VI, changes the emitter potentials of Q1 and Q2 and
thus varies the charge and discharge currents of C1 so that the duty cycle of the output varies in
direct linear proportion to VI.
January 6, 2000 | edn 119
design
ideas
C R V
T2 = 1 6 H .
K 2 VI1V BE
If the R1-to-R4 divider network is symmetrical, or R15R4 and R25R3, this expression simplifies to
DUTYCYCLE =
K 2 VI1VBE
100%.
VCC (11K1 )12 VBE
0.4 VI1VBE
100%.
0.4 VCC12 VBE
Figure 3
Although the frequency of the output waveform varies with the input voltage, the PWM circuit
exhibits a linear relationship between input voltage and output duty cycle.
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ideas
Figure 2
A behavioral simulation of the decoders operation shows the internal signals involved in decoding.
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ideas
R1
5V
Figure 1
0.1 mF
470
D1
D2
D3
RS
IN
2.2k
10 mF/
NONPOLAR
4.7k
TO CIRCUIT
DSO
D4
R2
15V
D5 470
D6
(c)
NOTES: ALL DIODES=1N4935 FAST-RECOVERY TYPE.
Two surge shunt paths, consisting of D1, D2, and D3 to ground or D4, D5, and
D6 to ground, provide overvoltage protection.
Tests with a 30V charged capacitor at the input show the circuits
response with a horizontal scale of 25 nsec/div (a) and 1 msec/div
(b). The long-term response shows the recovery of the coupling
capacitor (c).
design
ideas
LIN
Figure 1
LOAD
COUT
RSENSE
330 pF
0.005
5W
1%
10k
15V
15V
1k
CURRENT SENSE (+)
0.1 mF
0.1 mF
7
3
2
+
2
1
MC34072
1k
CURRENT SENSE (2)
5V
REF
4.87k 294k
VIN
33.2k
1
10k
CF
AD736
6
OUT
CC
CAV 5
COM 2VS
8
330 pF
+VS
10 mF
1.02k
MC34072
5
6 2
VRMS
47.5k
+
10 mF
5V REF
5V REF
5V REF
1.02k
47.5k
Level-shifting the input to an rms-to-dc converter allows you to use the converter with only positive supply voltages.
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ORST_N
The simulation waveform shows that the circuit asserts the output reset signal, orst_n, immediately
after the system asserts the asynchronous input signal, irst_n, and shows that the reset release is
synchronous with the clock signal within two cycles.
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ideas
Figure 1
IC3
LT1460-5
+
8V
+
100 mF
10 mF
5V
5k
IC1B
LTC1043
IC1A
1k
6
8
5V
100 pF
K
100 pF
100 pF
11
5k
1 mF
12
3
5k
100 pF
100 pF
15
18
10 TO
10O pF
13
LTC1250
+
2
14
IC2
25V
5k
10k
10k
25V
150 pF
1k
IC5
LTC2400
5V
1
10k
10k
3
2
5k
2
+
2
+
IC4
1
2 LT1112
3
10 mF
VCC
OSE
VREF
SCK
VIN
EDO
GND
CS
0.1 mF
Using an analog switch, IC1; a chopper-stabilized amplifier, IC2; a reference, IC3; a buffer, IC4; and a delta-sigma ADC, IC5, this circuit can resolve 0.1-fF
changes in a 100-pF bridge element.
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those that may occur in oil due to contamination. For example, if you create a
capacitor using 535-in. plates that are 1/4
in. apart, the dielectric constant, K, of the
media between the plates could be resolvable over the range of 1 to 4.5 (22.48
to 101.2 pF). A change in K of as little as
0.000004 would be measurable. The
rigidity and separation between these
plates would have to be constant and stable because movement of as little as 0.3
mm would produce the same 0.1-fF
change. The use of low-thermal-coefficient materials would be necessary to
maintain this separation, but this measurement is practical with good mechanical design.
Other capacitor geometries are possible, of course. For example, the plates of
the capacitor could be coplanar interleaved fingers etched onto an insulator,
and the unknown dielectric could either
touch the surface or be distanced with an
insulator. Also, many configurations of
bridges are possible. For example, you
could devise bridges to compare two sub-
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ideas
100 mF
ON
PGI
PS
R4
+ C2
100 mF
ONA
OFF
OFF
ON
ONB
5
3V
IC1
MAXIM
MAX1672
OUT
PG0
ILIM
FB
REF
C3
0.1 mF
PGND
GND
3 OR
R1
300k
3/5
5V
OUTPUT LEVELS;
NOT LOGIC LEVELS
3 OR
5V
10
R2
100k
R2
100k
R5
1M
+ C4 5V
4.7 mF
LOW-BATTERYDETECTOR
OUTPUT
Q1
2N7002
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This circuit provides the same outputs as the circuit in Figure 1 without tying up the internal
power-good comparator.
January 20, 2000 | edn 113
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ideas
IL = IN 2 + 1 .
(1)
R1 R X
R
R 3 = (R 2 + R X ) 4 .
R1
(2)
In Equation 1, you can arbitrarily select any four of the terms and then determine the fifth term by solving the resulting equation. In Equation 2, you can
arbitrarily select either R3 or R4 and then
R2
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ideas
5V
5V
5.1
5.1
2N3906
2
0.1 mF
5V
226
IC3B
0.1 mF
1
4 LT1633
2N3906
IC3C
1
4 LT1633
+
10k
10 nF
220 mH
1.5 nF
220 mH
10 nF
IC1
HP MSA0785
1.5 nF
1.5 nF
IC2
HP MSA0785
VOUT
3.9 mH
+
IC3A
1
4 LT1633
1k
A simple op-amp-follower circuit with the aid of inductive blocking restores the dc level of an RF
signal.
hicle- and engine-speed sensors. The circuit in Figure 1 uses discrete components
to multiplex two sensors with open-collector outputs into a single output, there-
12V
Figure 1
R1
1k
C1
0.1 mF
R4
1k
R3
1k
R2
1k
MUXED_OUT
SENSOR 1
1
D1
1N4148
2
R5
1k
12V
1
R8
1k
8
Q1C
MPQ3906
9
Q2
BS170
R10
1k
Q1B
MPQ3906
6
R6
1k
SENSOR 2
2
Q1A
MPQ3906
12V
7
R7
1k
1
D3
5.1V
2
10
Q1D
14 MPQ3906
13
12
R11
1k
D2
1N4148
R9
1k
Q3
BS170
SELECT
12V
FROM
mC
12V
R12
10k
You can multiplex the output signals from two sensors into one input-capture line in a mC.
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ideas
MUXED_OUT. Therefore, when the Select input is low, MUXED_OUT produces pulses that are inverted but synchronized with the Sensor 1 pulses. At the
same time, Q3 and Q1D are on, turning off
Q1B and disabling the Sensor 2 input.
Similarly, when Select goes high, Q2
and Q1C turn on, turning off Q1A and disabling the Sensor 1 input. At the same
time, Q3 and Q1D turn off, allowing the
Sensor 2 signal to turn Q1B on and off
when Sensor 2 switches on (low) and off
(high-impedance state), respectively.
Therefore, MUXED_OUT produce puls-
ALD4213
1
Figure 1
V+
2 D1
3
4
C1 +
10 mF
IN1
S1
V2
GND
S4
74HC4316
IN2 16
16
D2 15
15
V+
S2
V+
13
V+
D4
IN4
CLK
14
13
S3
CLK
12
11
6
7
V+
10 mF
2VOUT
D3 10
2VOUT
10
IN3 9
9
C2
10 mF
(b)
(a)
+
10 mF
NOTES:
< <
2V_V+_5V.
CLK IS CMOS LOGIC LEVEL WITH FREQUENCY OF 5 TO 500 kHz.
V+ IS THE DC-TO-DC INPUT.
2VOUT IS THE DC-TO-DC OUTPUT.
Using an analog switch with two external capacitors and an external clock is a viable way to produce 25V from a 5V input for low-power, 25V needs.
One approach uses only one phase of the clock (a); a second approach requires both phases (b).
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ideas
tive supply uses a low-cost quad- semiconductor analog switch and an onboard
system clock (Figure 1a). This type of
voltage converter generates a low-power, negative bias voltage from a 5V input.
This circuit emulates charge-pump dc/dc
converters, which are suitable for generating an output voltage whose polarity is
opposite that of the input voltage. Two
charge-storage capacitors are also necessary, as with conventional converters.
Unlike the conventional self-contained
dc/dc converter approach, this circuit requires a single external clock input to sequence the switches on and off and approximately the same amount of pcboard space. You can tap this clock from
any 5V logic-gate output with continuous, regular periods of 5- to 500-kHz signals.
Charge-pump converters operate by
first charging up one capacitor and alternately transferring that charge to another capacitor using a switching circuit.
The switching circuit in Figure 1a alternately charges and discharges C1 and C2
to generate a 25V output from a 5V input. Integrated level translators and log-
74HC4316 quad analog switch with level translator (Figure 1b). The circuit is
similar to the circuit in Figure 1a but has
different pin connections. This circuit
also requires both phases of the clock.
You can use an additional inverting logic gate to generate both clock phases if
necessary. The recommended input is a
logic clock that has a useful frequency
range of 5 to 500 kHz.
Figure 1as single-phase design costs
less than $1 in large quantities. The cost
of the circuit in Figure 1b can be less than
half the cost of the circuit in Figure 1a
provided that both clock phases exist and
that you dont have to add an external
logic-gate inverter. You can also integrate
analog-switching inverters with other
analog functions in a custom ASIC; the
ALD4213 and ALD500A are compatible
with the companys library of standard
cells. (DI #2476)
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ideas
current is near zero, keeping the optocoupler off and its transistor open with
the voltage at Pin 5 at the battery voltage.
The Tip and Ring lines are at 6 and 0V,
respectively, to power the phones on the
line (Most phones operate on as little as
3V.) Battery drain in this condition is
minimal. When a receiver goes off-hook,
the line impedance drops, and several
milliamps flow through the saturated
ton. The message plays once in its entirety every time a receiver goes off-hook.
C2 prevents any clicks at the end of the
message from restarting the sequence if
the receiver goes on-hook before the
message ends. (DI #2472)
B1
5V
B0
IC1A
3
2
74HC00
Figure 1
IC3
A4N28
R7
10k
PULSE FOR
"1" BITS
IC1B
4
5
SRCK
74HC00
13
IC1C
12
8
10
SERIN
5V
74HC00
PULSE BOTH
TO UPDATE
LATCHES.
PULSE FOR
"0"' BITS
5V
IC4
A4N28
R8
10k
12
IC5
G
RCK
IC1D
10
11
SRCLR
SRCK
14
SER
11
13
74HC00
2
15
1
2
3
4
5
6
7
9
74HC595
IC2A
QA
QB
QC
QD
QE
QF
QG
QH
QHP
13
RCK
12
74HC02
5V
IC6
G
RCK
10
11
SRCLR
SRCK
14
SER
QA
QB
QC
QD
QE
QF
QG
QH
QHP
15
1
2
3
4
5
6
7
9
74HC595
ADDITIONAL DEVICES
Optocouplers allow you to isolate and control shift registers with only two logic signals.
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ideas
1.2000
Figure 2
1.0000
0.8000
VOUT
0.6000
VIN
R=0.25
0.4000
R=0.1
R=0.025
0.2000
0.0000
1
33
65
129
161
193
225
TAP
Its not log, but its close. These curves approximate what you can obtain from an audio-taper
potentiometer.
design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
ZIP
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
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ideas
Figure 1
VD1
VD2
*10k
OUTPUT
2.5 TO 4.5V
LM385
*10k
VIN
0 TO 2V
+
10 mF
C2
0.1 mF
CERAMIC
60 TURNS
20 mH
SECONDARY
1N4148
60 TURNS
20 mH
PRIMARY
T1
1N4148
+
10 mF
100k
10k
A
BC237
10k
10k
(a)
NOTES:
* 1% 25-PPM METAL-FILM RESISTOR.
T1=2360-TURN BIFILAR ON R1'0 TORROID T38 MATERIAL.
10-kHz SQUARE
WAVE
22.5V 610%
BAV99 DUAL DIODE
IF
R1
VD1
VD2
CLAMP TO
TRANSFOMER
SECONDARY
VREF
1.25V
VI1
R2
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+
Q
2
IF
+
2
VI2
VIN
0 TO 2V DC
~10 mA
LM385
(b)
An isolation amplifier for instrumentation applications provides as much as 500V of galvanic isolation and uses only one low-cost transformer (a). The clamp circuit includes dc blocking, which VD2
provides (b).
February 3, 2000 | edn 141
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ideas
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ideas
0.082 mF, 5%
200k, 1%
5V
IC1 OPA340
5V
IN2
OUT
IN+
+
10 mF
0.1 mF
GND
IC2 PIC12C671
GND
A/D
5V
CLK
DAT
SW
5V
TMR0
ACQ
IC3 MAX323
IO1
IO1
CON2
GND
CPUPWR
CPUDAT
CPUCLK
CPUGND
5V
5V
CON1
IO2
IO2
IC4 EX039F
16.3 MHz
64 kHz
0.1 mF
5V
5V
C
B
A
STDBY
GND
0.1 mF
When the switch is in the acquire position, this data-acquisition-system circuit bypasses the keyboard and puts data into an Excel spreadsheet column at the rate of 1 point/sec.
The ADC inputs derive the commonmode dc operating voltage directly from
the input signal. The circuit has two requirements: The analog input signal
must remain between 0V and the 5V supply voltage, and the ac transients must remain below the 62V bipolar input range
of the ADC. In Figure 1a, R1 and the
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ideas
This ac-coupling circuit adds no distortion to the input signal. You can couple
a 1.1-MHz Nyquist frequency sine wave
into the ADC while keeping the THD below 282 dB.(DI #2479)
To Vote For This Design,
Circle No. 304
5V
Figure 1
C2
1 mF
1
2
R2
1.6k
VIN
R3
51
C3
56 pF
4.09V
5
6
C4
10 mF +
7
8
(a)
CONV
AGND1
CLK
AIN+
VSS
4 A
IN2
R1
1.6k
C1
1 mF
AVDD
NOTES:
C1, C2=FILM TYPE.
C3=COG TYPE.
C4, C5=CERAMIC BYPASS.
DGND
LTC1402
VREF
DVDD
AGND2
OVDD
DOUT
GAIN
OGND
BIP
16
2.2M SAMPLES/SEC
15
35 MHz
14
13
12
11
3 TO 5V
10
SERIAL OUT
C5
10 mF
GROUND
10 mF
10
80-MHz
FULL-POWER BANDWIDTH
1-kHz
HIGHPASS
210
46 MHz WITH
R3-C3
220
AMPLITUDE RESPONSE
(dB)
230
240
250
>60-dB
REJECTION
260
(b)
270
1z1023 0.01
0.1
10
100 1z103
FREQUENCY (Hz)
You can use fully differential analog inputs, such as those of the LTC1402 ADC, to ac-couple an analog signal without this midsupply bias voltage (a).
The circuits frequency response includes a low-cutoff pole at 1 kHz and low-frequency rejection of 260 dB (b).
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ideas
D5
Figure 1
C5
3.3 mF
D4
C4
3.3 mF
D3
C2, 3.3 mF
D1
6.8 mH
VIN
ONE CELL
LI-ION
VGATE(2)
25V, 10 mA
C3
3.3 mF
D2
VCOL
5V, 250 mA
8
2
IC1
LM2621
2.2 mF
1
500
C1
68 mF
M1
100 mF
200k
5
4
150k
39 pF
51k
A step-up regulator, IC1; a charge-pump inverter comprising C2, C3, D2, and D3; and a charge-pump doubler comprising C4, C5, D4, and D5 produce the
three voltages necessary for active-matrix-LCD applications.
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nominal values. The efficiency of this circuit varies from 75 to 82% when operating from a one-cell lithium-ion battery.
(DI #2477)
To Vote For This Design,
Circle No. 305
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
ZIP
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
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ideas
Figure 1
0
SWITCH_INPUT (7 TO 0)
5V
2
3
4
5
RA0
RB0
RA1
RB1
RA2
RB2
RA3
IC1
PIC16C63
5V
RB3
RB4
20
C1
10 nF
VDD
RB5
VSS
RB6
RB7
21
R1 TO R8
4.7k
0
22
23
24
25
26
27
28
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ideas
5V
12
Figure 1
DIVIDE BY 2
7474
V+
(2.5 kHz)
14 FILIN
5
FILOUT
LVSHF
CLKR
CLKIN
10
AGND
V1
7
10002RPS CLOCK
(FOR 10 RPS, USE 100-kHz CLOCK.)
CLOCK450 2 FCO
15V
5V P-P
SLOWER
2V P-P
FASTER
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ideas
Figure 2
NOTES:
ALL OP AMPS USE 612V POWER SUPPLIES.
ALL OP AMPS ARE MC34084.
CONTROL, DIRECTION,
ACCELERATION, BRAKING
OPTICAL
ENCODER
INDEX OUT
START/STOP
START/STOP
MOTOR
DRIVE
MOTOR
CONTROL
SIGNAL
DIVIDE BY 10
RANGE
INTEGRATOR
MC34084
74HC74
MC14017
31
5V
14
5
FILIN
V+
FILOUT
CLKR
0.22 mF
3
2
75k
12
CLAMP
DIODE
4.3V
OP AMP 5
DIVIDE BY 2
30.1
2
2
3
+
OP AMP 4
INTEGRAL CONTROL
0.1 mF
+
2
FROM START/STOP
CONTROL CIRCUITS
OP AMP 1
75k
0.1 mF
10k
LMF 40CIWM
503 CLOCK
STOP
SWITCH
2k
3.3k
2k
10k
SPEED CLOCK
CLOCK AT 10003RPS FOR 31 RANGE
CLOCK AT 10003RPS FOR 30.1 RANGE
2
SPEED
TRIM
5V
2k
3 +
OP AMP 2
200k
APPROXIMATELY 1.25V
EXAMPLES:
31 RANGE
CLOCK=60 kHz.
MOTOR SPEED=60 RPS (3600 RPM).
LMF40 CUTOFF F0=1200 Hz.
ENCODER DIVIDED BY 20=1500 Hz.
LMF40 OUTPUT=2V P-P NOMINAL.
30.1 RANGE
CLOCK=60 kHz.
MOTOR SPEED=6 RPS (360 RPM).
LMF40 CUTOFF F0=1200 Hz.
ENCODER DIVIDED BY 2=1500 Hz.
LMF40 OUTPUT=2V P-P NOMINAL.
10k
10k
5.1k
LOOP-GAIN SET
5V P-P
SLOWER
2V P-P
OPERATING POINT
(1500 Hz)
FASTER
3 +
6
PROPORTIONAL
CONTROL
OP AMP 3
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ideas
1.8
1.8
1.6
1.6
START-UP VOLTAGE (V)
Figure 2
1.4
1.2
WITHOUT LOAD SWITCH
1
1.4
1.2
WITHOUT LOAD SWITCH
1
0.8
0.8
WITH LOAD SWITCH
0.6
0.01
(a)
0.1
1
10
LOAD CURRENT (mA)
100
1000
(b)
0.1
1
10
LOAD CURRENT (mA)
100
1000
The load-disconnect switch in Figure 1 allows the regulator to start up with heavy loads and low input voltages (a). A slight modification of the circuit
in Figure 1 provides 5V-output operation (b).
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nous boost converter whose bootstrapped operation cannot start until its
output voltage exceeds the internal
UVLO threshold of 2.3V. You can overcome this start-up limitation with an external power MOSFET, Q1, operating as
a load-disconnect switch, and by using
the power-OK (POK) comparator built
into many low-voltage switching regulators. R3 and R4 set the POK threshold at
2.5V, allowing VIN to rise above the UVLO
threshold. Q2 inverts the POK output be-
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Figure 2
RXDATA
CLK
RXLOCK
SHIFT
REGISTER
QN
PRBS
ERROR
QM
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ednmag.com. Click on Search Databases and then enter the Software Center to
download the file for Design Idea #2489.
(DI #2489)
To Vote For This Design,
Circle No. 407
X1
UTD
Figure 1
UTD
CLK
X4
UTD
X3
INV
X6
AND2
UTD
4
QB
(a)
(b)
Two AND gates and two delay lines generate a dead-time element in
Spice (a). When both inputs are high, the output is a logic one (b).
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LISTING 2HALF-BRIDGE DRIVER IN PSPICE
Figure 2
g
IIN
+
DT=350 nSEC
VHIGH=10
VLOW=100 mV
RS=10
RGU
12
CLOCK
DEAD-TIME
GENERATOR
8
+VCC
40V
G
QU
S
QL G
+
VGU
22
MTP10N10E
6
VOUT
RGL
12
4
23
MTP10N10E
RLOAD
10
VC
VGL
(a)
lation of this generator is easy to implement. The netlists in listings 1 and 2 implement a half-bridge driver with a floating upper output in IsSpice4 (Intusoft)
and Pspice (OrCAD), respectively. The
BL (Listing 1) and EBL (Listing 2) inline
equations implement the AND gates of
Figure 1a, which saves you from using a
subcircuit arrangement. Typical applications include half-bridge drivers and synchronous rectifiers. You can easily tailor
any output polarity by reversing the corresponding Spice element. For instance,
if you want to reverse the upper generator, BU1, in Listing 1, simply replace the
line
V5(V(CLK).800M)
&
(V(TD1).800M) ? {VHIGH} : {VLOW}
with V5(V(CLK).800M) & (V(TD1)
.800M) ? {VLOW} : {VHIGH}.
Figure 2a portrays a typical application of the dead-time generator in a simplified half-bridge driver, and Figure 2b
shows the corresponding IsSpice4 waveforms. You can download both listings
from EDNs Web site, www.ednmag.com.
Click on Search Databases and then enter the Software Center to download the
file for Design Idea #2490. (DI #2490)
(b)
A typical application for the Spice dead-time generator is for simulating the operation of a halfbridge driver (a). IsSpice4 waveforms show a dead time of 350 nsec (b).
design
ideas
ter (Reference 2). For a two-pole filter, dielectric resonators help achieve input-tooutput bridging coupling (Reference 3).
You can also implement a two-pole
www.ednmag.com
design
ideas
Insertion loss
(dB)
40.3
17.8
6.2
4.0
2.0
0.8
0.2
0
0
0
0.2
0.7
1.7
3.0
4.4
8.6
14.2
17.8
26.2
3.38 mH
4.7 pF
1.5 TO 14 pF
1.5 TO
14 pF
27 pF
27 pF
2 pF
Figure 1
0.65 mH
1.5 TO
14 pF
50 pF
0.65 mH
1.5 TO
14 pF
50 pF
A bridging inductor across the input and output of a conventional two-pole bandpass filter creates
a general filter that provides nearby rejection peaks with degraded far-out selectivity.
TABLE 2RESPONSE OF A
TWO-POLE GENERAL FILTER
Frequency
(MHz)
13
15
17
18
18.2
18.3
18.4
18.6
18.8
19
19.2
19.4
19.6
19.8
20
20.2
20.4
20.6
20.8
21
21.2
21.4
21.6
21.8
22
22.5
23
23.5
24
25
30
Insertion loss
(dB)
9.8
11.2
14
22
29.2
>34 (peak)
28.6
18.2
12.6
7.3
4.0
1.6
0.5
0.2
0
0
0.2
0.8
1.8
3.6
6.6
8.0
10.4
13.1
16.2
24.6
>39 (peak)
29.8
25.2
22
20.4
References
1. Kurzrok, RM, General three-resonator filters, EDN, May 1966, pg 92.
2. Kurzrok, RM, Single component
changes bandpass into general filter,
Electronics, April 18, 1966 pg 95.
3. Cohn, SB, Microwave filters containing high-dielectric resonators, presented at Clearwater, FL, May 5 to 7,
1965, and printed in G-MTT Digest, pg
49.
design
ideas
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design
ideas
Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
I hereby submit my Design Ideas entry.
Name
Title
Phone
E-mail
Fax
Company
Address
Country
ZIP
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
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design
ideas
+
_
RG
V)
(V
20.5k
5.36k
1.5k
487
147
V*OS
mV)
(m
1300
450
160
100
90
Bandwidth
(kHz)
900
850
500
160
40
* Referred to input
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design
ideas
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design
ideas
Q1
2SB950
Figure 1
DI-4 IN5404
TR1 50 VA
110/220V AC
12V AC
16
2
1
6
7
2k
50
nF
+
1
V+
COSC
L1
100 mH
FERRITE CORE
R1
1k
+
D5
MR850
FAST
12V/20W
HALOGEN LIGHT
IC2
LM324
13
12
4
1
14
11
10
COMP
9
RCOMP
30k
C2
1000 mF
35V
PULSEWIDTH
MODULATOR
IC1
SG 3524
ROSC
R2
10k
15
5V REF
POT 1
10k
C1
1000 mF
35V
electronic transformers, which are basically switching power supplies that drop
the mains voltage from 110/220V ac to
12V dc thats pulsed at high frequency.
These systems generate higher RFI than
the design in Figure 1. In this design, because the controlled variable is current,
not voltage, you could use supplies higher than 12V ac to compensate for the
drop in the connecting wires in case you
wish to place the halogen bulb and dimmer at some distance from the transformer. (DI #2497).
11
+
1
3
2
GND
8
R4
60.4k
R3
2k
SHUNT
0.1V, 5W
CCOMP
10 nF
NOTE:
FOR A 20W LIGHT, MAXIMUM CURRENT IS 1.6A;
THAT IS, A 0.16V DROP ACROSS THE SHUNT. THIS
DROP EQUALS 5V INPUT TO THE PWM IC. THE GAIN
OF THE NONINVERTING OP AMP IS 31.2.
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design
ideas
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design
ideas
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design
ideas
the output reaches VIN, the op amps output (status) becomes 0V, and the handler
stops incrementing the bit pattern presented to the DAC.
This final digital value corresponds to
the analog input VIN. For each occurrence
of INT 1CH (Ticker), the design completes a conversion cycle. Make sure that
the handler routine does not exceed the
time of occurrence of the interrupt. You
can implement a successive-approxima-
Frequency
500 Hz
700 Hz
1000 Hz
1050 Hz
Closest half-cycle
time period obtainable
msec
with 25-m
interrupt interval
100
700
500
475
Period of halfmsec)
cycle (m
1000
714
500
476
VCC
Figure 1
Error
(%)
0
1.96
0
0.21
Count
1000/25=40
700/25=28
500/25=20
475/25=19
C4
1 mF /16V
C1
10 nF
R3
8.2k
Y1
24 MHz
C2
22 pF
C3
22 pF
RST
P30/RXD
P31/TXD
XTAL2
XTAL1
P32/IINT0
P33/IINT1
P34/T0
P35/T1
10
GND
2
3
4
5
6
7
8
9
IC1
89C2051
VCC
P17
P16
P15
P14
P13
P12
P11/AIN1
P10/AIN0
P37
20
19
18
17
16
15
14
13
12
VCC
f1
f2
f3
f4
f5
f6
VCC
R1
10k
R2
10k
f7
f8
11
www.ednmag.com
design
ideas
Period of half-cycle
msec)
(m
500
476
455
333
294
250
Closest half-cycle
period obtainable with
msec interrupt interval
18-m
504
468
450
324
288
252
shows the new accuracy figures with fewer frequencies.You can download Listing
1 from EDNs Web site, www.ednmag.
com. Click on Search Databases and
then enter the Software Center to down-
Error
(%)
0.8
1.68
1.11
2.7
2.04
0.8
Count
504/18=28
468/18=26
450/18=25
324/18=18
288/18=16
252/18=14
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design
ideas
Fax
Company
Address
Country
ZIP
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design
ideas
D1
(MURS120)
MBRS130
T1
(COILTRONICS)
CTX03-14439
5V
100 mF
100 mF
+
5V AT 1A
MMDF3N03HD
1
300
300
MAX253
IC1
D2
MBRS130
(MURS120)
5V
6
0.1 mF
90
SCHOTTKY
ULTRAFAST
MURS120
70
MBRS130
80
60
EFFICIENCY (%) 50
40
30
20
10
100
200
300
400
500
600
700 800
IOUT (mA)
Figure 2
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design
ideas
have a built-in SPI (serial-peripheral-interface) port that you can use to effect serial programming. The SPI port uses only
the system-clock (SCK), master-output/
slave-input (MOSI), and master-input/
slave-output (MISO) pins. The AVR data
book requires that, to place a mC in serial-programming mode, you must first
pull the Reset and SCK pins low (Reference 1). Then, the mC must execute a
programming-enable instruction before
it can execute any program of erase instructions.
Hence, you need four pins to control
the programming of a mC. For instance,
the control signals from the AT89C4051
port pins P1.4 to P1.7 are for 40-pin mCs,
the signals from P1.0 to P1.3 are for 20-
VR1
JP1
5V
9V DC
78L05
+
Figure 1
C2
0.1 mF
C1
10 mF
VCC
1
20
R2
10k
LED1
P1.7
11
P3.7
P1.6
P1.5
5V
P1.4
C4 +
10 mF
16
C5
10 mF
+
4
+
TO PC SERIAL PORT
COM1
J1
2
3
IC1
3 MAX232 5
7
8
P1.2
C7
4.7 mF
9
10
6
15
19
MOSI
18
MISO
17
SCK
16
RESET
15
RESET2
37
36
35
34
33
32
P3.2
20
30
14
12
19
29
13
13
18
28 MISO2
14
17
27 MOSI2
15
16
26
16
15
25
17
14
24
18
13
23
12
CR2
4 MHz
RESET3
6
CR/CR3
4 MHz
XTAL1
VCC2
RX
TX
31
11
P1.1
P1.0
C9
0.1 mF
38
C8
4.7 mF
5V
39
40-PIN
ZIF SOCKET
10
P1.3
2
C6 +
4.7 mF
R3
10k
IC2
AT89C4051
C3
4.7 mF
R1
330
VCC
RST
40
7
P3.3
8
P3.4
9
P3.5
SCK2
VCC3
SCK3
19
12
22
20
10
11
21
MISO3
MOSI3
GND
Exploit the power of Atmels AVR mCs, using this easy-to-build programmer.
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design
ideas
References
1. 8-bit RISC Microcontrollers Data
R1
10
12V
Figure 1
C8
0.1 mF
R2
51
IC1
LTC1430
R3
16k
R5
15k
15 PV
CC2
14
VCC
11
FSET
12
IMAX
8
SD
10
COMP
9
SS
R4
10k
Q2
TP0610T
RESET
C6
0.01 mF
R7
10k
R10
10k
C9
0.01 mF
Q5
Q4
2N3904
R9 2N3904
20k
C12
1 mF
R11
10k
C11
220 pF
C1
330 mF
6.3V
R8
13k
C14
1500 pF
+ C13
22 mF
35V
SGND
PVCC1
G1
IFB
G2
PGND
2SENS
+SENS
FB
C4
1 mF
C
+ 1
330 mF
6.3V
5V
C2
C
3
+ 330 mF +
330 mF
6.3V
6.3V
Q1
IRF7801
1
L1
13
16
3
5
7
6
R6
1k
Q3
IRF7801
E1
+
2.4 mH
+
D1
MBRS130
C7
330 mF
C10
330 mF 6.3V
6.3V
C15
0.1 mF
+ C8
330 mF
6.3V
OUTPUT
3.3V AT 7A
E2
2
You can add a latch-off current-limiting feature to a simple pulse-width-modulation controller by adding a few external components.
www.ednmag.com
design
ideas
Figure 1
47k
0.1 mF
10
1
1000 pF
2
3
C2
2200 pF
R1
2.2k
IC1
LTC1438-ADJ
10
C1
1000 pF
4
5
POR2
82 pF
6
7
8
9
LB0
47k
C6, 1000 pF
C7, 2200 pF
10
11
R5
2.2k
12
13
14
SENSE+1
RUN/SS1
SENSE21
BOOST 1
VOSENSE1
ITH1
TGL1
SW1
POR2
VIN
COSC
BG1
SGND
LBI
LBO
SFB1
ITH2
VOSENSE2
INTVCC
PGND
BG2
EXTVCC
SW2
TGL2
SENSE22
BOOST 2
SENSE+2
RUN/SS2
28
27
10
0.1 mF
50V
0.1 mF
Q1
26
R2
0.01
25
24
23
CMDSH-3
0.1
mF
22
21
1 mF
Q2
4.7 mF
10V
19
C11 TO C13 +
330 mF
50V
33
L1
5.2 mH
VIN1
5.5 TO 28V
1M
280k
R3
35.7k
1000
pF
100 pF
D1
C3 TO C5
330 mF +
6V, 33
R4
11.0k
D2
C8 TO C10
330 mF
6V, 33
R7
20.0k
100 pF
R8
35.7k
1000
pF
Q3
20
18
17
CMDSH-3
L2
5.2 mH
0.1 mF
16
R6
0.01
Q4
VOUT1
5V/8A
1 mF
10V
1 mF
10V
VOUT2
3.3V/8A
15
0.1 mF
1000 pF
MMSD914
10
MMSD0.1 mF 914
10
0.1 mF
C14 TO C16 +
330 mF
35V
33
VIN2
5.5 TO 2.8V
0.1 mF
NOTES:
C11 TO C13, C14 TO C16=SANYO 35CV330GX.
C3 TO C5, C8 TO C10=KEMET T495X337M006AS.
D1, D2=MOTOROLA MBRD835L.
L1, L2=PULSE ENGINEERING PE-53700.
Q1, Q4=SILICONIX SUD50N03-10.
Q2, Q3=SILICONIX Si4420DY.
R2, R6=IRC LRF2512-01-R010-J.
A single IC regulates both 5 and 3.3V outputs; each output delivers 8A.
www.ednmag.com
design
ideas
Figure 1
1N4005
1N4005
RLOAD
IRFP264
10
IRFP264
10
6.8k
10k
3W
2N3906
4
50k
47k
3
47 mF +
25V
CW
5
TLC555CP
1N5242B
100k
470k
6
7
0.1 mF
This smart switch provides a small initial current for loads with a normally high inrush current.
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design
ideas
12V
Figure 1
R1
27k
C1 +
150 pF
Q1
2N3904
C2
0.1 mF
J1
R9
1.5k
Q2
2N5460
R4
10k
R3
1k
Q3
2N3906
S
R2
20k
FROM PC MIC
C3
0.1 mF
C4
0.22 mF
R7
10k
R5
1M
R10
2k
R8
360k
R6
1M
J2
R11
2.4k
R12
10k
TO PC MIC INPUT
12V
R15
10M
R14
22k
J3
C5
0.1 mF
FROM PC SPEAKER
R13
1k
R19
IC1A
8 LM393N 2.2M
3
+
1
2
R18
1
4
1k
R16
20k
R20
220k
R22
10M
R21
220k
5 +
IC1B
4 LM393N
R23
10k
R24
4.7k
TALK
D2
LED
7
D1
1N4148
R25
150k
C6
0.022 mF
R17
20k
Eliminate annoying echoes from loudspeaker-microphone feedback by using this simple circuit.
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design
ideas
VOUT
D3
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design
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Company
Address
Country
ZIP
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
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design
ideas
1 2
A 1
4
0
5
1
6
0
7
0
8
1
9 10
0 0
3
1
11
(a)
11
11
11 12 13 14 15 16
0 0 1 0 1 0
17 18
1 1
19 20
1 0
11
11
BIT F
Figure 1
(b)
Five delay cells and an XOR gate (a) configure the data stream (b).
www.ednmag.com
design
ideas
clock pulse and a 125-msec period. Rising edges generate the interval number,
and falling edges generate the data out.
Because 244 nsec is much less than 125
msec, data out is present in all intervals.
Concurrent processing
produces fast priority selector
Itamar Elhanany, Ben-Gurion University, Beer-Sheva, Israel
riority-encoding cirN
cuits are common
Figure 1
Y
in high-speed digital applications, such as interN
rupt controllers and task schedN
N
PRIORITY ENCODER
PRIORITY
ENCODER
PRIORITY ENCODER
X
ulers, for selecting the highest
priority set bit of all set bits in a
given binary vector. Typically,
the bit index corresponds to its
priority level. A project required
that several logic-function A straightforward realization of an N-bit priority selector involves cascading a series of 1-bit priority
blocks, as opposed to one, would selectors.
be enabled concurrently at any
XN
given time. Accordingly, the design goal
YN
was to identify the M highest priS
N
Figure 2
mM
/
(X
...X
)
1
N
ority admissible logic blocks. A
conventional 1-bit priority selector reXN21
YN21
ceives as its input an arbitrary binary vecS
N21
mM
tor and outputs a vector of the same size,
/
(X1...XN21)
where the location of the set bit correN
X
/
sponds to the position of the highest priority set bit in the input vector. Such a seXN2M
YN2M
N2M
lector may be described by the following
S
mM
/
(X1...XN2M)
Boolean expressions:
X1
i =1
i11
i 1
Yi =
i > 1.
X
=
X
i
j
i
j=1 j
j
1
=
design
ideas
Figure 1
IC1
R1
5.1k
IC2
5V
16
10
10k
3k
Q1
BC167
9
C
15
R
2
W
1 C
7 R
3k
13
Q4 14 5 I7
Q3 13 6 I6
Q2 12 7 I5
11 8
Q1
I4
9 I
Q4 6
3
5
10
Q3
I2
11
4
Q2
I1
12
Q1 3
I0
51k
14
+
15
1
1
LC
4
Io
R2
4.7k
R3
510
1N4002
1M
BZY10C12
1N4002
IC3A
_
HEATER
VS
16
5V
10 nF
750
IC3B
_
6
BC259
IC4A
BC259
10k
231N4154
15V
5V
MAINS
220V
50 Hz
12.1k
AC/DC
CONVERTER
42.2k
10k
15V
220
10
300
5V
5.6k
300
1.5k
+
_
IC3C
10k
8.56k
1.65k
NOTES:
IC1=4520.
IC2=MDAC08 (TESLA).
IC3=TL084.
IC4A=4011.
100 mF
16V
R4
1.5k
2
Io
470 nF
400V
1k
Q2
BC167
920
12
IC3D
_
11
13
15V
14
1 TIL112 5
OPTOCOUPLER
TRIAC
BTA08/400
Depending on the objects temperature, which Q2 senses, IC4A passes all, part, or none of the triggering pulses to the triac that controls the heater.
www.ednmag.com
design
ideas
ous inputs of the possible paths and detects the tag at the output, or speaker.
A direct-sequence noise generator
running at 6 kHz furnishes the local oscillator, and a 9-kHz square-wave, lowpass filter that is filtered for its fundamental furnishes the sine-wave carrier.
The circuit derives both of these signals
from an 18-kHz clock. A PIC12C508A,
running at 4 MHz, generates the local os-
LEVEL SET
SO IT DOES
NOT OVERDRIVE
LOWPASS
FILTER
SPREAD-SPECTRUM
CONDITIONAL INVERTER
GENERATOR
(DOUBLE-BALANCED MIXER)
TP2
9-kHz LOWPASS FILTER
(GAIN=1)
10k
CONVERTS SQUARE WAVE
1
TO SINE WAVE (GAIN=4) 1200 pF
TP3
5V
0.01 mF
2
Figure 1
86.6k
0.1 mF
1200 pF
1%
13.7k
LM358
+
4 0.01 mF
8.25k
6
4.99k
1200 pF
1%
25V
1%
5.90k
2
LM358
+
CARRIER
44.2k
7
1200 pF
1%
0.01 mF
5V
19.6k
DIRECT-SEQUENCE
0.01 mF NOISE GENERATOR
4 MHz
PIC12C508
D 3
GP4
5 VSS
22 pF
S 2
SST215
3
SUBSTRATE TIED
MOST NEGATIVE
25V
1.0k
4
G
D
3
5V
1.0k
SPREAD-SPECTRUM DETECTOR
22 pF
0.01 mF
LM358
3
NOISE_DISABLE
FOR AUDIO TONE
G
S 2
4.99k
52.3k
NOISE_ENA
RECEIVED-AUDIO
SPREAD-SPECTRUM
SIGNAL WITH A
LOT OF TVAUDIO NOISE
LM358
25V
44.2k
CP1
10k
SST215 1
25V
0.01 mF
CP0
LM358
52.3k
1 V
DD
2
GP5
10k
115k
4 0.01 mF
4.99k
25V
10k
10k
TP4
CONDITIONAL INVERTER
(DOUBLE-BALANCED MIXER)
(GAIN=2)
47.5k
820 pF, 1%
115k
115k
5
4.32k
820 pF
1%
+
LM358
DEMODULATED 9-kHz
CARRIER TO
TONE DETECTOR
80.6k
5V
0.01 mF
7
3 +
2
LM358
2
1
0.01 mF
(b)
(a)
25V
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design
ideas
Figure 2
100
90
1.6
70
1.2
VOUT (V)
EFFICIENCY (%)
80
60
50
0.8
40
30
0.4
20
10
0
0
(a)
0
0.1
10
LOAD CURRENT (mA)
100
1000
(b)
20
40
60
80
100
120
The circuit provides maximum efficiency for load currents of 10 to 100 mA (a) and maintains its output level for load currents as high as 100 mA (b).
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TABLE 2COMPENSATED
AMPLITUDE RESPONSE
Frequency (MHz)
11
11.5
12
12.5
12.8
13.1
13.4
13.56
13.7
14
14.3
14.46
14.6
14.9
15.2
15.5
15.8
16.5
17
18
19
20
25
30
35
40
45
50
60
design
ideas
Figure 1
I
VQ1A1VQ1B = 0.026 ln 2 =
I1
V41V3 .
The circuit applies this voltage differential to the bases of Q1C and Q1D. Because all four transistors closely match
one another, the ratio of currents I3/I4
equal the ratio I2/I1, or
I
I
0.026 ln 2 = 0.026 ln 3 .
I
1
I4
I1
R1
20k
V1
I2
47 pF
2
IC2A
+
BATTERY
UNDER
TEST
R4
20k
ILOAD
11
10
Q1A
6.8k
I4
2
IC2D
+
Q1B
Q1C
Q1D
RSET
1k
+V
I3
5
3.3k
+V
47 pF
12
V5
1.23V
IC2C
+
V6
R5
6.8k
14
R3
24.3k
2V
V2
6.8k
R6
1
2W
2
IC2B
+
6.8k
IC1
LM3046
47 pF
3.3k
R2
20k
V4
V3
1
Q2
MTD3055
(HEAT SINK)
SET POWER
47 pF
D1
LM4041-1.2
2V
Q1E
13
231N4001
SUBSTRATE
+V
2V
23100 mF
16V
6.3V AC IN
+
+
This active-load draws constant power; load current is inversely proportional to the applied voltage.
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design
ideas
= =
4 ,
I1 R1 R 2 I 4 R 3 R 4
or
V6 = (V53V2 ) V13
R1 R 4
3 .
R2 R3
A small power supply that outputs approximately 6.3V ac powers the circuit.
Two 1N4001 diodes half-wave-rectify the
positive and negative voltages, and two
100-mF capacitors provide filtering. The
extremely light load of the circuit means
that postfilter regulation is unnecessary.
If portability is necessary, you could power the circuit from a pair of series-wired
9V batteries. You can also use asymmetrical power supplies, but you need a positive voltage of around 8V to allow Q2 to
turn fully on. If you substitute a different op amp, make sure that it can withstand the power-supply voltages. Q2 dissipates most of the power, so it needs an
attached heat sink. (DI #2512)
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Edited by Bill Travis and Anne Watson Swager
ideas
UNITS
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design
ideas
Figure 1
1N3612
4
LM2905
'7V DC
3
8
CT
200M
RT
1N755
(7.5V)
100 mF
10V
5 mF
POLYCARBONATE
2N5021
(P-CHANNEL)
10k
2W
LINE
FAN
SSR
1
LOAD
R
1.5k (TYPICAL)
Gain control of your bathroom fan by using this simple time-out circuit.
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design
ideas
sirable, as the core voltage can vary without upsetting the termination-voltage set
point. The circuit in Figure 1 is a 6A power-supply design that generates a termination voltage regulated to 1/2 VCORE. The
circuit targets applications in which the
core voltage is approximately 1.8 to 3.6V.
An LM2636 synchronous-rectifier controller switching at 300 kHz provides an
efficient power converter that operates
from a 5V input. Because the LM2636 is
designed to operate at a fixed output voltage (as determined by control bits 14
through 18), the circuit in Figure 1 uses
Figure 1
5V
10
CR1
MBR0530T3
2.2 mF
MLCC
N/C
13
PWR
GD
19
OUT
EN
VCC
2
BOOTV
I MAX
HS GATE
0.1 mF
MLCC
2.2k
IRF7807
(22)
1000 mF
10V
(SEE
NOTES)
CR2
MBRD320
20
8
4.7 mH
220
IFB
LM2636
LS GATE
P GND
S GND
FREQ
ADJ VID 0 VID 1 VID 2 VID 3 VID 4 SENSE VREF FB
12
18
82k
17
N/C
16
15
N/C
14
11
3.9
0.01 mF
MLCC
IRF7807
(32)
1500 mF
6.3V
(SEE
NOTES)
L1
220 pF
MLCC
E/A
OUT
R5
2k
C1
TERMINATION
VOLTAGE
(ONE-HALF
CORE VOLTAGE)
GND
R3
56k
2200 pF
MLCC
R6
430
10k
1
51
10
R4
10k
N/C
2.2 mF
MLCC
10k
IC1B
3
2
()LM324A
7
()LM324A 11
6
2
IC1A
5
+
1k
C2
1 mF
MLCC
R2
0.5%
4.99k
FROM
CORE
VOLTAGE
()LM324A
10
()LM324A
12
+
14
IC1C 13
2
10k
1%
+
IC1D
2
0.1 mF
MLCC
0.1 mF
MLCC
R1
4.99k
0.5%
10k
1%
NOTES:
USE LOW-ESR ALUMINUM ELECTROLYTIC CAPACITOR SUITABLE FOR 300-kHz SWITCHING APPLICATIONS.
UNLESS OTHERWISE SHOWN, RESISTOR TOLERANCES ARE 5%.
MLCC DESIGNATES A CERAMIC CAPACITOR WITH AN X7R OR X5R TEMPERATURE RANGE.
Optimize your CPUs performance by feeding it a termination voltage thats exactly half the core voltage.
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design
ideas
put of the LM2636, which would normally sense the regulated output voltage.
Because the termination output voltage
must be variable (to track the core voltage), a fixed 2.5V goes to the sense pin,
and the control pins 16 and 18 are
grounded. These connections program
the internal DAC for a 2.5V output. This
Figure 1
HOT
R2
1.5k
but this technique increases the program-scan time and ties up valuable
timers. The solid-state, electrically isolated circuit in Figure 1 debounces single
inputs without slowing the PLC module.
Optoisolators IC1 and IC2 provide electrical isolation for the ac sources at the input and output. IC3 is a CMOS switch debouncer whose output (a 4V logic high)
appears following a fixed 40-msec delay.
A 63-kV pullup resistor, connected internally between IN and VCC, forms a
voltage divider with R1. R1s value ensures
a logic low of less than 0.8V at IN when
IC1
TLP626
IC3
MAX681
5V
1
4
3
24V AC
2
NEUTRAL
GND
2 IN
VCC
OUT
5V
4
3
R1
10k
5V
IC2
TPL3043
R3
820
NOTES: FOR 120V AC INPUT OR OUTPUT,
R2=7.5k, 2W;
R4=160;
ALL RESISTORS ARE W.
ZC
R4
33
HOT
24V AC
RLOAD
NEUTRAL
2N6073B
2N7000
This debouncer circuit allows an isolated ac voltage to control a separately isolated ac source.
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An ac switch (top trace) turns on and then briefly bounces off; the output of the associated
debouncer circuit turns on cleanly (bottom trace).
Figure 1
EXTERNAL
RESET INPUTS
RESET 0
RESET 1
RESET 2
RESET 3
ALL DIODES
ARE 1N914B
RESET 4
RESET 5
RESET 6
RESET 7
2 D0
3 D1
Q0
4 D2
5 D3
Q2
6 D4
7 D5
Q4
8 D6
9 D7
11
RESET
1
OC
Q1
Q3
Q5
Q6
Q7
74HCT574
IC1
READ
CHIP ENABLE
19
18
17
16
15
14
13
12
TO CPU
DATA
BUS
74HCT32
IC2
design
ideas
VCC
Figure 1
VCC
15
16
40
P1.0 DATA
P1.1 CLK
IC1
74HCT4094
8051
CONTROLLER
P1.2 RS
P1.3 E
4 Q0
D0 7
5 Q1
D0 8
6 Q2
D0 9
7 Q3
D0 10
14 Q4
D0 11
13 Q5
D0 12
12 Q6
D0 13
11 Q7
D0 14
LCD
MODULE
2
5
RS
E
VCC
20
VCC
Figure 2
VCC
16
40
P1.0 DATA 1
8051
CONTROLLER
P1.1 CLK
P1.2 RS
P1.3 E
6
9
IC1
26LS31
15
CONNECT AT
REMOTE LOCATION
TO IC2 PINS
10
11
14
20
13
12
8
VCC
VCC
16
CONNECTION
FROM IC1 PINS
1
2
7
6
9
10
15
14
14
3
5
IC2
26LS32
DATA
CLK
11 RS
13 E
2
3
IC3
74HCT4094
8
12
15
4 Q0
D0 7
5 Q1
D0 8
6 Q2
D0 9
7 Q3
D0 10
14 Q4
D0 11
13 Q5
D0 12
12 Q6
D0 13
11 Q7
D0 14
RS
E
LCD
MODULE
VCC
2
Extend Figure 1s scheme to long distances by using line-driver and -receiver ICs.
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Fax
Company
Address
Country
ZIP
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Edited by Bill Travis and Anne Watson Swager
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er, the circuit requires an additional refinement because pure tones are unpleasant. Thus, some modulation is necessary. This circuit allows for dual tones,
such as a police siren, or sweeping tones,
such as an ambulance siren, using a
switch. The circuit provides dual-tone
operation using a bipolar transistor that
shorts a capacitor on and off in the capacitive section of the oscillator path. The
sweeping tone is a mixed AM/FM format
that the circuit produces by biasing the
relaxation oscillator with a triangular signal from a lower frequency oscillator.
This bias changes the threshold level of
the modulating tone, which produces
modulation of the fundamental frequency and the aspect ratio of the output.
A regulated power source biases the oscillator section to minimize the high-frequency oscillators voltage sensitivity. A
current source, which is insensitive to
supply voltage, controls the final stage.
This control, instead of a direct connection to the supply voltage, provides some
protection in the event of a short circuit
and provides similar output independently of the antenna resistance. The LED,
which the circuit uses as a voltage reference, also indicates circuit activity. The
supply voltage can vary from 7 to 12V or
higher if you take care of the BD140 transistors dissipation requirements.
To use the circuit, switch on an AM receiver and find a position without broadcast stations. Place the receiver close to
the generator, switch on the circuit, and
adjust the variable resistor until the tone
is audible. Move the receiver to find the
direction of better sensitivity. Then, use
the radio receiver to find where the twisted-pair cable goes.
Beware that this circuit produces EMI
not only in the AM-broadcast range, but
also over a wide frequency range due to
the high harmonic content of the generated signals. The use of twisted-pair cable reduces the amount of interference in
the far-field region. Therefore, use the
circuit cautiously, and disconnect the circuit as soon as you locate the cable. (DI
#2523)
VCC
Figure 1
OUT
IN
100 nF
GND
4.7
GREEN
7805
VIN
33 mF/60V
+
100 nF
BD140
33 mF/60V
1k
JP1
4
9
24k
10
VCC
470k
+
10k
12
11 1k
TWISTED CABLE
G
IFR9530
74HC132
13
74HC132
100 nF
10k
BC547
2.3k
100 nF
3 mF/25V
1
2
24k
74HC132
BC547
74HC132
10k
330 pF
10k
To discover the location of cable conduits, a relaxation oscillator applies current pulses to a twisted-pair cable, and an AM radio functions as a receiver.
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additional, secondary windings on T2
and the bridge rectifier support this function (Figure 3). Unfortunately, the core
choke, L1, can have no secondary windings because those windings cant supply enough power to the controller under maximum-duty-cycle conditions.
After adding an EMI filter and bridge
rectifier to the regulator input, the circuit
can work in stand-alone mode. With the
halogen lamp close to maximal. The prototype uses a cheap controller, the
UC3842, which operates in voltage mode
because of the presence of the R3/R4
divider.
To operate the circuit, you need to supply the controller. On power-up, C2
charges through R1 and R2, which starts
the switching. To keep the controller
running requires extra power to C2. The
programs the synthesizers internal registers. You can calculate the register values
using the program LMX2325.EXE (National Semiconductor). The values depend on the desired oscillation frequency, the external crystal, and the
reference-frequency values. R1, C1, and C2
implement a second-order loop filter, and
you can determine the component values
using the LOOPFILT.EXE (National
Semiconductor) program. The values depend mainly on the oscillation frequency and the VCO tuning sensitivity.
R2, R3, R4, and L1 form a T-network.
The design in Figure 1 assumes that a
50V load connects to ac-coupling capacitor C3. The T-section matches the syn-
5V
Figure 1
4
18k
3
1
XTAL
5V
VCC
2
0SC IN
30 pF
30 pF
VP
0SC OUT
D0
LMX2325
R1
10k
GND
5V
CLOCK DATA LE
6
12
VCC RESET
11
13
14
16
C2
4.7 nF
C1
680 pF
CLOCK DATA LE
JTOS-3000P
R4
COP8SAA7
GND
VCC
GND RF OUT
1
13
R3
22
FIN
10
V-TUNE
11
L1
R2
4.8 nH
C3
22 10 nF
RF OUT
2.3 TO
2.5 GHz
thesizer FIN pins input reactive impedance of 40-jv to the 50V output impedance of the VCOs RF OUT pin and output load. If f is the oscillation frequency
in hertz, X is approximately equal to
(23631029)f1162. Therefore, the following inductor value for L1 cancels the
reactance:
L=
99
19
12 10 .
design
ideas
110V
V+
V1
_
10k
INB
LT1684
INA
100 pF
2 COMP1
20 pF
3
4
1N5817
5
6
7
COMP2
BGOUT
AMP_IN
LIM1
GATE+
VNEG
VPOS
GATE1
ATREF
LIM+
OUT
14
10k
V+
1k
V1
LT1017
10k
7
LT1017
Figure 1
2
100k
100k
13
IRF610
12
100
11
10
D1N4001
C1
0.22 mF
9
8
R1
5.6k
6.8 nF
FMB1601
FERRITE BEAD
0.1 mF
+
OUTPUT
1
R3
680k
C2
0.22 mF
6.8 nF
R2
2.7k
100k
100
IRF9610
1110V
An active-filter IC, the LT1684, and a pair of MOSFETs produce a high-voltage, high-quality sine wave at the output.
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design
ideas
1
.25 / )
of 95V (7-REN load capability), a ring
Q
frequency of 20 Hz, and a bandpass Q of
R2 =
.
9.4. A square wave with peak amplitude
Given capacitor values of 0.22 mF,
(2Q 21H0 )( 0 C)
A has a fundamental component with an Q59.4, |HO|560, and vO52p(20 Hz),
Figure 3
10k
MURS160 0.47 mF
160V
2
+
COILTRONICS
14293-X3
5 TO 15V
INPUT
0.47 mF
160V
7.8
1 nF
1N4001
220 mF
160V
10 mF
160V
20 pF 3
4
1N5817
4
39
4
SW
IC1
LT1270
7
1
FB
VC
GND
5
LT1684
100 pF
11
9
VIN
10k
MBRS1100
6
5
5
6
7
91V
3
0.1 mF
INB
MURS160
12
44V
OUTA
VCC
IN2A
OUTB
IN+A
IN2B
VEE
IN+B
5.6
220 mF
160V
COMP1
100k
LIM2
GATE2
LIM+
ATREF
OUT
6
5
10k
10k
100k
IRF610
100
0.22 mF
5.6k
FMB1601
FERRITE BEAD
6.8 nF
+
0.1 mF
680k
50k
0.22 mF
1k
GATE+ 11
10
VPOS
VNEG
LT1017
INA 14
13
COMP2 BGOUT
12
AMP_IN
2.7k
DN14001
+
OUTPUT
2
6.8 nF
H11AG1
0.01 mF
2k
6
5
1
IRF9610
91V
100
50k
2
4
H11AG1
LOAD (REN)
7
10
R1
V (PEAK)
5.6k
95V
6.8k
70V
10k
100k
R2
R3
2.7k 680k
3.3k 620k
A dc-to-ring-tone converter combines the circuit from Figure 1 with a high-voltage power supply.
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design
ideas
5V
Figure 1
7805CT
DC POWER JACK
1
3
IN
0.22 mF
OUT
GND
2
3
0.1 mF
J1
1
2
IC1A
R LS123
CX
14
5V
Q 13
15
5V
RX/CX
33 pF
5V
220
8.2k
0.1 mF
50k
R1
4
2
33 pF
10 B
ICIB
11
R LS123
6
CX
7
RX/CX
12
5V
PR
IC2A
LS74
CK
CLR
1
8.2k
Two one-shots and a D flip-flop comprise a pulse generator that can produce pulses of 5 to 850
nsec with a low repetition rate.
to TTL-compatible circuitry.
The circuit in Figure 1 uses two oneshot timers and a D flip-flop to create a
short, TTL-compatible positive pulse
when triggered with a TTL-compatible
positive edge. Because the circuit is positive-edge-triggered, the only requirement for the duty cycle of the triggering
device is that it meets the minimum input pulse width for the one-shot timers,
which is 40 nsec for the 74LS123, IC1.
IC1B provides a fixed pulse width of approximately 150 nsec. Via R1, IC1A provides a variable pulse width of 150 to
1000 nsec. A positive pulse at Input A
triggers each timer. This trigger inactivates IC2As CLR input and makes its CK
signal low. When IC1B times out, its positive-going edge clocks the logic 1 on the
D input of IC2A to Output B. When IC1A
times out, its output clears the Q output
of IC2A, taking Output B low. Thus, you
can express the pulse width at Output B
as follows: Pulse width of IC2A5pulse
width of IC1A2pulse width of IC1B.
The output pulse width for this circuit
is variable from approximately 5 to 850
nsec. You can produce a shorter pulse
width by using faster logic. The circuit
also allows for easy modification should
negative trigger inputs, output pulses, or
both be necessary. (DI #2528)
To Vote For This Design,
Circle No. 348
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design
ideas
5V
8
Figure 1
10k25
14
VDD
16
DECREMENT
OSC1
MRESET
1
A2
15
2
OSC2
A3
3
A4
IC6
18
B0 6
A1
B1 7
B 8
22 pF
1
7
17
A0
INCREMENT
GND
B7
13
VOUT
U/D
INC
IC0
CS0
4
22 pF
H
U/D
INC
IC1
CS1
L
B3 9
B4 10
B5 11
B 12
H
U/D
INC
IC2
CS2
L
H
U/D
NOTE:
IC0 TO IC5=MAX5160.
INC
IC3
CS3
L
H
U/D
INC
IC4
CS4
L
H
U/D
INC
IC5
CS5
L
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Design Idea Entry Blank
Entry blank must accompany all entries. $100 Cash Award for all published Design Ideas. An additional $100 Cash Award for
the winning design of each issue, determined by vote of readers. Additional $1500 Cash Award for annual Grand Prize Design,
selected among biweekly winners by vote of editors.
To: Design Ideas Editor, EDN Magazine
275 Washington St, Newton, MA 02458
Fax
Company
Address
Signed
Country
ZIP
Date
Your vote determines this issues winner. Vote now, by circling the appropriate number on the reader inquiry card.
Enter 10 at www.ednmag.com/infoaccess.asp
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design
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L4
C5
L4
C5
2/3
0.51
mH
68 pF
Multiplying the normalized filter in Figure 1 by the reference inductance and capacitance values
yields this 31.2-MHz, 50V filter.
Value
0.51 mH
0.13 mH
68 pF
50 pF
BNC female
Aluminum box
Cut by hand
Male/female
Type
Micro-Metals T 25-10 14T- #26
Micro-Metals T 25-10 14T- #26
CD-15 Series dipped mica
DC-15 Series dipped mica
Pomona 2447 panel receptacle
Hammond 1590A/Bud CU-123
Vector board 169P44C1
Amatom 9794-SS-0440
Quantity
Two
Two
Four
One
Two
One
One
Four
design
ideas
Z0
= 0.255 H ;
2 f 0
C0 =
106
= 102 pF.
2 f 0 Z 0
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output with less than 1% pulse-top aberrations. Comparator IC1 delivers a 1MHz square wave to current-mode
switch Q2-Q3. Note that IC1 obtains power between ground and 25V to meet the
transistors biasing requirements. Q1 provides drive to Q2 and Q3. When IC1 biases Q2, Q3 turns off. Q3s collector rises
rapidly to a potential determined by Q1s
collector current, D1, and the output resistors combined with the 50V termination resistor. When IC1 goes low, Q2 turns
off, Q3 turns on, and the output settles to
0V. D2 prevents Q3 from saturating.
The circuits output transition is extremely fast and singularly clean. Figure
2, viewed on a 1-GHz real-time-bandwidth oscilloscope, shows 850-psec rise
15V
Figure 1
TR1
200
510
0.5V AMPLITUDE
OUTPUT TRIM
240
D1
Q1
50V COAX
TR2
FRONT CORNER
PEAKING 200
1.2k
+
1k
OUTPUT:
1-MHz/850-PSEC
RISE TIME
5.1k
4.7 mF
510
43
50
TR3
D2
BASELINE TRIM
2 IC
680 pF
LT1394
+
25V
Q2
100
Q3
100
1k
1k
NOTES:
PNP=2N5771.
NPN=2N6304.
=HP5082-2810.
180
130
1k
25V
25V
25V
Need a fast, clean pulse? This simple circuit provides 500-mV, 850-nsec pulses with a high degree of purity.
0.1V/DIV
5 mV/DIV
500 pSEC/DIV
500 pSEC/DIV
Figure 2
Viewed with 1-GHz bandwidth, pulses are free of discontinuities and
anomalies.
Figure 3
Pulse tops exhibit less than 64 mV, or less than 61%, aberrations.
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design
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probably eliminate it by using striplinelayout techniques. The level of performance of this circuit requires some trimming. The oscilloscope you use should
have at least 1-GHz bandwidth. You adjust trimmers TR2 and TR3 for the best
pulse presentation. TR1 sets the output
amplitude at 500 mV across the 50V termination. The trims are somewhat interactive, although not unduly so, and
www.ednmag.com
design
ideas
set and clear bits in a word, and the everneeded shift-left and -right functions. As
an example, many of the three-wire serial devices need to have a setup word shifted to them. Suppose you need to shift the
setup word 0111 1101 first to an A/D converter to initiate a conversion on some
channel. You can use the functions in the
ActiveX control to easily effect the shift
operation, as follows:
Setup_word = Bits (01111101)
`Returns 125
For i = 0 to 7
Val = ShiftRight_8(setup_word,0)
`write val to the A/D here
next i
In the above example, val has the
values 1, 0, 1, 1, 1, 1, 1, 0 during each iteration of the loop. The routine can then
clock these bits to the A/D converter as
required by the hardware. If the operation requires MSB first, you can use the
ShiftLeft function. The SetBit and ClearBit functions are useful when using a port
as clock and data lines, because you can
set individual bits as needed instead of
doing entire port writes. Any modern
programming language that can use ActiveX controls, such as Agilent VEE, Visual Basic, Delphi, and others, can use the
functions given here. You can download
the ActiveX control from EDNs Web site,
www.ednmag.com. Click on Search
Databases and then enter the Software
Center to download the file for Design
Idea #2534. The routine includes all the
functions listed in Figure 1, plus a few
more, with application examples. (DI
#2534)
To Vote For This Design,
Enter No. 367 at
www.ednmag.com/infoaccess.asp
Figure 1
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design
ideas
VIN
Q1
MTD20P06HDL
10 TO
32V
RSENSE
50m
R1
20k
Figure 1
ILOAD
RS+
RS1
Q2
MMBT3906
49.9k
R2
20k
Q3
MMBTA63
RLOAD
249k
7
PG
IC1
MAX4172
S1
LOAD
CONNECT
V+
R3
249k
R4
1M
(DUAL)
NC
NC
OUT
Q4A
IOUT
VOUT
Q4B
VCC= 5V
4
GND
5
0.1 mF
ROUT
10k
Q4
MBT3904DW1TI
(DUAL)
VTHRESH
RTHRESH
10k
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design
ideas
LP
L
I11 jv P2 I2 .
n
n
L2 =
Figure 1
Out1
+
L1
V1
L2
I1
In2
I2
n:1
(b)
Out2
I2/n
LS
In1
V1
V2
2
2
In2
(a)
+
LP
I2
I1
In1
+
LP
n2
Out1
+
VX
2
+
VX/n
V2
2
Out2
Spice models simulate an ideal transformer (a) and a nonideal one (b).
Figure 2
V2 = jvMI11jvL 2I2 .
VOUT
design
ideas
1
L S = L P 2 21 ;
k
L
n = k 1 .
L
2
As an example, consider a
transformer that provides
an impedance transformation of 46 to 75V at 72 kHz.
It uses an RM8 ferrite core
with inductance factor
AL51600 nH. The measured inductances are L154.2
mH, L252.6 mH, and
LS520 mH. Figure 2 shows
the simulated transfer function of the transformer. You
can download Listing 1
from EDNs Web site,
www.ednmag.com. Click on
Search Databases and
then enter the Software
Center to download the file
for Design Idea #2539. (DI
#2539).
Reference
1. Coelho, J,A Spice model for the ideal transformer, Electronic Design, June
28, 1999.
D
RxD
CKR_ERRA
RD
D
Q
CKR_ERRB
RD
D
RxC
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ideas
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design
ideas
1
4
clk
mr
PAR2SER
clk_rx
mr_rx
CONTROL
MACHINE
valid_data
CONTROL
MACHINE
start_frame_rx
SHIFT
REGISTER
SHIFT
N REGISTER
CRC
GENERATOR
serial_ou
+
serial_in
2
SERIAL LINE
N parallel_out
CRC
CHECK
SER2PAR
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ideas
any A/D converters use an internal resistor ladder as a twopoint differential voltage reference
in the conversion. This method demands
that these two nodes remain steady. The
higher the resolution, the stronger the demand for quiet voltages. Figure 1 depicts
a simplified schematic of the LM985XX
reference ladder. Figure 1a shows the traditional decoupling scheme; Figure 1b
shows a proposed scheme. Typically, designers use two capacitors to decouple
each reference nodeone low-value capacitor and one of higher value because
the effective series inductance (ESL) of
the smaller capacitor is much lower than
that of the larger one. Contrary to tradition, you can eliminate these larger capacitors and replace them with one differential capacitor if you choose the
values wisely. Because the difference in
the reference voltages, DVREF, is important in conversion, this is the delta that
is of interest.
Figure 1b shows two common-mode
decoupling capacitors, C1 and C2, and the
differential capacitor, C3. The current
sources, I1 and I2, represent the average
currents pushing or pulling on the lad-
2
(C2 R P3 R P1 + C3 R P2 R P1 + C1 R P2 R P3 )
d;
[(C2 C3 + C1 C3 + C1 C2 ) R P2 R P3 R P1]
pole1 =
2
(C 2 R P3 R P1 + C 3 R P2 R P1 + C1 R P2 R P3 )
[(C 2 C 3 + C 1 C 3 + C 1 C 2 ) R P2 R P3 R P1 ]
pole 2 =
(d - 2) ;
(d << 1)
ZERO =
R 2 +R 1
R Rm
, and R PK = n
,
R 2 R 1 (C1 + C 2 )
R n + Rm
VDD
VDD
LM98502
Figure 1
VREFT
I1
VREFT
1048
R3 I2
C1
0.1 mF
C3
12 mF
C1
0.1 mF
DREF
I2
VREFB
C2
0.1 mF
C4
12 mF
(a)
LM98502
R1
524
I1
C3
12 mF
VREFD
I1
I2
C2
0.1 mF
328.2
R2
1048
R3 I2
I1
328.2
R2
(b)
More is not always better; the circuit in b provides better decoupling than the one in a.
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the power-MOSFET pair. A voltage-feedback sample, compared with the 1.2V reference source in a MAX951, IC7, provides
a closed-loop feedback to vary the value
of the constant-current source comprising Q7 and the optoisolator, IC8. This
variable constant-current source varies
the monostable output of IC3, which
feeds the IC6 NAND gates. The feedback
system thus maintains the proper pulse
width in the gate drivers.
You can easily modify the (squarewave) circuit for a sinusoidal output by
(text continued on pg 174)
12V
Figure 1
0.1 mF
8
R
IC4
MC4027
13
CK
7
IC2
555
10k
11
6
1 mF/
16V
K
9
Q
VEE
0.1 mF
16
12
10
1k
510
0.1 mF
10k
100k
15
14
5V
5V
0.1 mF
12V
16
10 mF
16V
10M
10 mF
25V
680
3
680
6
1.2k
IC8
4N35
4.7k
4
6
7
0.1 mF
5.2V
2.7k
VREF
1.2V
IC7, MAX951
6 12k
4.7k
+
2
1.5 nF
Q2
BC108
5.6V
12k
2
12k
56k
780
100k
2.2k
33 mF
25V
3
1
Q6
2.2k 2N1613
3.3k
1 mF
50V
10k
Q5
2N1613
0.1 mF
Q7
2N3905
15
14
C/R
C/R
13
CD
CD
IC3
12
B 744538
B
11
A
A
10
Q
Q
Q GND Q 9
C
0.1 mF
1k
100 mF
16V
470
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94
Figure 2
92
BATTERY VOLTAGE=12V.
EFFICIENCY (%)
90
88
86
84
82
80
0
20
40
60
80
100
120
140
180
160
200
LOAD (W)
The circuit in Figure 1 maintains reasonably tight regulation for a wide range of loads.
12V
0.1 mF
1N4007
1
3.3k
3
Q1
BC108
9.1V
0.1 mF
IC5
IR2151
33k
IC1
7805
12V
RED
240
5V
+
100 mF
50V
10 mF
25V
10 nF
6
Q3
IRFP250
5
H
56
2.2k
47 mF
63V
+
8.2V
33k
8.2V
16V
12V
1
0.1 mF
12V
1
5
6
8
IC6
744011B
FUSE 1, 20A
12V BATTERY
2 +
14
FUSE 2, 1A
REGULATED
OUTPUT
2 230V/50 Hz
1N4001
100 mF
50V
9
10
12
11
13
7
56
8.2V
Q4
IRFP250
33k
16V
2.2k
5W
+ 47 mF
63V
8.2V
12V
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design
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BATTERY VOLTAGE=13V.
BATTERY VOLTAGE=12.5V.
BATTERY VOLTAGE=12V.
BATTERY VOLTAGE=11.8V.
(NOMINAL OUTPUT VOLTAGE SET AT 200V.)
100
120
140
160
180
200
LOAD (W)
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EDNs Design Idea Grand Prize Winner is selected from among the 26 issue winners that readers have selected during
the year. We list the issue winners below and congratulate all on their creativity and ingenuity.
DESIGN IDEAS ISSUE WINNERS 1999
1/7/99
mC reprograms audio DAC via serial
interface, by Lukasz Sliwczynski
5/13/99
Simple fix adds door-chime repeater,
by Dennis Eichenberg
9/16/99
5V logic pulser is battery-powered,
by W Stephen Woodward
1/21/99
Light powers isolation amplifier,
by Stephen Woodward
5/27/1999
Charge indicator gauges lead-acid
batteries, by Fran Hoffart
9/30/99
SSB modulator covers HF band,
by Israel Schleicher
2/4/99
RS-232C circuit has galvanic isolation,
by Ioan Ciascai
6/10/1999
Precision reference bans precision
resistors, by Budge Ing
10/14/99
Dual supply suits portable systems,
by Budge Ing
2/18/99
Monostable makes low-cost F/V
converter, by Mark Brinegar
6/24/1999
Ultrasonic range finder uses few
components, by Daniel R Herrington
10/28/99
mC forms FM oscillator,
by Abel Raynus
3/4/99
Single-button lock provides high
security, by Maxwell Strange
7/8/1999
Simple scheme detects shorts,
by Luis Miguel Brugarolas
11/11/99
Ring your bell; light your light,
by Dennis Eichenberg
3/18/99
LED driver displays standing-wave
ratio, by Richard Panosh
7/22/1999
Simple technique speeds Microstrip
breadboarding, by Steve Hageman
11/24/99
RF transmitter uses AMI encoding,
by Paul Sofianos
4/1/99
Tiny IC debounces pushbutton
switch, by Len Sherman
8/5/1999
Single mC pin makes half-duplex
RS-232C, by Marin Ossman
12/9/99
Motor controller operates without
tachometer feedback, by Bruce Trump
4/15/99
NCO technique helps mC produce
clean analog signals, by Steve Ploss
8/19/1999
Circuit emulates mechanical
metronome, by Jim Kocsis
12/23/99
Simple tester checks Christmas-tree
lights, by William Dias
4/29/99
Simple circuit safely deep-discharges
NiCd battery, by Jim Hagerman
9/2/99
DDS device provides amplitude
modulation, by Mary McCarthy
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design
ideas
0.3 sec. These outputs connect to the select gate, IC5. The initial entry also sets
timer T1 to enable the decoded decade
counter, IC3. Each entry clocks IC3.
As IC3 steps through its counts, certain
of its output positions represent short
and connect to IC4s inputs; unconnected lines represent long positions. This
coding arrangement sets the combination. Short pulse positions change the
address of IC5 to select the short input
pulse; otherwise, IC5 selects the long
pulse input. The short and long inputs,
if present in the programmed sequence,
produce an output from IC5. IC6 counts
the outputs and produces an unlock
Figure 1
LONG
CODE
ENTER
PULSEWIDTH
SEPARATOR
DEBOUNCE
LONG/
SHORT
SELECT
SHORT
CLOCK
LONG/SHORT
ADDRESS
ENTRY
WINDOW, T1
(8 SEC)
CLOCK
R-1
DECODER
COUNTER
FIRST
TRIGGER
RESET
R-1
R-2
TRIGGER
LOCKOUT, T2
(10 SEC MINIMUM)
TRIGGER
TRIGGER
CODEENTRY
WINDOW
TIMER
(T1)
1
2
3
4
DECODED
COUNTER
RESET
R-2
UNLOCK
COMMAND
10
SEC
OR
GATE
5
6
7
8
COMBINATION
SET
(SEE TEXT)
RETRIGGERLOCKOUT
TIMER
(T2)
A handful of timers and counters configures a highly secure, single-button combination lock.
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design
ideas
1/4 CD4093
+
~600 mSEC
1M
R2
24k
14
3
1 mF
~7 mSEC
LOCK
COMMAND
You can generate a lock command with this additional circuit by rapidly entering four or more
short pulses.
IC1
CD4093
Figure 2
"LONG"
(>0.3 SEC)
+
A
240k
14
12
2
1 mF
NO
0.082 mF
5
6
CODEENTRY
BUTTON
22k
43Ok
100k
"SHORT"
10 (<0.3 SEC)
14
D
0
9
14
UNLOCK
COMMAND
8
15
100k
16
0
13
100k
IC6
CD4017
16
13
100k
IC5
CD4019
11
13
15
~7 mSEC
1 mF
+
LONG/SHORT
ADDRESS
LINES
10 mF +
20V
TANTALUM
POWER
(5 TO 15V)
20-mSEC CLOCK
DELAY
1000 pF
22k
TRIGGER
DUAL TIMER
(T1 AND T2)
COMBINATION SET
(LLSSLSSL SHOWN)
+
0
22k
3
12
10
11
10M
8.2M
13
16
2
1 mF
1 mF
220k
7
8
16
2
4
7
IC3
CD4017 10
1
5
15
R-1
6
9
8
13
IC2
CD4538 5
14
+
14
15
1M
2
3
9
10
11 B
3 A
4
4
5
6
7
8
14
12
22 mF
20V
TANTALUM
13
POWER-ON
RESET
IC4
CD4072
R-2
NOTE: ALL DIODES=1N4148.
You program your combination by hard-wiring the IC3-IC4 output-to-input connections, LLSSLSSL, where L and S are long and short inputs, respectively, in this example.
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IF
INPUT
+
COMP1
1
LEVEL
DETECTOR
ARM
FILTER
07
VCXO
VREF-1I
LOOP
FILTER
LOCKDETECTOR
OUTPUT
I DATA
DIODE
RECTIFIER
TO LOCK
INDICATOR
DIODE
RECTIFIER
LEVEL
DETECTOR
VREF-1Q
+
COMP3
1
VREF-2Q
(a)
+
COMP4
1
(b)
Figure 2
+
COMP2
1
Q DATA
907
ARM
FILTER
VREF-2I
DEMODULATION
LOCK DETECTION
ARM
FILTER
SQUARE
LIMITER
IF
INPUT
07
VCXO
LOOP
FILTER
SQUARE
907
LIMITER
ARM
FILTER
SQUARE
TO LOCK
INDICATOR
SQUARE
(c)
Various lock-detection schemes for Costas-loop systems suffer from problems. Level-detection (a) and a similar method (b) can give ambiguous results
under noisy conditions. A coherent method (c) gives unambiguous results but is complex.
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design
ideas
locked condition than in the locked condition. By detecting this differFROM LOCK
Figure 3
DETECTOR
ence in levels, you can determine
the locked condition. This method is not
SWEEP
SWITCH
GENERATOR
free of ambiguities under noisy conditions because the detected levels change
with levels of noise. Thus, reference-voltage settings for level comparison are critical. At some levels of noise, level comLOOP
FROM PHASE
TO VCXO
parison becomes almost impossible;
FILTER
DETECTOR
under such conditions, this method of
lock detection fails.
The coherent method illustrated in
Figure 2c gives ambiguity-free lock detection for modified Costas-loop sysTO LOCK
50-Hz SINE-WAVE
HIGHPASS
AMPLIFIER
RECTIFIER
INDICATION
tems. Unfortunately, this method is comGENERATOR
FILTER
COMPARplex, and the hardware realization is as
ATOR
V
REF
complex as the demodulation process itself.
Figure 3 presents a new method of An improved lock-detection scheme introduces a low-frequency, low-level modulation into the
lock detection with much less hardware loop. When the loop is in lock, this low-frequency signal at the output of the loop filter disappears.
complexity. You can adopt this level of
detection for any PLL system. The un- the loop filter, which is an active filter, mains connected to the loop filter even
derlying principle of this method is that and injecting a sweep signal of 2 Hz, during lock. The presence of this signal
when the PLL is in lock, it tracks and neu- which speeds lock acquisition. If you use at the input of the loop filter does not detralizes all of the low-frequency modu- a passive filter in place of the active fil- grade the demodulator performance belations within the loop. Therefore, if the ter, you can apply the signal at the input cause the level is low. You choose 50 Hz
system introduces a low-frequency, low- of VCXO after the loop filter, that is at the as the injected signal frequency because
level modulation, such as at the loop-fil- input of the amplifier after the passive 50 Hz is considerably higher than the
ter input, into the loop, then when the loop filter.
sweep-signal frequency and considerably
loop is locked, the low-frequency signal
The scheme taps the output of the loop lower than the loop bandwidth.
at the output of loop filter disappears. filter and filters out the sweep signal. The
The performance of this method is efThe presence or absence of the signal at scheme then amplifies the 50-Hz signal fective even under very noisy conditions,
the output of the filter provides unam- to compensate for attenuation in the such as when the inputs Eb/No (energybiguous lock detection.
loop filter and rectifies the signal to give per-bit-to-noise) figure is 3 dB. Previous
The circuit in Figure 3 implements a dc voltage to indicate its presence. methods give ambiguity-free results only
this method in a 375-MHz QPSK de- When the loop is in lock, the 50-Hz sig- at Eb/No levels of 7 or 8 dB. (DI #2545)
modulator with a loop bandwidth of 10 nal disappears, and the rectifier output is
To Vote For This Design,
kHz. This method involves injecting a zero. The lock-indication output also
Enter No. 365
low-level, 50-Hz sine wave at the input of cuts off the sweep. The 50-Hz signal re-
and feedthrough terminations. The technique applies to all commercial, industrial, and educational breadboard units
that require a quick-and-dirty implementation. The test pieces are useful for
low-cost laboratory experiments on passive circuits at reasonably high frequenwww.ednmag.com
design
ideas
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Figure 1
1k
0.1
mF
1k
10k
J1-7
10k
10k
10k
POWER
J1-8
ADM1021
J1-9
VDD
2N3904
D+
ALERT
J1-2
STBY
74HC05
J1-13
SCLK
SENSING
JUNCTION
SHIELD
D1
J1-3
SDATA
ALERT
ADD0
ADD1
J1-10
74HC05
SET TO
REQUIRED
ADDRESS
J1-19
J1-20
J1-21
J1-22
J1-23
J1-24
J1-25
J1-26
J1-27
J1-28
J1-29
J1-30
74HC05
GND
74HC05
10k
10k
Using a regular, general-purposes transistor and a thermal-diode-sensor IC, you can monitor remote temperature and display it on your PC.
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design
Edited by Bill Travis and Anne Watson Swager
ideas
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design
ideas
V1
VTL
VTH1VTL =
T1
(VOH1VIN )T1
.
R 3C1
VOUT
f=
100
T2 VOH1VIN
,
=
T1
VIN
T2
T1
=
T1 + T2
1
V
= 100 IN .
T2
V
OH
1+
T1
You can see that the duty cycle is directly proportional to VIN: 0% for
VIN50V and 100% for VIN5VOH. Moreover, the duty cycle is essentially independent of the component values, with
the constraint that R2..R1 to keep hysteresis small. An inverse relationship be-
25,000
100
R2
1M
Figure 2
90
20,000
80
9 TO 12V
R1
10k
VIN
V+
R4
10k
VOH
(5V)
Figure 1
70
VOUT
IC1A
TLC393
V1 _
60
15,000
DUTY CYCLE 50
(%)
40
10,000
FREQUENCY
(Hz)
30
NOTES:
DC (%).
F (Hz).
20
C1
1 nF
R3
1M
10
5000
0
0
VIN (V)
design
ideas
Figure 1
INTERRUPT
INTERRUPT
PIN
VCC
STOP
RESET
RUN
STOP
2INT
+
RST
8OC51
RST
4001
PIN
(a)
PORT
PIN
PIN
(b)
A simple NOR gate (a) allows interrupt-driven wake-up from power-down mode (b).
design
ideas
ANALOG 5V SUPPLY
assumption that the wiring resistances of
the three-wire RTD are equal.
Figure 1
Figure 1 shows a typical circuit
AVDD
DVDD
REFIN(+)
REFOUT
based on this assumption. The two current sources are assumed to be identical
REFIN(1)
2.5V
and to track each other closely over temREFERENCE
perature and supply-voltage changes.
200 mA
However, a finite level of mismatch exRL1
RTD1
ists. In applications in which accuracy is
paramount, it may be wise to use only
PROGRAMMABLEGAIN AMPLIFIER
one excitation-current source for the
AIN1(+)
RTD and thus avoid any potential mis+
INTERNAL
RTD
match between two sources. However,
AIN1(1)
CIRCUITRY
_
the single-current-source approach for
A=1 TO 128
exciting a three-wire RTD complicates
RL2
RTD2
the effort to reject the ohmic drops, because you can no longer eliminate the
200 mA
wiring drops as a common-mode signal.
Nevertheless, you can still eliminate
RL3
AD7711A
AGND
the wiring drops by using a two-channel
ADC and a little extra software compuDGND
VSS
tation. You take two conversions, and
software subtracts the error term stemming from the wiring resistance. In Figure 2 the wiring resistances are represented by lumped elements RL1, RL2, and Two current sources turn wiring drops into a common-mode signal.
RL3. Assume that the wiring resistance of
all three leads is equal (RL15
Figure 2
RL25RL35RL). In fact, it is necessary only that RL2 and RL3 be equal, beRL1
cause RL1 appears in both equations. The
REFIN(1)
circuit uses the RTD in an upside-down
fashion. Two FET switches, SWA and SWB,
REFIN(+)
direct the excitation current through the
RL2
400 mA
appropriate legs of the RTD. To avoid inRREF
RTD CURRENT
terruptions in the current flow, make-before-break switching is advisable. StartAIN1(+)
ing with both switches closed, SWA opens,
PROGRAMMABLEGAIN AMPLIFIER
and the AD7711A takes a measurement.
RTD
The measured voltage is 2I1RL, which
AIN1(1)
+
represents the out-and-back wiring drop.
_
MULTIPLEXER
Next, SWA closes, and SWB opens. The
A=1 TO 128
AIN2(+)
ADC takes a measurement on Channel 2.
The measured voltage is 2I1RL1VRTD. This
RL3
AIN2(1)
signal represents the out-and-back
wiring drop plus the desired signal. The
VRTD term is the first result subtracted
AD7711A
from the second. The onboard, 400-mA
current source of the AD7711A serves as
SWA
SWB
the excitation current in Figure 2. (DI
#2556)
design
ideas
ty. Whats more, the cookbook component-value formulas can yield unrealistic
values for the capacitors and resistors.
Butterworth filters, for example, offer
the flattest passband. They also provide
a fast initial falloff and reasonable overshoot. You can easily design such filters
using Table 1 with the following equations: R251/(2pfCC=X and R15XR2.
For a gained filter response, the use of a
fixed-gain op amp reduces cost and component count. It also reduces sensitivity,
because the internal, factory-trimmed,
precision gain-setting resistors provide
0.1% gain accuracy. To design a secondorder Butterworth lowpass or highpass
filter using a fixed-gain op amp, follow
these steps:
Figure 1
5
VCC
R1
VIN
R2
3 IN1
MAX4174
+
OUT 1
VOUT
RF
RG
VEE
2
(a)
Lowpass
X
*
2
0.5
0.404
0.343
0.268
0.222
0.191
0.15
0.125
0.107
0.084
0.076
0.07
0.057
0.049
0.038
0.032
0.031
0.026
0.02
0.017
0.017
0.014
0.011
0.009
0.009
Highpass
X
1.372
1.072
0.764
0.672
0.602
0.5
0.429
0.377
0.305
0.257
0.222
0.176
0.159
0.146
0.121
0.103
0.08
0.068
0.066
0.056
0.043
0.035
0.035
0.029
0.022
0.018
0.018
LOWPASS
R2
5
VCC
C
VIN
R1
MAX4174
+
OUT 1
RF
RG
VEE
2
(b)
HIGHPASS
VOUT
design
ideas
1000
10,000
100,000
FREQUENCY (Hz)
Using the circuit values in the text, the circuit in Figure 1a produces this Butterworth response.
ues of R1, R2, and C1 give a serial outputpulse train at a rate of 10 kHz/V according to FOUT5VIN/10(R11R2)C.
The converters output linearity of less
than 0.01% ensures a linear conversion of
the sensed voltage/current to frequency
throughout the current range.
Figure 1b shows the other part of the
circuit that attaches to the PCs LPT
printer port. This circuit couples the converters output pulses through an optocoupler. It also conditions and counts the
pulses using a 16-bit counter, IC4 and IC5,
whose output bits IC7 and IC8 buffer. The
circuit hooks the buffer outputs to the input port, STATUS port at 0x379h, of the
printer adapter. The circuit inhibits or allows the pulses to the counter by controlling the output bit D2 (DATA port at
0x378h) of the printer port to enable or
disable AND gate IC4. The PC reads the
counter output a nibble at a time by con-
trolling the address inputs of a two-tofour decoder (IC9) using D0 and D1 bits
of the DATA port. The decoder outputs
in turn control the buffer outputs.
A simple Turbo C program controls
the remote current measurement. (You
can download the program from EDNs
Web site, www.ednmag.com. Click on
Search Databases and then enter the
Software Center to download the file for
Design Idea #2550). The timer-tick interrupt, 0x1Ch, which occurs 18.2 times/
sec and whose only task is to keep track
of the time of day, generates the timebase.
The timer-tick interrupt executes the
TIMEBASE() routine to update the
TIMER variable. To make a measurement, the printer port first disables the
pulses to the counter by setting D2 of the
data port to logic 0 and clearing the
counter contents by setting D3 to logic 1
and resetting it to logic 0. To enable the
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design
ideas
15V
Figure 1
2N2222
IIN
0.1 mF
200k
1M
100k
5
MANGANIN
SHUNT
40k
0.1%
0.1 mF
IC1
INA101
7
2
8 10k
+
10 mF
5V
10
13
10
10k
5
IC2
AD537
470 ULN2003
1
11
C1
0.01 mF
330
12
IOUT
3
215V
POLYSTYRENE
R2
100
(a)
TO LPT1
16
IC3
14
R1
1k
0.1%
D0
2
13
D1
6
IC9
1 74LS155
5
15
4
14
5V
2
D2
5V
4
5
D3
1
2
4
IC7
14
74LS244 6
8
12
11
9
13
7
15
17
5
19
3
13
18
12
16
10
11
3
74LS14
470
9
7
6
5
10
3
2
4
13 IC5
CD4040
1
3
IC4
74LS08
FROM REMOTE
PART OF
CIRCUIT
IC10
74LS14
2
4N35
11
D25 CONNECTOR
PC PRINTER PORT
1
2
4
14
6
8
12 IC8
74LS244 11
9
13
7
15
17
5
19
3
18
16
(b)
12
14
15
1
3
4
2
IC6
CD4520
5
7
6
A low-temperature-coefficient manganin element senses the high current of the remote module, and IC2s voltage-to-frequency converter digitizes the
resulting amplified voltage (a). This result, in turn, attaches to the PCs LPT printer port through an optocoupler, counters, and buffers (b).
www.ednmag.com
design
ideas
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design
ideas
for a bit_clk is 4(k12) cycles long (Listing 1). Therefore, k5(NP/16)22. If you
choose P516, k then conveniently becomes N22. At FOSC58 MHz, these parameters reliably cover speeds of 2400 to
38,400 bps, or baud rate, which in the
Circuitcomputesfirstderivative
Richard Panosh, Vista, Bolingbrook, IL
he circuit in Figure 1 computes the
derivative of an input signal
Figure 1
as the integral of the input
signal minus the signal itself. The response of the circuit is
VOUT
R EQ C1s
R
=1 2 VIN
,
1 + R EQ C1s
R1
where REQ is the parallel equivalent resistance of R1 and R2 plus the resistance
of R3, or
R EQ =
R1R 2 + R1R 2 + R 2R 3
.
R1+ R 2
R2
R1
INPUT
IC1
C1
OUTPUT
+
R3
R1
R2
R1R 2
.
R1 + R 2
design
ideas
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design
ideas
5V
Figure 1
0.1 mF
1.5k
12V
F
Q1
Q3
T1
47
Q2
100
CF
CE
CD
CC
CB
CA
12V
Q4
100
R1
121k
499
499
47
10k
CA
R2
1k
CA
5
IC3
OPA137
4 _
2
CA
2M
3 +
1k
R
10
nF
SINGLESIDEBAND
IN
499
Q5
Q7
Q6
1k
100
T2
499
47
R3
47
16 2
4
2
IC2
74F157
8
1
SIDEBAND
SELECT
5
IC1A Q
74F74 Q 6
NOTES:
ALL RESISTORS ARE 121k, 61%.
CA=4.7 nF, CB=3.3 nF, CC=2 nF,
CD=1 nF, CE=560 pF, CF=470 pF.
ALL ARE CERAMIC, 2%, NPO.
Q1 THROUGH Q8=2N3904.
1k
5V
15
AUDIO
OUTPUT
1
mF
0.1
mF
1k
R4
Q8
100
1 mF
10k
12
11
9
IC1B
Q
74F74 Q 8
1, 4, 10, 13, 14
5V
fIN=43fC
CLOCK
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design
ideas
he prescaler in Figure 1 inexpensively extends the range of a frequency counter by dividing the input
signals frequency by a factor of 1000. The
guaranteed input-frequency range of the
input prescaler, IC1, is 250 MHz to 2.8
GHz, although typical values are 100
MHz to 3.5 GHz. The prototype operates
at frequencies well below 100 MHz, but
its fastest generator goes only to 1.7 GHz,
so you cannot confirm the upper range.
The input-voltage range is 400 to 1000
mV p-p from 250 to 500 MHz and 100
to 1000 mV p-p for higher than 500
MHz. IC1 serves as a divide-by-128
prescaler, whose output is a 1.6V p-p
square wave. The RC network level-shifts
the output of IC1 to ensure that the top of
the square wave is above the 2V input
threshold of IC5A. The output of IC5A is a
5V, CMOS-compatible square wave with
a frequency of 1/128 of the input frequency. Most frequency counters can handle
VIN
1 nF
P5
2
8
3 4 5
8 8 7
6
8
7 8
8 8
9 10 11 12
8 7 8 8
13 14 15 16
8 8 7 8
1 nF
IN
50
Pulse number 1
Divide by
8
VCC
SW1
OUT
IN
P5
NC
MC12079
SW2
IC1
6
5
P5
GND
2.32k
3
10 nF
2k
1k
CLR 1
CLK 2
2
M1
IC5A
74HCT02
VCC
16
15 RCO
14 QA
QB
13
4
74HC161
QC
C 5
12
IC2
D 6
11 QD
ENT
ENP
10
7
LOAD
GND
8
9
B
VOUT
8
10
M1
IC5C
74HCT02
Figure 1
P5
CLR
P5
1
16
VCC
15 RCO
2
QA
A 3
14
B
QB
13
4
74HC161
QC
C
5
12
IC4
QD
D 6
11
ENT
ENP
10
7
GND
8
9 LOAD
CLK
V
16 CC
15 RCO
QA
A3
14
QB
B4
13
74HC161
QC
C 5
12
IC3
D 6
11 QD
CLR
1
CLK 2
ENP 7
GND 8
10 ENT
9 LOAD
4
M1
IC5B
74HCT02
NOTE:
CIRCUIT INSIDE DASHED LINES IS
SURFACE-MOUNT WITH GROUND PLANE.
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design
ideas
ground plane, and the center pin connected to the Surfboard with the shortest
possible wire. The rest of the circuit is
noncritical. To avoid clutter, Figure 1
shows no bypass capacitors, but you
www.ednmag.com
design
ideas
50, 48, 40, 38, 30, and 28. You can download Listing 1 from EDNs Web site,
www.ednmag.com. Click on Search
Databases and then enter the Software
Center to download the file for Design
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design
ideas
Fax
Company
Address
Country
ZIP
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design
ideas
3.50
UPPER THRESHOLD
THRESHOLD
VOLTAGE
2.50
(V)
LOWER THRESHOLD
1.50
1
0.50
0
4.50
6.25
9.75
11.50
13.25
15
For the circuit in Figure 1, the thresholds vary with supply voltage as shown.
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design
ideas
(1)
(2)
Z21
Gn1k11
DATA_IN
Gn1k(D)=gn1k11Dn1k11+gn1k12
Dn1k12++g1D+g0,
(3)
(4)
Figure 2
(5)
Equation 5 shows that the transmitted frame is divisible by the generator polynomial. At the receiving
side it is divided by the same generator polynomial, and the quotient,
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design
ideas
Reference
1. Ross, N, A painless guide to CRC
error detection algorithms, ftp://ftp.
rocksoft.com/papers/crc_v3.txt.
www.ednmag.com
design
ideas
Figure 1
VCC
THERMOSTATIC
SENSOR
VID0
VID1
VID0 TO 4 AND
FAN-DIVISOR
REGISTERS
VID2
LOGIC INPUTS
VID3
SERIAL-BUS
ADDRESS
REGISTER
A0
SERIAL-BUS
ADDRESS
REGISTER
VID4
PULSE COUNTER
SCL
I2C INTERFACE
INT
FAN1
FAN-SPEED
COUNTER
FAN2
PS1
A1
SDA
VALUE AND
LIMIT
REGISTERS
12VIN
PS2
5VIN
3.3VIN
INPUT
ATTENUATORS
AND
ANALOG
MULTIPLEXER
VCCP1
PS3
VCCP2
2.5VIN
BANDGAP
TEMPERATURE
SENSOR
ILOAD
RSENSE
LIMIT
COMPARATORS
9-BIT ADC
ADM9240
ANALOG
OUTPUT REGISTER
AND 8-BIT DAC
AOUT
GROUND
R (FIXED)
THERMISTOR
SENSOR
You can configure a DAS to simultaneously measure multichannel voltages, temperature, resistance, current, and frequency.
www.ednmag.com
design
ideas
AREA(P1P2P3 ) =
x1
1
x2
2
x3
y1 1
y2 1 ,
y3 1
fashion. To determine whether ABC contains P, calculate the area of ABC using
Equation 1 and then define three new triangles, each having as its vertices point P
and two vertices of ABC.
This operation results in three unique
Figure 2
Figure 1
Figure 3
C
C
B
P
A
A
A
If P is within triangle ABC, the three new triangles will be within ABC, too.
If P is outside triangle ABC, the three new triangles will extend beyond ABCs borders.
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design
ideas
LOWPASS FILTER
100 nF
FULL-WAVE RECTIFIER
Figure 2
5 +
6
IC1B
2
1N4001
R5
2.7k
TL084
12V
3
10
+
1
2 IC1A
2
TL084
11
212V
x(t)
13
12
10k
10k
390
2.7k
y(t)
2
IC1C
+
RH
TL084
U/D
2
INC
1
CS
7
VCC
VCC
TL084
LM393
5.6k
RL
VSS
4
VCC
EMAX
P1
10k
IC3B 5
+
RW
E(t)
14
8
1N4001
U/D
3
2
IC1D
+
VCC
IC2
VCC
X9C103
INC
1
IC5A
7432
1
IC4A
VCC
5.6k
7486
8
1
LM393
IC3A 2
2
4
P2
10k
EMIN
AGC_CLK
VCC
PROGRAMMABLE-GAIN AMPLIFIER
CONTROL
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design
ideas
design
ideas
Figure 1
RFB
VREF
DAC
_
IC1A
+
BIPOLAR OUTPUT45VREF
R1A
R1B
R1F
R1D
R1E
_
IC1B
+
VREF
VOLTAGEOUTPUT
SECTION
UNIPOLAR
OUTPUT
0 TO VREF
R1C
R1H
R1G
_
IC1C
+
JP3
JP4
R2A
R2B
JP1
R2C
VSUPPLY
_
IC1D
+
VREF
JP2
R2D
Q1
CURRENTOUTPUT
SECTION
RX
0 TO 1 mA
OR
4 TO 20 mA
This circuit simultaneously provides unipolar and bipolar voltage outputs and two output-current ranges.
www.ednmag.com
design
ideas
Bridge-temperature measurement
allows software compensation
John Wynne, Analog Devices Inc, Limerick, Ireland
ridge transducers are notori- efficients in their manufacturing processously temperature-sensitive. When es. Another approach is to simply measthe temperature changes, almost ure the temperature of the bridge and
everything else varies with some param- then use a mC to compensate in software,
eters increasing and some decreasing. given certain basic properties, such as the
The TCS (temperature coefficient of bridge resistance at 258C and the TCR.
span) is generally negative for piezoelec- This approach is effective, but concerns
tric pressure sensors, and the TCR (tem- that the temperature you measure may
perature coefficient of resistance) is pos- not be the real temperature of the bridge
itive. In other words, as the temperature hamper it. For instance, placing the temrises, the sensitivity decreases, and the re- perature sensor relative to mechanical atsistance of the bridge increases. In gen- tachment of the strain gauge has a crucial
eral, the TCS and TCR are close to each bearing on the accuracy of the reading.
other. This fact has in the past motivated Its not unusual to see errors of 18C or
designers to add both active and passive more in such situations. The idea preexternal components to achieve some sented here (Figure 1), suggested in Refmeasure of temperature compensation. erence 1, is to determine the temperature
However, the calibration of such systems of the bridge by measuring the voltage
can be tedious; the resulting performance, problematic. Piezoelectric-bridge
manufacturers have tried to ease
5V
Figure 1
the problem by equalizing the co-
RREF
560
Bridge-temperature measurement
allows software compensation ................127
Timer automatically shuts off ..................128
Video amplifier provides
digital gain control ......................................130
VDD
REF IN (+)
VREF
AD589
Q1
AD820
+
IC1
REF IN (!)
AD7706
IN+
AIN2
OUT(+)
OUT(1)
AIN1
COMMON
www.ednmag.com
AIN3
IN1
PRESSURE
BRIDGE
ROFF
33
GND
You can provide software compensation for bridge-temperature coefficients through accurate temperature measurements.
August 17, 2000 | edn 127
design
ideas
products.analog.com/products/info.asp?
product=AD7706. (DI #2576)
Reference
1. Paillard, Bruno,Temperature compensating an integrated pressure sensor,
Sensors, January 1998, pg 36.
Is this the best Design Idea in this issue?
Vote at www.ednmag.com/ednmag/
infoaccess.asp, enter No. 440 in the
Circle Number field, and hit the Search
bar. Put a tick in the Select box and hit
Submit.
Time
10 sec
15 sec
20 sec
30 sec
45 sec
One minute
Two minutes
Three minutes
Five minutes
10 minutes
15 minutes
30 minutes
45 minutes
One hour
Two hours
Three hours
+
D1
1N4148
AGN2104N
1
2
5V
3
S1
+
C1
220 mF/
10V
C2
0.1 mF
PIC12C508
VDD
VSS
GP5
GP0
GP4
GP1
GP3
GP2
8
7
C
D
D2
1N4148
1
This timer consumes no power in the off state and has zero voltage drop in the on state.
mC derives power through D1. C1 discharges through D2 when you release the
button. After turning on the relay, the mC
reads the four inputs GP0 through GP3
to determine the delay time (Table 1).
Once the time is over, an inverted pulse
appears on GP5 and GP4 and turns off
the latching relay. Once the relay turns
off, the circuit consumes no power. You
can download the PIC12C508 assembly
program for the timer from EDNs Web
site, www.ednmag.com. Click on Search
design
ideas
Figure 1
GAIN A
GAIN B
GAIN C
GAIN D
33 mH
13
14
100 mF AT 6V
HCT04
12
0.1 mF
IN
3
IN1
1
IN0
2
0.1 mF
0.1 mF
6 MAX4258
+
7
IC1
2
4
0.1 mF
51.1*
150*
49.9*
3
IN1
1
IN0
2
5
+
100 mF AT 6V
6 MAX4258
+
7
IC2
2
3
IN1 8
1
IN0
2
4
150*
MAX4258
+ 6
IC3
5
2 4
150*
33 mH
49.9*
49.9*
C1
0.1 mF
0.1 mF
C2
0.1 mF
0.1 mF
NOTE:
*1% METAL FILM.
You can obtain eight distinct gain settings with this low-noise, high-bandwidth video amplifier.
www.ednmag.com
cies of interest dont extend much below 100 kHz. So, using 0.1-mF capacitors results in a roll-off of approximately 50 kHz. Larger values for these
capacitors would reduce this figure.
Omitting the capacitors for a dc response is not recommended, however, because the resulting amplification
of IC1s input offset would produce an
output offset in the order of volts at
high gain settings. You can generate
1
2
3
4
5
6
7
8
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
the gain-programming
word using any TTLcompatible, 8-bit parallel-I/O port, such as a
PCs parallel printer
port or an EIA-1284compatible port. The
HCT04 CMOS inverter
chip in the gain-control
pathway blocks any possible noise entry in the
gain-control lines.
The overall input-referred voltage noise is approximately 2 nV
per the square root of hertz, equivalent to the Johnson noise of a
250V resistor. Maximum output
level is 15 dBm (3.6V p-p) into
50V and twice that into high-impedance loads. The combination
of extreme gain and high-frequency response (gain-bandwidth
products approaching 200 GHz)
of this circuit mandates careful attention to issues of ground-plane
and power-supply-bypass integrity. In addition, you must make
every effort to minimize stray capacitance around the feedback-pin
(Pin 5) components of all gain
stages. (DI #2559)
V,
Gain (into 50V
in decibels)
316=24.1
332=30.1
364=36.1
3128=42.1
3256=48.2
3512=54.2
31024=60.2
32048=66.2
5V
HCT04
HCT04
4
HCT04
8
6
0.1 mF
0.1 mF
0.1 mF
3
IN1
1
IN0
2
MAX4258
6
7
IC4
5
2 4
+
3
IN1
1
IN0
2
150*
MAX4258
6
+
IC5
5
2
4
3
IN1
1
IN0
2
8
+
5
100*
IC6
2
MAX4258
6
7 39.2
J1
50V
VOUT
4
150*
49.9*
49.9*
C3
0.1 mF
49.9*
0.1 mF
C4
0.1 mF
49.9*
0.1 mF
C5
0.1 mF
0.1 mF
25
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design
ideas
Figure 1
VCC
FROM
PRIVATE
BRANCH
EXCHANGE
TO LOGIC
+
R2
10k
FROM
PRIVATE
BRANCH
EXCHANGE
D1
200V
R1
10k
2
VCC
C
6N138
VB
3 K
B
E
TO LOGIC
7
5
D2
39V
(a)
(b)
The ac-coupled circuit in (a) is useless in some PBX systems; the configuration in (b) takes over for PBX-generated dc ringing signals.
PULSE
IC9
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design
ideas
el of the circuit; a Verilog testbench verifies the circuits function. A pair of delay-logic elements is modeled with 20 de-
Figure 2
lay lines of 1 nsec each. The testbench instantiated this operation. A simulation
(Figure 2) used Cadence Verilog-XL. A
20-MHz clock serves as the input clock. The select signals in
Figure 2 for the increase-dutycycle delay-logic element, IC5,
and the decrease-duty-cycle delay-logic element, IC7, correspond to the number of 1-nsec
delay elements inserted into the
delay paths. Thus, a select value of 12 corresponds to a 12nsec delay. You can download
Listing 1 and the Verilog testbench from EDNs Web site,
www.ednmag.com. Click on
Search Databases and then
enter the Software Center to
download the file for Design
Idea #2554. (DI #2554)
Is this the best Design Idea in
this issue? Vote at www.edn
mag.com/ednmag/infoaccess.
asp, enter No. 444 in the Circle
Number field, and hit the
Search bar. Put a tick in the Select box and hit Submit.
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design
ideas
3VIN12VD
10 mF
VIN=5V
12
OUTPUT
VOLTAGE 9
(V)
VIN=3.3V
0
0.1
10
100
Finite output impedance causes a decline in voltage with increasing load current.
plies to other mCs, too.) The 74HC14 derives its supply voltage, VCCA, from the
stabilization circuit comprising the inexpensive shunt regulator, SR1. You can adjust VCCA by trimming R1. The test circuit
used VCCA54.096V. The PWM signals
now have a stable amplitude that varies
less than 0.1% when the mCs supply
varies from 4.5 to 5.5V. Resistors R3 to R5
limit the current flowing from the mC
through the 74HC14s input-protection
diodes when VCCA is too low. The values
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design
ideas
switched-capacitor circuit. You can configure the circuit using any switched-capacitor IC thats capable of inversion.
This example uses the LM2664, but you
can use larger ICs, such as the LM2661 or
LM2663, to obtain higher current. The
circuit in Figure 1 can simultaneously invert, double, and halve the input voltage
over an input range of 1.8 to 5.5V. The
combined current capability of the three
outputs equals the maximum load current of the IC in either of the standard
topologies: inverting or doubling (40 mA
for the LM2664 and 200 mA for the
LM2663).
The output resistance for any output is
equal to or less than the typical output resistance of the basic doubler or inverter.
This last statement holds true only if you
realize that the doubling output is actually 2VIN22VFD, where VFD is the forward
drop of the diodes used. The doubling
output simply uses two diodes to make a
discrete charge pump in conjunction
with the switch that connects CAP1 to
VIN during one cycle and to ground during the next cycle. The extra diode drops
may be a problem in some applications,
but they would be insignificant if you
connected a linear, low-dropout regulator to the doubled output. The halving
output uses the concept of an unregulatwww.ednmag.com
design
ideas
VOUT242VIN12VFD
C4
3.3 mF
C3
3.3 mF
L1
100 mH
CAP`
C1
3.3 mF
V`
VIN41.8 TO 5.5V
LM266
CAP1
GND
SD
VOUT141VIN
OUT
C2
3.3 mF
One switched-capacitor IC simultaneously inverts, doubles, and halves the input voltage.
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design
ideas
VOS1 + VOS2
V
1 IN
IL = R SENSE + R SENSE .
IDEAL OFFSET ERROR
(VA1VIN ) G A = Z LIL
(1)
1
VA = 1R SENSEIL ,
1 +
GB
VIN
(0 TO 61.2V)
1WVIN
R SENSE W + Z Ls
1VIN
for R SENSE W >> Z L W,
R SENSE
which demonstrates the load currents insensitivity to the load, ZL. (DI #2579)
(2)
The maximum variation in load current is 66 mA for a 200V current-sensing resistor, RSENSE. This variation yields
a maximum load voltage of 612V (3V
less than the supply voltages). The maximum current-offset error is 0.01
Figure 1
mA for VOS1 and VOS2 of 1 mV.
This amount of offset is normal for lower grade op amps. Note that you connect
IL =
15V
_
IC1
GA
VA
LOAD
ZL (0 TO 2 kV)
RSENSE=200V
IL
115V
VG
IC2
VOS2<1 mV
GB
DUAL OP AMP
Modification improves
VCAs Spice simulation ..............................148
VOS1
IL (0 TO 66 mA)
mC takes control
of comparator ..............................................158
A 66-mA current source has a 612V compliance range.
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ideas
1
+
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design
ideas
Figure 1
7
6
5
2
3
4
1
2
3
14
13
12
11
10
9
7
6
4
5
5V
LPT1
74HCT138
13
12
10
11
5
18
16
14
12
4
3
74HCT14
2
4
6
8
1
4
15
3
1
2
6 74HCT- 10
7 193 9
11
12 13
14 2
7
IC1
9
7
5
3
18
16
14
12
11
13
15
17
74HCT244
74HCT244
5 4
15
3
1
2
6 74HCT- 10
7 193 9
11
74HCT153 4
5
fIN/100
2
74HCT- 3
90
6
7
11
14
fIN/10
IC5
fIN
11
19
1
2
4
6
8
12
1
5V
12
2
74HCT- 3
90 6
1
7
14
IC2
IC6
12 13
5V
5
2
Q0 3
1
74HCT14
18
16
14
12
Q1 11
12
Q2 3
Q3 11
13
74HCT74
74HCT14
10
5 4
15
3
1
2
10
6
74HCT9
7
193
11
12 13
5V
3
IC3
9
7
5
3
11
13
15
17
74HCT244
D1
1
74HCT08
19
74HCT14
9 12
13
5V
2
4
6
8
fIN
1k
D2
4 15
3 5
1
2
6 74HCT- 10
7 193 9
11
12
IC4
11
74HCT14
By using BIOS INT1Ch, you can measure frequency, using few resources of the host PC.
www.ednmag.com
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ideas
(continued on pg 156)
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design
ideas
subsequent manipulations. The FREQREAD routine reads the counters output, a nibble at a time, starting with
Counter 1 (IC1, nib0), depending on the
last-read SNIBBLE, to Counter 4 (IC4,
nib3). The program manipulates the nibbles and displays the frequency in hertz.
At the end of a measurement cycle, the
routine sets SINTR and MINTR to zero
and clears the counters and flip-flops to
make them ready for another measurement cycle.You can use the design for frequencies of 1 Hz to 7 MHz. However, you
can extend the range to 25 MHz or
greater by increasing the counter capacity to 20 bits or more (for example, by us-
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design
ideas
transforms the signal level to a value acceptable for the mCs input. Usually, it is
a comparator. Often, this signal channel
is open or closed for some programmable time period. For this purpose, you can
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design
ideas
5V
300k
2
LM393
3 +
VIN
R1
200k
5V
4
mC
10k
8
VREF
VOUT
pA0
pA1
VIN
3
VREF
2
1
0
5V
VOUT
3
2
1
0
You can use a mC to control a comparator, thus avoiding the need for analog switches.
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design
ideas
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SHUNT
design
ideas
Figure 1
1
115V
15V
10
2
9
12
1 TO 10V
D7
200
S2
13
IC6B
74LS08 3
VIN1
D4
14
11
IC3
74LS171
15
14
10
13
0 TO 1V
IC5
ULN2003
15
SM2
STEPPER
MOTORS
IC1
AD570
14
D3
15
11
17
16
16
S1
MOVE
12V
13
D0
DR
14
11
15 1
3
IC2
74LS171
16
15
10
IC4
ULN2003
14
SM1
13
9
13
12V
10k
6
3
4
5
74LS14
IC6A
74LS08
100 pF
SELECT
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design
ideas
SC
MOVE
INPUT
t2
t1
t3
DR
OUTPUT
ADC
OUTPUT
OPEN
NOTES:
t1=40 mSEC (MINIMUM).
t2=2 mSEC (MINIMUM).
t3=1.5 mSEC.
VALID
CODE
OPEN
VALID
CODE
OPEN
VALID
CODE
OPEN
VALID
CODE
Timing waveforms show the MOVE inputs control of the ADC output.
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design
ideas
the necessary interrupt occurrences between writing new data for the stepper.
Is this the best Design Idea in this
issue? Vote at www.ednmag.com/edn
mag/vote.asp.
of temperatures than silicon-based sensors. In many cases, platinum RTDs sit far
from the measurement circuitry, which
adds a great deal of error into the meas-
Figure 1
5V
NULL-A
NULL-B
BIAS
VS
2.5V
5V
+
MATCHED
CURRENT
SOURCES
IC3
ADG709
RREF=1k
IC1
ADT70
2.5V
REF
S1A
S4A
SHUTDOWN
+
INST
AMP
2
RGA
RGB
GND
SENSE
AGND
2VS
SHUTDOWN
DGND
1k
VSS
GND
(TO mC)
1 OF 4
DECODER
A0
49.9k
VOUT=5 mV/8C
A1 EN
SHUTDOWN (TO mC)
A0
A1
SHDN
5V
2
VOUT (SENSE) 3
VIN
GND
IC2
ADR390/
ADR391
A1
A0
X
0
0
1
1
X
0
1
0
1
SHUTDOWN
1 VOUT (FORCE)
1 mF
0
1
1
1
1
ON-SWITCH
PAIR
NONE
1
2
3
4
1k
A general-purpose amplifier in IC1, Kelvin-connected voltage references, and platinum RTDs enable this circuit to accurately detect temperatures of
2200 to 14008C.
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design
ideas
ground for IC1 to overcome this inaccuracy. IC2 has good temperature stability
and low noise and can provide 5 mA of
drive current. IC2 also has a sense pin for
sensing the drop on the line and compensating for the drop. Thus, the circuit
provides stable and identical voltages at
the bottom of the platinum RTD and
RREF. The circuit also buffers this voltage
using the internal amplifier of IC1. A 1kV resistor in parallel with a 1-mF capacitor at the output of IC2 provides a
path for the current to flow to ground.
IC3 makes it possible for the mC to address the platinum RTD. The circuit in
Figure 1 can accommodate four platinum RTDs, but you can increase this
number by using other differential multiplexers. IC3s low on-resistance match
between channels of 0.4V does not introduce large errors into the system.
Another feature of this circuit is that it
allows a programmer to put the circuit
y using a pseudo-RETI instruction, the program in Listing 1 provides an 8051 mC with a three-lev-
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ideas
OUTPUT
At the hold instants of the circuit in Figure 1, the circuit produces the inverted derivative of the
input waveform.
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ideas
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1N5817
A2
1N5817
A1
5V
2
LM2904
3
VIN
VOUT
5V
A0
VOUT
(a)
(b)
VIN
VTH1 VTH2
A nonlinear attenuator in the feedback loop (a) results in a square-law characteristic (b).
Regulator IC forms
convenient overvoltage detector
Robert Bell, On Semiconductor, Phoenix, AZ
igure 1 shows a simple, standalone overvoltage detector. The intent of the circuit is to monitor a
voltage, VMONITOR, and set the output,
VOUT, high when the monitored voltage
exceeds a preset threshold. The mini-
Figure 1
1k
Q1
2N2907A
51
VOUT
VMONITOR
R1
TLV431
R2
D1
1N914
10k
NOTE: VTHRESHOLD=1.25(1+ R1 ).
2
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design
ideas
20
40
41
10
11
12
38
39
45
46
19
18
17
16
15
14
13
12
11
A4
F3
G3
E3
D3
C3
B3
A3
F2
IC2
B4
21
C4
22
DP5
D4
23
E4
24
G4 F4
25 26
only 6 bits, whereas the drivers can provide 8 bits. That fact means that two more
seven-segment output ports go unused.
You can take advantage of the unused
ports of IC2 and IC3 to solve the decimalbit problem. Connect DP1 (Pin 5 of IC1)
to Pin 25 of IC3, DP2 (Pin 9 of IC1) to Pin
23 of IC3, DP3 (Pin 13 of IC1) to Pin 21
of IC3, and DP4 (Pin 17 of IC1) to Pin 25
of IC2. Also, connect COL1 (Pin 33 of
IC1) to Pin 23 of IC2, and COL2 (Pin 42
of IC1) to Pin 24 of IC2. With the help of
some mC software, you can control the
LCD in a flexible fashion. Listing 1 shows
the AT89C51 assembly code for controlling the LCD. You can download Listing
1 from EDNs Web site, www.ednmag.
com. Click on Search Databases and
then enter the Software Center to download the file for Design Idea #2574.
B0
10
G2
E2
43
8
D2
44 COM
C2
B2
49
50
VCC
5
A2
BP
F1
G1 E1
7211
B1
B2
33
34
27
28
29
30
31
32
D0
D1
D2
D3
D4
D5 P2.6 P3.6
35 36
D1
37 38
39
40
48 47
VSS
Figure 1
DATA BUS
50 49
48
47 46
45 44
43 COL2
41 40
39
38
37 36
50 49
48
47 46
45
43
41 40
39
38
37
G1
F1
A1
B1
G2
F2
44
A2
B2
42
COL G3
F3
A3 B3
IC1
COM E1 D1
C1
C2
DP
E3
D3
C3
35
36 35
G4 F4
34 COL1 32
31 30
29
28 27
26
34
31 30
29
28
26
33 32
A4 B4
COL G5
F5 A5
B5 G6
27
F6
A6
YN06
DP
E2
D2
10
11
12
DP E4 D4
COM
4 DP1
DP2
10
11
12 DP3 14 15
13 14 15
C4
16
DP
E5
D5
C5
DP
E6
D6
C6 B6
17
18
19
20
21
22
23
24 25
16 DP4
18
19
20 DP5
22
23
24 25
The unused driver outputs take care of the LCDs need for decimal-bit inputs.
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20
A4
27
28
22
23
24
25
26
31
32
19
18
17
16
15
14
13
12
11
F3
G3
E3
D3
C3
B3
A3
F2
IC3
B4
21
DP3
C4
22
D4
23
DP2
E4
24
G4 F4
25 26
DP1
B0
18
19
10
G2
20 29
E2
8
D2
30 COM
7
C2
6
B2
BP
37
14
VCC
F1
G1
E1
GND OSC A1 B1 C1
D1
7211
B1
B2
CS2
34
27
28
29
30
31
32
D0
D1
D2
D3
D4
D5 P2.5 P3.6
VCC
5
A2
36
35
36
37 38
39 40
35 34
16 15
D5
D4
D3
D2
D1
D0
DIP1
11
10
11 PIN
TO mC AT89C51
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design
ideas
Figure 2
1k
RS
0.5
Q1
VIN
OUTPUT
R1
1k
1k
VREF
2.5V
220
LM431
VIN
2N3906
8
1
1 nF
1 mF
LM358
1 nF
1k
1k
2N3904
10k
7
D1
1N914
2N3904
2
LM358
4
2
3
S2
6
5
S1
VREF
IN
REQUIV
10k
R2
1k
LM3420
1
1.23V
+
2
31k
+
OUT
D2
1N914
R3
30.9k
10 nF
2
4.2V
60.5%
75k
4
COMP
10k
2
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(continued on pg 134)
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LISTING 1C PROGRAM FOR PRECISION REFERENCE GENERATOR (CONTINUED)
Multiplexer enables
pseudomultidrop RS-232 transmission
Dan Christman, Maxim Integrated Products, Sunnyvale, CA
S-232 communications with one
REMOTE
mC and more than one reDEVICES
CHANNEL SELECT
Figure 1
mote system can be probR
lematic, because most mCs contain only
T
one UART, which provides an interface
IC3
between synchronous and asynchronous
MAX3221
V+ A1 A0 EN
VDD
ports. The multiplexer in Figure 1, IC2,
NO1A
allows multiple channels (four, in this
NO2A
R
V+ MAX3221
case) to share a single UART. The dual
NO3A
T
IC1
IC4
COMA
T
NO4A
four-to-one multiplexer allows transUART
MAX3221
R
COMB
ceiver IC1 to form a network with the four
NO1B
remote transceivers IC3 to IC6. Table 1 deV1
R
NO2B
fines the channel-selection codes. SelectT
NO3B
ing Channel 1, for instance, enables IC1
IC5
MAX3221
NO4B
to communicate with IC3 without being
V1 GND
loaded by IC4 to IC6. Pulldown resistors
R
inside the remote transceivers force the
MAX399
IC2
T
outputs of unselected receivers to a
IC6
known state.
MAX3221
The circuits supply-voltage range (3
to 5.5V) makes it compatible with 3 and
5V logic. IC2 receives its power directly One UART and one multiplexer enable one RS-232 transceiver to communicate with four others.
from the V1 and V2 terminals of IC1,
whose 65.5V outputs come from an in- its power from IC1 ensures that RS-232 232 transmission levels out of specificaternal charge pump. The multiplexer signals pass directly through, regardless tion.
handles rail-to-rail signals, so obtaining of amplitude. Each transceivers charge
pump requires four small capaci- Is this the best Design Idea in this
TABLE 1CHANNEL SELECTION
tors (not shown), whose values issue? Vote at www.ednmag.com/edn
A1
A0
EN
Selected channel
depend on the VDD range but do mag/vote.asp.
X
X
0
All channels disconnected
not exceed 0.47 mF. Note that
0
0
1
Channel 1 (IC3)
pulling too much current from the
0
1
1
Channel 2 (IC4)
charge-pump terminals of IC1, V1
1
0
1
Channel 3 (IC5)
and V2, can cause these rails to
1
1
1
Channel 4 (IC6)
droop and may pull the ICs RS-
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ideas
Figure 1
AD830 1
OUTP
7
A=1
RF1
+
R1
1k
1k
VOCM
+
+
2
VIN
VCM
R2
1k
RF2
1k
A=1
7
OUTM
AD830 2
Figure 2
In the bottom traces, the differential outputs are 1808 out of phase with
each other.
Figure 3
design
ideas
10
10 nF
22k
10 nF
NOTES:
DIODES ARE 1N914, 1N4148, ETC.
TRANSISTORS ARE 2N2222, BC337,
MPSA06, ETC, DEPENDING ON RELAY.
22k
22k
22k
design
ideas
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ideas
12V
12V
Figure 2
MC33171P
2
2N3904
10k
COOLING FAN
5V
47k
5V
OVER/UNDERTEMPERATURE
DETECT
470
5V
2.2kV
2.2k
1
2
3
4
5V
5
6
7
8
2N3904
(TEMPERATUREZONE B)
FAN_OFF
SDA
MR
SCL
RST1
INT
GND
ADD
VCC
D2+/GPI
VMON
D22/THERM
RST2
D1+
FAN_SPD
D12
16
15
14
5V
13
PA1
PA3
PA0
PA4
4 MCLR
5
6
11
10
17
16
33 pF
OSC1
OSC2 15
PB0/INT
PB1
PB7
PB6
PB2
PB5
PB3
PB4
4 MHz
E
5V
GND PIC16C84
VCC
12
R/W RS
33 pF
5V
VCC 2
14
13
14
12
13
11
12
10
11 D
5
D7
D8
1634
LCD
5V
V0
D6
10
ADM1022
(TEMPERATUREZONE A)
SHIELDED
TWISTED-PAIR CABLE
18
PA2
2N3904
(TEMPERATUREZONE C)
D4
9
D3
8
D2
7
D1
GND
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where N is the total count during the integration period, T, and k is the
charge/count-conversion factor. However, if you periodically count the IRQ7 interruptssay, at 1-sec intervalsyou obtain the magnitude of the input current.
Though the circuit shown here is designed for positive input currents, you
can process bipolar input currents by using an absolute-value circuit before the
digital integrator. The Turbo C program
in Listing 1 controls the entire measurement. BIOS interrupt INT1Ch, which occurs 18.2 times/sec (normally used only
for time-of-day data), generates the 1-sec
timebase for the periodic counting of
the IRQ7 interrupts. At the start, the variables ITIMER, QTIMER, ICOUNT,
QCOUNT, ETIME, and TEMP are set to
zero. The INT1Ch signal causes execution of the TIMEBASE() routine to update the ITIMER and QTIMER variables,
and the IRQ7 interrupt causes execution
The output pulses of the digital integrator, after a division by 10 in IC4 and
buffering by IC5, interrupt the PC
through IRQ7 to a maximum rate of
1000 pulses/sec. Access to IRQ7 is via the
LPT printer port 10 (ACK) for testing
the design. However, you can also directly plug pin B21 into the PCs slot, as
in Figure 1. Each IRQ7 interrupt represents a fixed, 100-nC charge when
counted in totalizing mode over a period, T. The following equation gives the
total charge associated with the current
in period T:
5V
Figure 1
100 pF
**RF
10k
470
**10k
10k
15V
15V
IIN
2 _
IC1
6
OPA103
3
5
+
4
1
**10k
3 +
IC2
OP77
6
8
10k
5
10 mF
5
14
14
1 12
IC4 (410)
74LS90
3
11 2
7
IC5
74LS244
18
B21
20k
5k
20k
100k
13
IC3
AD537
7
2 _
PC
SLOT
10
11
12
820
B31
115V
100k
115V
*0.01 mF
500
*POLYSTYRENE
**0.1% METAL FILM
You can use a PCs interrupts to measure low currents and their associated charges.
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design
ideas
3
V1
V1
0.2
2
IP
V1 (V)
IP (mA)
V1 (V)
1
0.1
1
0
0
2
I (A)
0
0
I (A)
Figure 4
design
ideas
100k
100k
100k
100k
5V
1k
100k
MC68HC705KJ1
MC68HC705KJ1
MODE 1
PA0
MODE 1
PA1
MODE 2
PA2
PA2
MODE 3
PA3
PA3
MODE 4
PA0
SWITCH
IRQ
MODE 2
PA1
SW1
MODE 3
MODE 4
Single-sideband demodulator
covers the HF band ....................................170
Voltage reference improves JFET ............172
Wideband filter uses
image parameters ......................................174
(a)
(b)
As an alternative to a rotary switch (a), you can use a pushbutton switch (b) to cycle through four
modes of a mC-controlled process. Four LEDs indicate the selected mode.
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design
ideas
Figure 1
WENQ
D
C
WRITE_CNTR
WEN
WENQ
FF
WA0
WA1
G[1:0]
CE
WA[1:0]
VCC
CLR
AND2B1
D RAM16X1D
C
RA0
CG2RE
RA1
READ_CNTR
C
REN
RENQ
EF
WE
RA[1:0]
WCLK
A0
SPO
A1
A2
A3
DPO
DPRA0
DPRA1
DPRA2
G[1:0]
VCC
CE
DPRA3
CLR
AND2B1
CG2RE
COMP2
RA0
RA1
UP
DWN
Q0
Q1
Q2
Q3
OBUF4
FF0
FF1
FF2
FF3
OPAD4
WA0
O3
WA1
A0
A1
EQ
B1
O2
O1
FF
WEN
AND2
FDCE
O0
AND2B1
FFQ
D
NOTES:
RENQ: READ ENABLE QUALIFED WITH FIFO NOT EMPTY.
WENQ: WRITE ENABLE QUALIFED WITH FIFO NOT FULL.
CE
REN
P_EQ
B0
OR2
C
EF
AND2B1
HF
INV
CLR
GND
www.ednmag.com
design
ideas
13
www.ednmag.com
design
ideas
1031025
=pH
=pH
=pH
=pH
831025
12
9.29
6.71
3.06
631025
IDS (A)
431025
231025
0.5
1.5
VGS (V)
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design
ideas
Figure 2
measured values of temperature are beyond the temperature limits, then the
ADM1023 signals an Alert. The ALERT
is active-low; an LED tied to the pin lights
whenever an Alert signal arises. The USB
port supplies power to the circuit. The
port can supply as much as 500 mA at 5V.
Because both chips in Figure 2 operate at
3.3V, the circuit uses a 78033 regulator to
generate the required 3.3V. The USB
Master, which in this case is the application running on the PC, maintains control of the circuit. The master initiates all
USB communications. The temperaturemeasurement circuit is the slave. It responds only when the master requests it
to do so. When the master requests data
(via the PC application), the request travels down the USB cable to the mC. This
3.3V
3.3V
USB
J3
SH SH GND D+ D1 VCC
6 5
4
3 2
1
2.2k
3.3V
5V
2.2k
4.7k
ADM1023
1
0.1 mF
2
3
C
4
B
Q3904
5
6
7
8
NC
NC
VDD
STBY
D+
SCLK
D1
NC
NC
SDATA
ADD1 ALERT
GND
ADD0
GND
NC
16
3.3V
14
24LC00-SN
13
12
11
10
LED
470
GREEN
SDA GND 4
0.1 mF
3.3V
44 43 42 41 40 39 38 37 36 35 34
Y1
5V
12 MHz
+
8
SCL VCC
3.3V
3
OUT IN
COM
0.1 2
0.1
mF
mF
0.1 mF
10
mF
3.3V
RED
ALERT
78033
470
24
15
3.3V
POWER
LED
24
1.5k
10
mF
3.3V
AN2131SC
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0.1 mF 12 13 14 15 16 17 18 19 20 21 22
1M
33 pF
1
2
3
4
5
6
7
8
9
10
11
33 pF
33
32
31
30
29
28
27
26
25
24
23
0.1 mF
3.3V
0.1 mF
1 mF
www.ednmag.com
design
ideas
Reference
1. Zavrell, Robert, J, New low-power
single sideband circuit, Philips Semiconductor, AN1981.
5V
Figure 1
12V
0.1 mF
1.5k
Q1
Q2
T1
Q3
47
R
CF
499
CE
CD
CC
CA
CB
10k
R
100
CA
Q4
100
10k
499
R
1k
0.01 mF
3 +
499
Q6
T2
5
1
OPA137
4
2
2
Q5
SSB IN
CA
47
1k
1 mF
12V
CF
CE
F
CD
E
CC
D
CB
C
AUDIO
OUT
CA
B
2M
Q7
1k
499
47
100
100
Q8
0.1 mF
47
1k
1k
NOTES:
ALL RESISTORS ARE 121 kV, 1% UNLESS OTHERWISE SPECIFIED.
CA=4.7 nF, CB=3.3 nF, CC=2 nF, CD=1 nF, CE=560 pF, CF=470 pF;
ALL ARE CERAMIC 2% NPO.
Q1 TO Q8=2N3904.
5V
15
8
16 2
3 4
2 D
IC2
74LS157
1 7 5
IC1A
74F74
Q
Q
5
6
12
11
Q 9
IC1B
Q
7
1,4,10,13,14
SIDEBAND
SELECT
FIN=43FCARRIER
5V
www.ednmag.com
design
ideas
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design
ideas
63.0
66.0
6380
6980
MHz. Impedance levels are 50V. A maleto-male BNC adapter connects the two
separate filter units. At higher frequencies, total integration of the two filters in
a single enclosure would be desirable. Use
of surface-mount components might
also be appropriate.
Table 1 shows the measured amplitude
responses of the highpass and lowpass
sections. Table 2 summarizes the overall
www.ednmag.com
design
ideas
References
1. Kurzrok, Richard M,Low cost lowpass filter design using image parameters, Applied Microwave & Wireless, pg
72, February 1999, plus correction pg 12,
May 1999.
2. Kurzrok, Richard M, Filter design
uses image parameters, EDN, May 25,
2000, pg 111, May 25, 2000.
3. Kurzrok, Richard M, Update the
design of image-parameter filters, Microwaves & RF, pg 119, May 2000.
C3
470 pF
PLUS 30 pF
C2
680 pF
C5
680 pF
C1
680 pF
L1
5 mH
L2
1.25 mH
L4 OUTPUT
5 mH
L5
0.40 mH
C6
470 pF
PLUS 8 pF
L6
1.59 mH
C7
470 pF
PLUS 8 pF
L7
1.59 mH
C9
C8
470 pF
560 pF
PLUS 75 pF PLUS 8 pF
L8
0.40 mH
OUTPUT
C10
470 pF
PLUS 8 pF
LOWPASS FILTER
NOTES:
C1, C2, C4, C5=POLYPROPYLENE.
C3: 470 pF=POLYPROPYLENE, AND 30 pF=CM-15 DIPPED MICA.
L1, L4=MICRO METALS T37-2 32T-#26.
L2, L3=MICRO METALS T37-2 14T-#26.
C6, C7, C9, C10: 470 pF=POLYPROPYLENE, AND 8 pF=CERAMIC.
C8: 470 pF=POLYPROPYLENE, AND 75 pF=CM-15 DIPPED MICA.
L5, L8=MICRO METALS T25-6 10T-#30.
L6, L7=MICRO METALS T25-6 23T-#30.
ADAPTER=BNC M-M (U6-491A/U, COMMERCIAL).
I/O CONNECTORS=BNC FEMALE.
ENCLOSURE=ALUMINUM BOX (HAMMOND 1590A/BND CU-123).
PC BOARD=VECTOR BOARD 169P44C1, CUT BY HAND.
STANDOFFS=MALE, FEMALE (AMATOM 9794-SS-0440).
A low-cost wideband filter results from cascading a highpass and a lowpass filter using imageparameter designs.
0.1
L3
1.25 mH
HIGHPASS FILTER
C4
680 pF
0.1
0.1
0.2
0.55
1
5
23.5
www.ednmag.com
design
ideas
6V
6V
10
13
IC1C
11
1.35V
1k
1k
6
1.3V
1k
8
6V
6V
6V
10
2
IC2C
5k
1.55V
1k
11
1k
11
13
1.5V
1k
1k
12
2
IC2D
5k
6V
IC2B
7
IC1D
9
14
13
5k
1.45V
1k
6
6V
12
16
5k
6V
1k
15
5k
6V
14
10
+
NOTE:
IC1, IC2=LM339.
design
ideas
chronic faults. The circuit full-wave-rectifies the output from the Lem current
transducer and applies the result or with
a variable delay to a window comparator.
The reference steps are 600 mV/1A at Pin
7 as a high level. Signals greater than the
H pin of the CA3098 set a flip-flop in the
CA3098, which removes drive to the solid-state relay. Forcing Pin 1 of the
CA3098 from 21V to 1V resets the flipflop and restores load power. An offset
current through the 15-kV, 1% resistor
Figure 1
103301,
1%
412,
1%
1k
15V
200,
1%
15V
16.8V
115V
6.8V
15k,
1%
1
390k
LOAD
0 TO 10A
115V
5.62k,
1%
2N2222A
0.1
FAST
NEUTRAL
10k
10k
SLOW
2
10
IN914
270
CLOCKWISE 10k
LOG TAPER
NE5532
10k
23
470/50V
L
3
SOLID-STATE
RELAY
LED
1
+
LF411CN
0.22
140V
12A
16.8V
150k
68k
CA3098
4
1
10k
78L15
10k
10
IN914
6.34k,
1%
3.65k,
1%
1 nF
180k
15V
1k
12A
115V
LINE
0.1
115V AC
32 VCT
6 VA
0.1
1
79L15
RESET
115V
15V
PIN 1
LF411CN
10k
PIN 5
LF411CN
VOS
ADJUST
NEUTRAL
LINE
An electronic fuse combines the properties of a current transducer and a solid-state relay.
www.ednmag.com
design
ideas
Amplitude-stable oscillator
has low distortion, low cost
Moshe Gerstenhaber, Chau Tran, and Mark Murphy, Analog Devices Inc, Wilmington, MA
he multivibrator is a common cirVOUT
V+
cuit that consists of an ampliFigure 1
T
fier with both positive and
negative feedback (Figure 1a). When the
V2
output is positive, the positive input ter1
VIN2
minal equals /2 V1, and the voltage at the
V+
negative input terminal changes toward
2
T
V1. When this voltage exceeds 1/2 V1, the
2
output voltage rapidly changes to V2.
The positive input terminal becomes
+
1
VIN+
/2V2, and the negative input terminal
V+
changes toward V2. When the voltage at
2
T
the negative input terminal is less than
V2
1
/2V2, the process repeats (Figure 1b).
2
(a)
(b)
For the multivibrator to work, the
bandwidth of the amplifier must be 10
times higher than the time constant of The common multivibrator has positive and negative feedback (a). When VOUT is positive, VIN2
the passive network, and consideration of changes toward V+. When VIN2 exceeds V+/2, VOUT changes to V2 (b).
the high slew rate helps define the amplifier. The output is a square wave.
To meet the conditions necessary to
Figure 2b is a performance photo of
The circuit in Figure 2a is a sinusoidal sustain oscillationloop gain equal to the oscillator running at 4 MHz and 5V
oscillator. External compensation at Pin unity and phase equal to zerochoose p-p. For better frequency stability, you
5 forces the unity-gain bandwidth of the (1/gm)3C251/(100pf) and R13C15 can replace C2 with a crystal of the desired frequency and low shunt capaciamplifier to be the same as the passive- 1/(2pf).
The inverse transconductance, 1/gm, of tance.
network bandwidth.
Loop-gain analysis results in the fol- the input stage, re, is equal to 52V. The
design assures amplitude stability belowing transfer function:
cause re always increases with an ampliVOUT
(112 fR1C1j)
tude increase, which reduces the loop Is this the best Design Idea in this
=1
.
1
VIN
gain. The ratio of the R2/R3 divider net- issue? Vote at www.ednmag.com/edn
100 f g C2 j(1 + 2 fR1C1j)
m
mag/vote.asp.
work sets the amplitude.
R1
Figure 2
15V
0.1 mF
C1
2 _
7
6
AD829
3
+
4
0.1 mF
VOUT
R2
5k
R3
0.1k
C2
115V
(a)
(b)
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design
ideas
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design
ideas
Figure 4
6.6V
1-MHz CARRIER
WITH 100% AMPLITUDE
MODULATION AT 5 kHz
20k
120k
OUTPUT
1 nF
1 nF
2N3904
NOTES:
BASE-DRIVE CURRENT IS 300 mA, EMITTER REVERSE CURRENT
IS APPROXIMATELY 75 mA.
2N3904 FORWARD BETA IS GREATER THAN 100;
REVERSE BETA IS APPROXIMATELY 0.25.
EMITTER-BASE REVERSE-BREAKDOWN VOLTAGE IS GREATER THAN 6V.
AC-DRIVE VOLTAGE IS LESS THAN 6.6V P-P.
Figure 5
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design
ideas
Data-acquisition circuit
measures almost everything
Matt Smith, Analog Devices, Limerick, Ireland
sing a product developed for PCmotherboard environmental monitoring, you can configure a lowcost, general-purpose DAS (dataacquisition system) (Figure 1). The DAS
can directly monitor multiple voltage
channels as well as temperature and frequency. It can also directly monitor digital sensors. Using only a few additional
components, the system can accommodate other sensor and transducer elements. The flexibility exists to expand the
scheme to cover additional input channels if necessary. For voltage sensing, the
ADM9240 contains a multichannel ADC
that can directly monitor as many as six
input channels. The original intent of the
VCC
THERMOSTATIC
SENSOR
A0
VID0
Figure 1
VID1
VID 0 TO 4
AND
FAN-DIVISOR
REGISTERS
VID2
LOGIC INPUTS
VID3
SERIAL-BUS
ADDRESS
REGISTER
A1
SERIAL-BUS
INTERFACE
SDA
I2C
SCL
I2C INTE
VID4
PULSE COUNTER
VALUE AND
LIMIT
REGISTERS
FAN1
FAN-SPEED
COUNTER
FAN2
INT
PS1
12VIN
PS2
LIMIT
COMPARATORS
5VIN
3.3VIN
INPUT
ATTENUATORS
AND
ANALOG
MULTIPLEXER
VCCP1
PS3
VCCP2
2.5VIN
ILOAD
RSENSE
BANDGAP
TEMPERATURE
SENSOR
9-BIT ADC
ANALOG
OUTPUT REGISTER
AND 8-BIT DAC
AOUT
ADM9240
GND
RFIXED
THERMISTOR
SENSOR
www.ednmag.com
design
ideas
5V
Figure 2
3
VIN
5V
+ IC
7
1
2 LT1097
_
4
D1
6
5V
15V
SERIAL
BUS
CONTROL
AND
MEMORY
18
19
DCP1
DCP2
VOUT
_
IC2
LT1097
+
X9258 15V
You can program the gain of this full-wave rectifier from unity to 255.
D2
design
ideas
VCC
Figure 2
Figure 1
RBO (INT)
IOUT
2M
RC0
24V AC
MAC3040
MOC3040
100
PIC16C7X
PIC16C7X
100 nF
24V AC
design
ideas
www.ednmag.com
design
ideas
IN
R1
5.1k
BATTERY
Q3
2N3906
GND
R4
10k
S1
mC
VCC
DC/DC
CONVERTER
OUT
R3
10k
Q4
2N3904
R5
10k
C1
0.1 mF
R2
I/0
Q2
10k
2N3904
design
ideas
ic one and stops. Q2 turns off Q4, resetting the latch to its initial off state. R4 lowers the equivalent input impedance of Q3.
This function improves EMI and ESD
noise immunity and prevents the circuit
from turning itself on in the presence of
strong electromagnetic fields. Capacitor
C1 in combination with R5 protects Q4
and Q2 from direct ESD into the pushbutton. Some portable devices use undervoltage-lockout circuitry. This circuitry usually uses a voltage comparator
with a built-in voltage reference. If the
battery voltage drops below the threshold, the output of the comparator (usually an open-drain type) switches low. If
your portable system uses this type of circuitry, you can connect the open-drain
output of the comparator in parallel with
Q2, thus preventing the latch from turning on if the battery voltage is too low.
Figure 1
T1
D1
VBUS
R1
Q2
OA
FROM
PULSE-WIDTH
MODULATOR
0B
Q1
D2
R2
LOAD
You can use this low-cost circuit to drive high-side FETs or IGBTs.
R1
Figure 2
D1
VBUS
Q3
T1
Q1
OA
FROM
PULSE-WIDTH
MODULATOR
0B
D3
R2
D2
Q4
Q2
D4
LOAD
Two FETs in parallel provide more power than the circuit in Figure 1.
design
ideas
www.ednmag.com
design
ideas
Figure 1
VDD (V)
VDD
32.768-kHz OUTPUT
VDD
1 32K
OUT
2
3
4
SCL
OSCIN
OSCOUT
SDA
INTR
VSS
CURRENT (mA)
1.5
0.9
1.1
2.5
1.3
1.6
3.5
2.1
2.6
4.5
3.2
32.768 kHz
RS5C372B
3.9
5.5
4.7
5.6
This ultra-low-power oscillator uses only the oscillator portion of a real-time-clock chip.
design
ideas
Frequency (kHz)
50
20
10
5
2
1
0.5
0.2
0.15
0.1
TEST PORT
Frequency (kHz)
100
50
20
10
5
1
0.1
0.01
Figure 2
RETURN-LOSS BRIDGE
R1
T1
TO METER
FROM
GENERATOR
R2
R3
Frequency (kHz)
1000
500
200
50
20
10
5
2
1
0.5
Directivity (dB)
22
27
33.5
38
41.5
44.5
>46
>46
>46
>46
(Reference 2). The main program monitors the main-program flag, frqflg, until
the flag is set. Then, the main program
sends the counted frequency to the PCs
port using mode 1. First, it sends the special character L to recognize the following 3 bytes as valid data. Then it sends
the value of register R2, which is the most
significant byte of the counter value. This
value increments every time the counter
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design
ideas
Figure 1
RS-232
CONNECTOR
VCC
5V
1489
RxD
2
14
DEVICE 2
SERIAL OUT
10 mF
10k
VCC
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
RESET
33 pF
4
FREQUENCY
IN
12 MHz
21
9
22
10
23
11
24
12
5
8
33 pF
89C2051
12V
A
3
14
2
1488
7
25
13
3.4
TxD 3.1
3
10
212V
20
VCC
5V
References
1. Data Sheet for 89C2051, www.
atmel.com.
2. Ayala, Kenneth J, 8051 Microcontroller: Architecture, Programming and
Applications (ISBN 0-314-77278-2),
West Publishing Co, St Paul, MN.
Is this the best Design Idea in this issue? Vote at www.ednmag.com/edn
mag/vote.asp.
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design
ideas
offset in its accumulator to load the accumulator with a byte value. This solution to bit flipping is dynamically more
efficient than rotating a byte location
through carry bits or other possible solutions. However, its not the most statically efficient solution, because it requires
256 bytes of ROM for the look-up table.
You can download Listing 1 and the
look-up table from EDNs Web site,
www.ednmag.com. Click on Search
Databases and then enter the Software
Center to download the file for Design
Idea #2621.
Is this the best Design Idea in this
issue? Vote at www.ednmag.com/edn
mag/vote.asp.
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design
ideas
www.ednmag.com
1N4148
LINE IN USE
D3
RED LED
R3
560
47k
NiCd
ACCUMULATOR
+ 3.6V
300 mAh
+
+
D5
BZV55C4V3
Q2
Q2N2222A
+ C
1
1 mF
Q1
Q2N2222A
47k
R2
330
LINE IS FREE
D4
GREEN LED
SPEECH MODULATION
P200 mV
50
<15
LINE IS FREE
(b)
PHONE IS RINGING
PHONE IS IN USE
LINE IS FREE
D4 lights to indicate that the phone line is free, and D3 lights to indicate the line is in use (a),
depending on the three possible phone-line voltage states (b).
December 7, 2000 | edn 187
design
ideas
Figure 1
22 pF
11.0592 MHz
22 pF
0.22 mF
VCC
TXD 13
11
5
4
10k
3
4
DTR 1
1489
3
2
0.22 mF
XTL0
RESL
PB3 15
PD5
PB0 12
PD3
10
20
GND
F0=20 Hz
FSK MARK
FSK SPACE
CAS DT
RING
NO OUTPUT
20 Hz OUT
10 mF
TO POWER
AMP
V0=4VPP
PD1
VCC
+
FUNCTION
12k
5
1489
TLV2472
10k
DB9S
8
6.8k
1500 pF
RTS 10
75k
VCC
36k
VCC
XTL1
75k
IC1
AT9OS1200
1489
VCC
1C1
PIN 9
1C1
PIN 7
1C1
PIN 3
1
0
0
1
1
1
1
1
0
1
0
0
1
1
1
75k
38k
1500 pF
75k
8
7
4 TLV2472
6.8k
600 TO 600
TIP
10 mF 680
RING
V0=1.5VPP
12k
F0=2900 Hz
Based on RS-232 inputs from a PC, pin 12 of IC1 produces a PWM output proportional to FSK 1200-baud serial data or a dual-tone CAS signal. The output
at pin 15 is a 20-Hz-ring signal. Subsequent lowpass filtering produces sine-wave outputs.
www.ednmag.com
design
ideas
INTERNAL
VREF (4.8V)
+
1
6k
2
FB
3
30.25
_
9
+
CS
RESET
design
ideas
330 mH
MBRA140LT3
4.7 mH
Figure 2
470 mF
NCP1200
+ 4.7
mF
400V
+ 4.7
mF
400V
UNIVERSAL
INPUT
HV
2
3
4
10 mF
10V
6.5V AT
600 mA
+
GROUND
MTD1N60E
FB
CS1 VCC
GND DV
6
5
470
10
100
nF
(a)
10 mF
16V
27
SFH6156-2
68
47
MMSZ5V1
2N3904
68
22 nF
VOUT
(5V/DIV)
500 mSEC/DIV
OPTOCOUPLER
R3
100k
R2
820k
3
NCP1200
4
MBT
3946D
R1
100k
C1
0.22 mF
(a)
VOUT
(5V/DIV)
(b)
22
In this battery-charger circuit, the primary controllers operate without any auxiliary winding (a). Output-voltage runaway can damage the output capacitors if
the condition lasts too long (b).
(b)
Figure 3
100
100 mSEC/DIV
design
ideas
IN
GND
TO ALL 5V
5V
0.1 mF
78L05
+
1 mF
TANTALUM
5V
MCLR
1 mF
MAX231
SERIAL (RS-232)
INTERFACE
PIC18C252
5V
MXO45HS
OSCILLATOR
GND
40 MHz
1 mF
TANTALUM
GND
OSC1
5V
Figure 1
RC0
C+
V+
C1
5V
V1
GND
T2OUT
GND
R2IN
R1IN
RC7
R2OUT
R1OUT
T2IN
RED
RC1
RC6
YELLOW
RC2
RC5
BLACK
RC3
RC4
1 mF
TANTALUM
+
GREEN
5
2
3
DB-9S
The external wiring is simple because the Schmitt triggers, memory, and UART are all within the
mC.
design
ideas
mCs (Listing 1) overcomes this difficulty by producing a scope display that you
can read at a glance. The routine encodes
zero as a short pulse and one as a long
pulse. Using an open-drain I/O pin with
a large-value pullup resistor results in fast
falling and slow rising edges, which is due
to the RC time constant of the pullup resistor and the capacitance of the pin and
scope probe (Figure 1). Consequently,
zeros show up as short spikes in the display, and ones appear as medium spikes.
The separation between consecutive
bytes appears as a tall spike or pulse (Figure 2). Each byte starts with a clean
falling edge, which serves as a convenient
trigger signal for the scope. A midrange
PIC running at 4 MHz using a 100-kV
pullup resistor produces the plot in Figure 2. The resistor value is not critical. To
use another clock rate, you can scale the
resistor approximately as the inverse of
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0
2
1
A
HEX:
the clock rate. For example, at 8 MHz, a
0000 0010
BINARY: 0 0 0 0 0 0 1 0
pullup resistor of 47 kV produces
Figure 2
equivalent results.
The scope plot depicts a 16-bit value
of 00000010 for the first byte and
00011010 for the second byte. Each invocation of the subroutine in Listing 1
displays the most-significant bit of 1 byte
first. By taking care to invoke the subroutine on the most-significant byte of a
2V/DIV
multibyte value first, the scope display
naturally reads from left to right. Hence,
the depicted value is 021A hex. By slowing the timebase of the scope, you can
display a 32-bit value. The resolution of
the scope is the only limitation on the
amount of data the scope can display.
Because the subroutine preserves all
registers and flags, except for the gener20 mSEC/DIV
al-purpose register for the subroutine itself, you can safely insert a call to the
Inserting call Debug instructions into the code makes the 16-bit result visible. Zeros appear as
subroutine at any point in your code to
short spikes, ones appear as medium spikes, and a tall spike indicates separation between consecuobtain visibility into the value of the W
tive bytes.
register. The limitation on the W register is not a severe restriction because in
the PIC architecture, most operations value visible (Figure 2). You can downLISTING 2CODE SNIPPET
pass through the W register. One addi- load the subroutine from EDNs Web site,
tional instruction suffices to load any www.ednmag.com. Click on Search
general-purpose register into W before Databases and then enter the Software
Center to download the file for Design
calling the subroutine.
The code snippet in Listing 2 shows Idea #2594.
the addition of a 16-bit value called Result to a 24-bit Base value. Inserting call Is this the best Design Idea in this
Debug instructions at the points that the issue? Vote at www.ednmag.com/edn
arrows indicate makes the 16-bit Result mag/vote.asp.
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NiMH batteries................................................95
and R4 returns the feedback pin to
ground. R5 ensures that the base is high.
The
minimum
input
voltage
to
the
sysCircuit provides reverse-battery
tem is 5.6V if tON is 7 sec, the switching When the MC33342 needs to measure
protection ........................................................96
frequency is 100 kHz, VD is 0.3V, and VSAT the battery voltage, the VSEN pin pulls the
Transistor junctions monitor
is 1.2V. Selecting 6V as the input voltage base of Q1 low. The R3/R4 ratio ensures
temperature zones ........................................98
and allowing 0.1A ripple in the charging that the feedback pin is at a level higher
RTDs provide differential
current and 1.4V across the inductor at than its threshold. You must understand
temperature measurement ......................100
maximum charge, the calculated induc- the peak-voltage detector to properly detor value is 126 mH. The R6/R7 ratio sets sign the dc/dc converter. The detector
One-shot circuit is programmable ..........102
the fast-charge window. With VBAT at samples the battery voltage every 1.38
BIOS interrupt does eight-channel
3.05V, slightly higher than the maximum seconds. The sample time is 33 msec with
frequency counting ....................................102
charge level for the two cells, the ratio is an 11-msec preset time at the beginning.
0.525. With 10-mA bias current through During this preset time, the MC33342
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toggles the MC34063A into 0%-duty-cycle mode. This action shuts down the
current to the battery so the MC33342
can take an accurate voltage reading. The
inductor current must reach 0A during
the initial preset time to minimize errors
in the voltage reading.
RCS, R1, and R2 make up the tricklecharge circuit. To effect trickle charge,
this circuit connects to the current-limit
pin of the MC34063A to create an offset
for the maximum current. The open collector of the Fast/Trickle Charge pin goes
low to enter trickle-charge mode. When
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Figure 1
5V
2N3904
VDD
CHANNEL 1
IC1
ADG709
VDD
IC2
0.1 mF
VCC
10k
1k
D+
ADM1023
10k
mP OR mC
ALERT
STBY
CHANNEL 4
SCLK
D2
2N3904
EXPAND FOR
ADDITIONAL CHANNELS
1-OF-8
DECODER
D0
SDATA
D1
ALERT
INT
GND
SEL0
SEL1
GND
GND
A1
0
0
1
1
A0 CHANNEL
0
1
1
2
0
3
1
4
A0
A1
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