Verificacin de Sistemas Digitales

Hctor Sucar
Alejandro Moreno
Maestra en Diseo de Circuitos Integrados
ITESO

1. Intro to Verification

Development flow
Device specification
System requirements, external interface, architecture
Verification framework (test bench)

Micro-architecture specification
Design hierarchy and interfaces
Reference model
Verification plan, functional coverage

Functional implementation
RTL model
Verification checkers
RTL verification vs reference model
Coverage evaluation

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

Development flow (cont.)

Structural design
Logic synthesis, timing constraints
Full custom circuits (analog)
Gate-level model (unit delay)
Gate-level verification pre-SDF (mixed with RTL)
Mixed signal verification

*Standard Delay Format

*Register Transfer Level

Physical design and tape-out

Layout (synthesis & full custom)

*Layout vs. Schematic Verification
*Design Rules Checking
Layout integration and LVS/DRC
Formal verification
Gate-level verification post-SDF (timing back-annotation)

Fabrication

Mask generation
Wafer fabrication and packaging
Test generation (BIST, ATPG)
Fault grading

*Built-in Self-Test
*Automatic Test Pattern Generation

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

What is Verification?
To prove equivalence
To check/compare the expected or correct result
To find errors in the result
You are always verifying:

When you are shopping a good wine

When you are driving a car
Always

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

What is Hardware Verification?

Spec

DESIGN

Implementation

VERIFICATION

The process to determine that an implementation

behaves according to a given set of requirements
(Spec) for all possible scenarios

Hardware Verification = Correctness and Completeness

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

Verification vs. Validation

Verify
To prove that the implementation is a correct
functional representation of its specification.

Validate
To prove that the implementation is a correct physical
representation of its specification.

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

Verification vs. Testing

Manufacturing

HW Design

Spec

Silicon

RTL/Netlist
Verification

Verification
Proves the pre-silicon design
(implementation errors)

Testing

Testing
Proves the post-silicon design
(manufacturing defects)

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

Common Errors

Specification Errors: Ambiguous requirements

Interpretation: Human factor
Logic Bugs: Typical design bugs
Timing: Clock Hierarchy, Delays
Corner cases: Max/Min Values
Environment: Testbench

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

The Importance of Verification

Why Verification is important? R. Quality and Cost

Pre-Silicon
Low Cost

Post-Silicon
Pre-Production

Post-Production

Bugs are more costly

Very Expensive

If you find a bug in pre-silicon verification,

the cost is almost free, also it reduces the TTM

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

10

The Importance of Verification (cont.)

Development effort
Verification consumes about 70% of the development
effort, it involves: planning, environment, simulations,
debug, and many loops.

Critical path
Verification increases or decreases TTM, and it impacts
cost significantly.

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

11

The Importance of Verification (cont.)

Verification time can be reduced:

Parallelism: Human and Computing tasks.

Object Oriented Verification: Abstraction, Encapsulation,
Modularity, Polymorphism, Inheritance.

Automation: Automation lets you do something else while a

machine completes a task autonomously, faster and with
predictable results. It eliminates human factor.

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

12

The Importance of Verification (cont.)

Randomization: By constraining a random generator to
produce valid inputs within the bounds of a particular domain, it
is possible to automatically produce almost all of the interesting
conditions.

Functional Coverage: Automate tests to cover functionality is

better than specific testcases. FC identifies the circuit blocks that
were not exercised by analysis of simulation with random
stimulus.

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

13

The Importance of Verification (cont.)

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

14

Types of Hardware Verification

Structural Verification or Formal Verification
Proves the equivalence between two different representations or
models using formal methods.
Examples: Property Checking (Assertions), Equivalence Checking
(Synthesizable Model), or Model Checking.

Functional Verification
Proves the equivalence between two representations or models,
Reference Model and Functional Model -RTL- using simulation tools.

The course will be focused on Functional Verification

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

15

Functional Verification
The FV process is based on two principles:
Controllability - Ability of internal/external inputs to move the
model from any initial state to any other state: Stimuli
Observability - Ability of internal/external outputs to get the
current state of the model for analysis: Responses
Controllability
Stimuli

Functional
Models
RTL/RM

Observability
Response

What is a stimulus? What is a response?

How do you usually perform this process?
Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

16

Paradigms and Challenges

Verification Problem: what we are really verifying?
Verification Scope: when we really finish the verification?
Design for Verification: what verifies our verification
environment?
Interpretation: which interpretation is the best?
Human Factor: Human errors are always present
Mixed-Signal Verification: how to mix analog and digital
verification?
Object Oriented Verification : how to use HVL and OOP?

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

17

State of the Art

Techniques: Automation, Coverage-Driven, Assertion-Based
Languages: SystemVerilog, e-Laguage, SystemC.
Tools:
QuestaSim Mentor (evolution of ModelSim)
Specman Cadence
VCS Synopsys
VCS-NanoSim Synopsys (Mixed-Signal)
Methodologies: Based on Object Oriented, Layers,
AVM/OVM/UVM (Mentor/Cadence), VMM (Synopsys).

Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

18

Conclusions
Hardware Verification is the process to prove that an
implementation behaves according to the specification for all
possible scenarios.
Verification is the measure of quality of the product.
Verification time can be reduced through: Parallelism,
Abstraction, Automation, Randomization and Functional
Coverage.
Structural Verification proves the equivalence between two
representations or models using formal methods.
FV proves the equivalence between two models: RM vs RTL
using simulation tools. FV is based on Controllability and
Observability.
Verificacion de Sistemas Digitales - Maestra en Diseo de Circuitos Integrados - ITESO

19