1NK60Z PDF

STD1LNK60Z-1
STQ1NK60ZR - STN1NK60Z
N-CHANNEL 600V - 13 - 0.8A - TO-92 - IPAK - SOT-223
Zener-Protected SuperMESH Power MOSFET
General features
Type
VDSS
RDS(on)
ID
Pw
STD1LNK60Z-1
600V
<15
0.8A
25W
STQ1NK60ZR
600V
<15
0.3A
3W
STN1NK60Z
600V
<15
0.3A
3.3W
100% avalanche tested
Extremely high dv/dt capability
Gate charge minimized
ESD improved capability
New high voltage benchmark
TO-92 (Ammopak)
TO-92
SOT-223
Description
3
2
1
IPAK
Internal schematic diagram
The SuperMESH series is obtained through an

extreme optimization of STs well established
strip-based PowerMESH layout. In addition to
pushing on-resistance significantly down, special
care is taken to ensure a very good dv/dt
capability for the most demanding applications.
Such series complements ST full range of high
voltage MOSFETs including revolutionary
MDmesh products.
Applications
Switching application
Order codes
Sales Type
Marking
Package
Packaging
STD1LNK60Z-1
D1LNK60Z
IPAK
TUBE
STQ1NK60ZR
Q1NK60ZR
TO-92
BULK
STQ1NK60ZR-AP
Q1NK60ZR
TO-92
AMMOPAK
STN1NK60Z
1NK60Z
SOT-223
TAPE & REEL
February 2006
Rev 7
1/14
www.st.com
14
Electrical ratings
STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z
Electrical ratings
Table 1.
Absolute maximum ratings

Value
Symbol
Parameter
Unit
IPAK
VDS
TO-92
SOT-223
Drain-Source Voltage (V GS = 0)
600
VDGR
Drain-Gate Voltage (RGS = 20K)
600
VGS
Gate-Source Voltage
30
ID
Drain Current (continuous) at T C = 25C
0.8
ID
Drain Current (continuous) at T C=100C
0.5
0.189
Drain Current (pulsed)
3.2
1.2
Total Dissipation at T C = 25C
25
3.3
0.24
0.25
0.26
W/C
IDM
(1)
PTOT
Derating Factor
VESD(G-D)
dv/dt(2)
TJ
Tstg
0.3
0.3
Gate source ESD(HBM-C=100pF, R=1.5K)
800
Peak Diode Recovery voltage slope
4.5
V/ns
-55 to 150
Operating Junction Temperature

Storage Temperature
1. Pulse width limited by safe operating area

2. ISD 0.3A, di/dt 200A/s, VDD =80%V(BR)DSS
Table 2.
Thermal resistance
Value
Symbol
Rthj-case
Rthj-a
Rthj-lead
Tl
Parameter
Thermal resistance junction-case Max
Thermal resistance junction-ambient Max
Thermal resistance junction-lead Max
Maximum lead temperature for soldering
purpose
Unit
IPAK
TO-92
SOT-223
--
--
C/W
100
120
37.87(1)
C/W
--
40
--
C/W
275
260
Value
Unit
1. When mounted on 1 inch FR-4 board, 2 Oz Cu
Table 3.
Symbol
2/14
Avalanche data
Parameter
IAR
Avalanche Curent, Repetitive or Noy-Repetitive

(pulse width limited by Tj Max)
0.8
EAS
Single pulse avalanche Energy

(starting Tj=25C, Id=Iar, Vdd=50V)
60
mJ
Rev 7
Electrical characteristics
(TCASE=25C unless otherwise specified)
Table 4.
Symbol
On/off states
Parameter
Test Condictions
V(BR)DSS
Drain-Source Breakdown
Voltage
IDSS
Zero Gate Voltage Drain

Current (VGS = 0)
IGSS
Gate Body Leakage Current

VGS = 20V
(VDS = 0)
ID = 1mA, VGS= 0
Typ.
VDS= V GS, ID = 50A
RDS(on)
Static Drain-Source On
Resistance
VGS= 10V, ID= 0.4A
Unit
V
1
50
A
A
10
3.75
4..5
13
15
Typ.
Max.
Unit
VDS = MaxRating @125C
Gate Threshold Voltage
Max.
600
VDS = Max Rating,
VGS(th)
Table 5.
Min.
Dynamic
Symbol
Parameter
gfs (1)
Forward Transconductance
VDS =15V, ID = 0.4A
0.5
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
VDS =25V, f=1 MHz, V GS=0
94
17.6
2.8
pF
pF
pF
VGS=0, V DS =0V to 480V
11
pF
VDD=480V, ID = 0.8A
4.9
1
2.7
Ciss
Coss
Crss
Coss eq(2). Equivalent Output

Capacitance
Qg
Qgs
Qgd
Total Gate Charge

Gate-Source Charge
Gate-Drain Charge
Test Condictions
VGS =10V
(see Figure 11)
Min.
6.9
nC
nC
nC
1. Pulsed: pulse duration=300s, duty cycle 1.5%

2. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when VDS
inceases from 0 to 80% VDSS
Rev 7
3/14
Table 6.
Symbol
td(on)
tr
td(off)
tf
Table 7.
Symbol
Switching times
Parameter
Test Condictions
Turn-on Delay Time

Rise Time
Turn-off Delay Time
Fall Time
Min.
Typ.
Max.
Unit
5.5
5
13
28
VDD =300 V, ID= 0.4A,

RG=4.7, VGS=10V
(see Figure 19)
ns
ns
ns
ns
Source drain diode

Max
Unit
Source-drain Current
0.8
ISDM(1)
Source-drain Current (pulsed)
2.4
VSD(2)
Forward on Voltage
ISD=0.8A, VGS=0
1.6
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current
ISD=0.8A,
Reverse Recovery Time

Reverse Recovery Charge
Reverse Recovery Current
ISD=0.8A,
ISD
trr
Qrr
IRRM
trr
Qrr
IRRM
Parameter
Test Condictions
Min
di/dt = 100A/s,
VDD =20V, Tj=25C
di/dt = 100A/s,
VDD =20V, Tj=150C
Typ.
135
216
3.2
ns
nC
A
140
224
3.2
ns
nC
A
1. Pulse width limited by safe operating area

2. Pulsed: pulse duration=300s, duty cycle 1.5%
Table 8.
Symbol
BVGSO(1)
1.
4/14
Gate-source zener diode

Parameter
Gate-source Braekdown
Voltage
Test Condictions
Igs=1mA (Open Drain)
Min.
30
Typ.
Max.
Unit
V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only the devices
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the devices integrity. These integrated Zener diodes thus avoid the
usage of external components.
Rev 7
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area for IPAK
Figure 2.
Thermal impedance for IPAK
Figure 3.
Safe operating area for TO-92
Figure 4.
Thermal impedance for TO-92
Figure 5.
Safe operating area for SOT-223
Figure 6.
Thermal impedance for SOT-223
Rev 7
5/14
Figure 7.
Output characterisics
Figure 8.
Transfer characteristics
Figure 9.
Transconductance
Figure 10. Static drain-source on resistance
Figure 11. Gate charge vs gate-source voltage Figure 12. Capacitance variations
6/14
Rev 7
Figure 13. Normalized gate threshold voltage

vs temperature
Figure 14. Normalized on resistance vs

temperature
Figure 15. Source-drain diode forward

characteristics
Figure 16. Normalized BVDSS vs temperature
Figure 17. Maximum avalanche energy vs

temperature
Figure 18. Max Id Current vs Tc
Rev 7
7/14
Test circuit
Test circuit
Figure 19. Switching times test circuit for

resistive load
Figure 20. Gate charge test circuit
Figure 21. Test circuit for inductive load

Figure 22. Unclamped Inductive load test
switching and diode recovery times
circuit
Figure 23. Unclamped inductive waveform
8/14
Figure 24. Switching time waveform
Rev 7
Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect . The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
Rev 7
9/14
TO-92 MECHANICAL DATA

mm.
inch
DIM.
MIN.
MAX.
MIN.
TYP.
MAX.
4.32
4.95
0.170
0.194
0.36
0.51
0.014
0.020
4.45
4.95
0.175
0.194
3.30
3.94
0.130
0.155
2.41
2.67
0.094
0.105
0.055
e1
1.14
1.40
0.044
12.70
15.49
0.50
0.610
2.16
2.41
0.085
0.094
S1
0.92
1.52
0.036
0.060
0.41
0.56
0.016
10/14
TYP
0.022
5
Rev 7
TO-251 (IPAK) MECHANICAL DATA

mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A3
0.7
1.3
0.027
0.051
0.64
0.9
0.025
0.031
B2
5.2
5.4
0.204
0.212
B3
0.85
B5
0.033
0.3
0.012
B6
0.95
0.45
C2
0.48
6.4
6.6
0.037
0.6
0.017
0.023
0.6
0.019
0.023
6.2
0.236
0.244
0.252
0.260
4.4
4.6
0.173
0.181
15.9
16.3
0.626
0.641
9.4
0.354
0.370
L1
0.8
1.2
0.031
0.047
L2
0.8
0.031
0.039
A1
C2
A3
B3
=
=
B2
B5
D
B6
L2
L1
0068771-E
Rev 7
11/14
SOT-223 MECHANICAL DATA

mm
DIM.
mils
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
2.27
2.3
2.33
89.4
90.6
91.7
4.57
4.6
4.63
179.9
181.1
182.3
0.2
0.4
0.6
7.9
15.7
23.6
0.63
0.65
0.67
24.8
25.6
26.4
e1
1.5
1.6
1.7
59.1
63
66.9
e4
0.32
12.6
2.9
3.1
114.2
118.1
122.1
0.67
0.7
0.73
26.4
27.6
28.7
l1
6.7
7.3
263.8
275.6
287.4
l2
3.5
3.5
3.7
137.8
137.8
145.7
6.3
6.5
6.7
248
255.9
263.8
e1
l2
e4
l1
P008B
12/14
Rev 7
Revision history
Revision history
Table 9.
Revision history
Date
Revision
Changes
19-Mar-2003
First Release
15-May-2003
Removed DPAK
09-Jun-2003
Final datasheet
17-Nov-2004
Inserted SOT-223
15-Feb-2005
Modified Figure 3.
07-Sep-2005
Inserted ecopak indication
22-Feb-2006
New template
Rev 7
13/14
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STD1LNK60Z-1

100% avalanche tested

Extremely high dv/dt capability

Gate charge minimized

ESD improved capability

New high voltage benchmark

Internal schematic diagram

The SuperMESH series is obtained through an

TAPE & REEL

STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Absolute maximum ratings

Drain-Gate Voltage (RGS = 20K)

Drain Current (continuous) at T C = 25C

Drain Current (continuous) at T C=100C

Drain Current (pulsed)

Total Dissipation at T C = 25C

Gate source ESD(HBM-C=100pF, R=1.5K)

Peak Diode Recovery voltage slope

Operating Junction Temperature

1. Pulse width limited by safe operating area

1. When mounted on 1 inch FR-4 board, 2 Oz Cu

Avalanche Curent, Repetitive or Noy-Repetitive

Single pulse avalanche Energy

STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Zero Gate Voltage Drain

Gate Body Leakage Current

VDS= V GS, ID = 50A

VGS= 10V, ID= 0.4A

VDS = MaxRating @125C

Gate Threshold Voltage

VDS = Max Rating,

VDS =15V, ID = 0.4A

VDS =25V, f=1 MHz, V GS=0

VGS=0, V DS =0V to 480V

Coss eq(2). Equivalent Output

Total Gate Charge

1. Pulsed: pulse duration=300s, duty cycle 1.5%

STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Turn-on Delay Time

VDD =300 V, ID= 0.4A,

Source drain diode

Source-drain Current (pulsed)

Reverse Recovery Time

Reverse Recovery Time

1. Pulse width limited by safe operating area

Gate-source zener diode

STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Electrical characteristics (curves)

Safe operating area for IPAK

Thermal impedance for IPAK

Safe operating area for TO-92

Thermal impedance for TO-92

Safe operating area for SOT-223

Thermal impedance for SOT-223

STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Figure 10. Static drain-source on resistance

STD1LNK60Z-1 - STQ1NK60ZR - STN1NK60Z

Figure 13. Normalized gate threshold voltage

Figure 14. Normalized on resistance vs

Figure 15. Source-drain diode forward

Figure 16. Normalized BVDSS vs temperature

Figure 17. Maximum avalanche energy vs