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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 5, SEPTEMBER/OCTOBER 2014

Parameter Extraction Procedure for a Physics-Based

Power SiC Schottky Diode Model
Ruiyun Fu, Alexander E. Grekov, Kang Peng, and Enrico Santi, Senior Member, IEEE

AbstractA detailed parameter extraction procedure for a

simple physics-based power silicon carbide (SiC) Schottky diode
model is presented. The developed procedure includes the extraction of carrier concentration, active area, and thickness of the
drift region, which are needed in the power Schottky diode model.
The main advantage is that the developed procedure does not
require any knowledge of device fabrication, which is usually not
available to circuit designers. The only measurements required for
the parameter extraction are simple static IV characterization
and CV measurements. Furthermore, the physics-based SiC
Schottky diode model whose parameters are extracted by the
proposed procedure includes temperature dependences and is generally applicable to SiC Schottky diodes. The procedure is demonstrated for five Schottky diodes from two different manufacturers
having the following ratings: 600 V/50 A, 1.2 kV/3 A, 1.2 kV/7 A,
1.2 kV/20 A, and 600 V/4 A.
Index TermsParameter extraction procedure, physics-based
model, Schottky diode, silicon carbide (SiC).

I. I NTRODUCTION

ILICON CARBIDE (SiC) is one of the most promising semiconductor materials for high-voltage, high-speed,
and low-loss power switching applications. Excellent electrical
properties of SiC material, such as wider bandgap (3.26 eV),
higher thermal conductivity (4.9 W/cm K), and higher critical
breakdown electric field (2.2 106 V/cm, which is almost ten
times larger than Si), make it a very attractive semiconductor
material for power switching devices with capabilities that are
superior to those of devices based on silicon technology [1][3].
Owing to recent progress in SiC technology, SiC Schottky
diodes are now commercially available from several companies
such as Cree, GeneSiC, and Infineon. Since power devices
play a key role in power electronics applications, accurate and
computationally efficient power device models are required for
power electronics designers to evaluate the performance of
SiC Schottky diodes in different applications. So far, several
models have been developed for SiC Schottky diodes [4][10].

Manuscript received May 16, 2013; revised October 25, 2013; accepted
January 1, 2014. Date of publication February 5, 2014; date of current version
September 16, 2014. Paper 2013-PEDCC-282.R1, presented at the 2013 IEEE
Applied Power Electronics Conference and Exposition, Long Beach, CA, USA,
March 1721, and approved for publication in the IEEE T RANSACTIONS ON
I NDUSTRY A PPLICATIONS by the Power Electronic Devices and Components
Committee of the IEEE Industry Applications Society. This work was supported by the Office of Naval Research under Grant N00014-08-1-0080.
The authors are with the Department of Electrical Engineering, University
of South Carolina, Columbia, SC 29208 USA (e-mail: Ruiyun.Fu@sdsmt.edu;
GREKOV@cec.sc.edu; pengk@email.sc.edu; santi@engr.sc.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIA.2014.2304617

However, these models typically use either some fitting parameters that have no physical meaning or physical parameters that
are difficult to extract from experimental measurements. The
electrothermal macromodel in [4] is a standard piecewise linear
behavioral model. The model is simple, and the parameters
are easy to extract but have no physical meaning. The model
in [5] is a physics-based model implemented in the circuit
simulator Spice. The main feature of this model is that it takes
into account electrothermal (including self-heating) effects, but
it uses a few fitting parameters. The model in [6] is a simple
physics-based model for system modeling. The parameters in
this model are typical values from the literature. The physicsbased numerical model in [7] is based on the solution of the
semiconductor transport equations from the surface to the bulk
region. This model is accurate but complicated. The model in
[8] is a physics-based temperature-dependent model developed
in the Saber circuit simulator for Schottky merged PiN Schottky
(MPS) and PiN power diodes. Although this model can be used
in a wide range of test circuit conditions and for different types
of devices, it needs a few parameters that are unknown to the
designers. The parameter extraction sequence for this model is
given in [9]. Reference [10] shows an accurate analytical model
and complete parameter extraction of the forward characteristics of the Ni/6H-SiC Schottky barrier diodes (SBDs) for lowand high-level current densities using MEDICI program. This
model takes into account high-level injection effects and the
current dependence of the series resistance. The parameters are
extracted using the extraction program EXTRDEV.
In conclusion, some of the proposed physics-based models
provide good accuracy but usually need several device parameters (which are usually unknown to designers) to implement
the model for a specific device, and sometimes, the model
itself is overly complicated and requires long simulation time.
The SiC Schottky diode model presented in this paper is a
simple model that represents the basic physics behavior of the
device. This model has been implemented in PSPICE, a product
of CADENCE Corporation. The detailed parameter extraction
procedure introduced here does not require any knowledge of
device fabrication. The only measurements required for the
parameter extraction are simple static IV characterization and
CV measurement. These measurements are typically given
in the datasheets for commercial devices, so the parameter
extraction procedure can be performed based on datasheets
only. The extraction procedure is applied to several SiC power
diodes from different manufacturers. Results will be presented
for the following:
1) a 600-V 50-A Schottky diode from GeneSiC Inc.;
2) a 1200-V 3-A Schottky diode from GeneSiC Inc.;

0093-9994 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

FU et al.: PARAMETER EXTRACTION PROCEDURE FOR A PHYSICS-BASED POWER SiC SCHOTTKY DIODE MODEL

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TABLE I
S CHOTTKY D IODE M ODEL PARAMETERS

The series drift region resistance RD is given by

RD =

Fig. 1. (a) Structure of power Schottky diode. (b) Simple physics-based

Schottky diode model.

3) a 1200-V 7-A Schottky diode from GeneSiC Inc.;

4) a 1200-V 20-A Schottky diode from Cree Inc.;
5) a 600-V 4-A punch-through (PT) Schottky diode from
Cree Inc.
In Section II, the proposed physics-based model is introduced. The parameter extraction procedure is described in
Section III for non-PT (NPT) Schottky diodes, and the modifications needed for PT devices are described in Section IV.
In Section V, experimental validation is presented both under
static conditions and under inductive switching dynamic operation. Section VI presents a discussion of the results, and
Section VII presents the conclusion.
II. S IMPLE P HYSICS -BASED S CHOTTKY D IODE M ODEL
The structure of the power SiC Schottky diode with the
metalsemiconductor Schottky contact is shown in Fig. 1(a).
The simple physics-based Schottky diode model [shown in
Fig. 1(b)] is developed by using thermionic emission theory,
which describes the dominant carrier transport mechanism
in Schottky power rectifiers [11]. The model is comprised
of three elements: a voltage-controlled current source ID , a
temperature-dependent drift region resistance RD , and a nonlinear capacitance Cr .
In a SiC Schottky diode, the thermionic emission process
dominates in the current transport across the metal semiconductor contact. Under forward bias condition, the current across the
Schottky barrier is given by


ID = AA T 2 e(qb /kT ) e(qVD /nkT ) 1


(1)
= IS e(qVD /nkT ) 1
where IS is the saturation current density, A is the active area
of the diode, A is the Richardsons constant, b is the barrier
height between the metal and N-type semiconductor, n is the
ideality factor, T is the absolute temperature, q is the electron
charge, k is the Boltzmanns constant, and VD is the voltage
drop across the Schottky barrier.

LD
qD (T )ND A

(2)

where ND is the drift region carrier concentration, LD is the

thickness of the drift region, and D (T ) is the temperaturedependent electron mobility. Following [12], the temperaturedependent mobility can be expressed as

x
T
(3)
D (T ) = 300
300
where 300 is the carrier mobility at room temperature T =
300 K.
Since Schottky diode is a majority carrier device, there is
no minority carrier injection in the drift region during forward
conduction and no storage effect at diode turn-off. Consequently, the depletion layer capacitance determines the diodes
switching behavior. When a reverse bias voltage VR is applied
to the Schottky diode, a depletion region forms under the metal
semiconductor interface, and the depletion layer thickness Wr
can be calculated as [11]


20 r
20 r
(VR + Vbi )
(VR + b ). (4)
Wr =
qND
qND
Because all of the applied bias voltage is supported in the
semiconductor, this depletion width can be used to calculate
the nonlinear capacitance Cr of the Schottky diode as

qND 0 r
0 r A
.
(5)
=A
Cr =
Wr
2(VR + b )
The diode model described by (1)(5) is implemented in
Cadence Spice using the behavioral modeling source capability
of Spice. The nonlinear capacitor is implemented as a nonlinear
voltage-controlled current source. Since the capacitor current is
related to the voltage derivative, the capacitor implementation
may suffer from high-frequency noise problems. The use of a
bandwidth-limited derivative is recommended.
The complete list of the needed parameters for the considered
device model is given in Table I.
The proposed model neglects a number of physical effects.
This is done for simplicity and because a more complex device model capturing these effects would have a number of
parameters that cannot be easily extracted through measurements. Among the neglected effects are contact resistances and
substrate resistance. Several effects related to reverse leakage
current are also neglected, such as Schottky barrier lowering

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and avalanche multiplication. Also neglected is the fact that

many commercially available SiC diodes are not pure Schottky
diodes but junction barrier Schottky (JBS) also known as MPS.
Device manufacturers use this approach to reduce leakage current and to improve reverse blocking voltage capability. Under
extreme conditions such as very high temperature > 250 C and
high current density, the p-n junction in MPS and JBS diodes
also serves for improvement of the pulse current capability of
Schottky diodes. Since the proposed model does not consider
the effect of the p-n junction of the JBS structure on forward
conduction at extreme conditions such as very high temperature
and large forward bias, the validity of the proposed model is
limited to the nominal range of operation (< 200 C).
The effect of incomplete ionization can be neglected for
SBD since it consists of a metal and a semiconductor with
very low doping concentration (blocking region). The energy
level for nitrogentypical residual donor in low-doped SiCis
situated very close to the conduction band minimum (0.1 eV),
and therefore, ionization of nitrogen dopant in 4H-SiC occurs
with high rate (> 99%) even at room temperature. It is true
that the effect of incomplete doping ionization is significant
for devices with active region with moderate and high doping
concentrations (p-n junction, BJT). Since the proposed model
does not consider the effect of the p-n junction of the JBS or
MPS structure on forward conduction at extreme conditions
such as very high temperature and large forward bias, the effect
of incomplete ionization of dopant atoms is not included.

Fig. 2. (a) Structure of NPT Schottky diode. (b) Electric field distribution
along the drift region.

III. PARAMETER E XTRACTION P ROCEDURE

The proposed parameter extraction procedure is equally applicable to NPT and PT Schottky diodes. This section describes
the NPT case, and the next section describes the modifications
needed to apply the method to PT devices.
The parameter extraction approach discussed in this section
is based on the assumption that the Schottky diode is NPT and
that the carrier mobility at room temperature 300 is known.
The theoretical value of mobility for low-doped 4H-SiC material at room temperature is 980 cm2 /V s [13]. From past
experience in characterization of SiC MOSFETs and JFETs
[12], it was found that the actual room temperature electron
mobility is smaller than theoretical value and is in the range of
400600 cm2 /V s. Therefore, a value of 300 = 500 cm2 /V
s is used in this work.
With an NPT Schottky diode structure shown in Fig. 2(a), it is
assumed that the low-doped drift region is completely depleted
when the breakdown reverse voltage is applied. In other words,
the breakdown voltage coincides with the PT point. Under
this assumption, the breakdown voltage of the device can be
calculated by calculating the triangular area under the electric
field profile shown in Fig. 2(b).
A. Drift Region Parameters ND , LD , and A
To extract the drift region parameters ND , LD , and A, the
static IV characterization and CV measurements of the
Schottky diode are needed. The IV measurements in this work
are performed using a Tektronix 371 A power curve tracer, and
the CV measurements are performed using a Keithley 590 CV

Fig. 3. IV characteristics from 25 C to 175 for the 600-V 50-A GeneSiC

Schottky diode.

analyzer. The value of series resistance RD can be estimated

from the slope of the IV characteristics at high currents, as
shown in Fig. 3 for the 600-V 50-A GeneSiC Schottky diode.
Therefore, the slope S1 of the IV characteristics at a certain
temperature can be calculated from
S1 =

1
qD ND A
=
.
RD
LD

(6)

Besides the IV characteristics of the Schottky diode, CV

measurement is needed for the extraction procedure. Fig. 4
shows the CV characteristics of the 600-V 50-A GeneSiC
Schottky diode at measurement frequency f = 1 MHz.
From (5), one obtains
2
1
= 2
(VR + Vbi ).
Cr2
A qND 0 r

(7)

Therefore, the slope S2 of 1/Cr2 versus VR is given by

S2 =

2
.
A2 qND 0 r

(8)

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3561

cation process can affect the barrier height of the diodes. The
barrier height b can be extracted using the following steps.
Rewrite (1) for V  kT /q as
ln(I) = ln(Is ) +

qV
.
nkT

(13)

From the semilog plot of ln(I) versus V , the intercept of the

current axis at V = 0 gives the saturation current Is . The barrier
height b can be expressed as


AA T 2
kT
ln
b =
.
(14)
q
Is

Fig. 4. CV measurement of the 600-V 50-A GeneSiC Schottky diode.

(a) Cr versus Vr . (b) 1/Cr2 versus Vr .

Based on the assumption of a triangular electric field distribution shown in Fig. 2(b), one can calculate the device thickness
based on the breakdown voltage VB as

20 r VB
.
(9)
LD =
qND
Substituting (9) into (6) and squaring both sides, one obtains
S12 =

3 2
D A2
q 3 ND
.
20 r VB

(10)

Rewriting (8) to get an expression for A2 and then substituting it into (10), an expression for carrier concentration as a
function of breakdown voltage and slopes S1 and S2 can be
obtained

S 1 0 r V B S 2
.
(11)
ND =
qD
This is the first parameter extraction equation. Then, substituting the value for ND found using (11) back into (8), the
active area A can be calculated as

2
.
(12)
A=
S2 qND 0 r
For a specific device with known breakdown voltage, by capturing the IV characteristics and CV measurements of the
Schottky diode at room temperature, the drift region parameters
ND , LD , and A can be extracted using (11), (9), and (12),
respectively. The breakdown voltage can be either estimated
from the datasheets or measured with a power curve tracer.
B. Barrier Height b and Temperature Coefficient x
The barrier height b is defined as the potential difference
between the metal Fermi level and the majority carrier band
edge of the semiconductor. Barrier height of Schottky diodes
depends on the fabrication process and semiconductor material.
Any surface contamination introduced during the diode fabri-

Based on the assumption that the carrier mobility at room

temperature 300 is known (500 cm2 /V s is used in this
work), the temperature coefficient of carrier mobility x can be
calculated by using the value of mobility extracted from static
characteristics at an elevated temperature T1 [12]


ln (T1 ) /300
.
(15)
x=
ln(T1 /300)
For 4H-SiC, the theoretical value of Richardsons constant
A is 146 A cm2 K2 [6]. For simplicity, the ideality factor
n is assumed to be unity.
In conclusion, the parameter extraction procedure consists of
the following steps.
1) Assume that the Richardsons constant is A = 146 A
cm2 K2 , the ideality factor is n = 1, and the carrier
mobility at room temperature 300 has a known value
(500 cm2 /V s is used in this work).
2) Obtain slope S1 from the IV characteristics and slope
S2 from the CV measurement [see Figs. 3 and 4(b)].
3) Calculate the drift region parameters ND , LD , and A by
using (11), (9), and (12), respectively.
4) Extract barrier height b from the IV characteristics by
using (14).
5) Calculate the corresponding carrier mobility (T1 ) at one
elevated temperature T1 . Mobility at elevated temperature
T1 is calculated using (6), since all other quantities in (6)
are known, including the measured slope S1 at elevated
temperatures and carrier concentration ND previously
extracted from slope S1 at room temperature in step 3.
6) Extract the temperature coefficient x of carrier mobility
by using (15).
IV. M ODIFICATIONS OF PARAMETER E XTRACTION
P ROCEDURE FOR A PT S CHOTTKY D IODE
For a PT Schottky diode shown in Fig. 1(a), the parameter
extraction procedure is quite similar to the NPT case described
previously. The only difference is that the voltage used to
calculate the drift region thickness LD is not the breakdown
voltage VB but the PT voltage VPT that totally depletes the drift
region. In PT operation, the CV characteristic of the Schottky
diode is shown in Fig. 5. Once the drift region is totally depleted
at voltage VPT , any further increase in applied voltage does not
cause a decrease in the incremental capacitance Cr , which is
constant and equal to CPT and no longer dependent on reverse

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Fig. 5. CV characteristics of a PT Schottky diode.

bias. Using this feature, it is straightforward to establish from

the CV characteristic whether a Schottky diode operates in
PT mode or not. Note that the CV characteristic must be
measured over an extended voltage range all the way to rated
blocking voltage.
When the depletion region just hits the N /N+ interface
at voltage VPT , the electric field profile along the drift region is
triangular and is shown in Fig. 2(b). Therefore, the thickness of
the drift region can be calculated using (16), which replaces (9)

20 r VPT
LD =
(16)
qND
where VPT is the voltage totally depleting the drift region. This
voltage can be obtained from the diode CV characteristic
(see Fig. 5).
Therefore, the carrier concentration in drift region ND can
be rewritten as

S1 0 r VPT S2
ND =
.
(17)
qD
The parameter extraction procedure for the PT case is identical to the procedure for the NPT case given in Section III,
except that step 3) is modified to the following.
3) Calculate the drift region parameters ND , LD , and A by
using (17), (16), and (12), respectively.
The nonlinear capacitance model in the simple Schottky
diode model needs to be modified: its value needs to have a
lower bound equal to the PT capacitance CPT at voltage VPT .
The IV characteristics and CV characteristics needed for
the extraction procedure can typically be found in the device
datasheet provided by the manufacturer. In this paper, the PT
parameter extraction procedure is applied to the 600-V 4-A PT
Schottky diode C3 D04060A from Cree Inc. Since the Keithley
590 CV measurement setup available in our laboratory is
limited to a maximum bias voltage of 100 V, the parameter
extraction data are obtained from the datasheet. The actual IV
and CV data obtained by scanning the Cree datasheets using
the Plot Digitizer software program are shown in Fig. 6.
V. VALIDATION OF PARAMETER E XTRACTION
P ROCEDURE AND S CHOTTKY D IODE M ODEL
The parameter extraction procedure is applied to several
SiC Schottky diodes: 600-V 50-A, 1200-V 3-A, and 1200-V
7-A Schottky diodes from GeneSiC Inc., and a 1200-V 20-A

Fig. 6. Characteristics of 600-V/4-A PT Schottky diode scanned from

datasheet. (a) IV curves. (b) CV curve.
TABLE II
E XTRACTED PARAMETERS

Schottky diode and a 600-V 4-A PT Schottky diode from Cree

Inc. Table II gives the extracted parameters of the five devices
with the assumption that room temperature electron mobility
300 is 550 cm2 /V s. After all Schottky diode parameters
are extracted, the model defined by (1), (2), and (5) can be
validated. Fig. 7 shows the comparison of the simulated (dashed
lines) IV characteristics of SiC Schottky diodes based on
extracted parameters, with experimental (solid lines) static
characteristics for temperatures from 25 C to 175 C. The
temperature step is t = 50 C. The simulated IV curves are
in fairly good agreement with the experimental results for the
five devices. Fig. 8 shows the comparison of simulated (dashed
lines) with experimental CV characteristics of SiC Schottky
diodes measured at frequency f = 1 MHz. Fig. 9 shows the
comparison of the corresponding curves of 1/Cr2 versus reverse
voltage Vr . Figs. 8 and 9 demonstrate that the simulated CV
curves have fairly good agreement with the experimental results, which is very important for switching performance, even
if some discrepancy can be seen at low voltages.

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Fig. 7. Comparison of simulated (dashed lines) with experimental (solid lines) static characteristics of SiC Schottky diodes measured at a temperature from 25 C
to 175 C. (a) GeneSiC 1200 V, 3 A. (b) GeneSiC 1200, 7 A. (c) Cree 1200 V, 20 A. (d) GeneSiC 600 V, 50 A. (e) Cree 600 V, 4 A (estimated from datasheet).

For a dynamic characteristic validation, a Double Pulse Tester

was built to perform inductive switching experiments on these
five SiC Schottky diodes. The active device used for the experiment was a 1200-V 24-A n-channel SiC MOSFET from Cree,
Inc., part number CMF10120D. Fig. 10 shows the corresponding inductive circuit used in the simulation, which includes various parasitic inductances. The gate-to-source switching loop
and drain-to-source switching loop parasitic inductances of the
PCB layout are extracted by the 3-D inductance extraction program FastHenry, which uses partial element equivalent circuit
method for magneto-quasistatic analysis of 3-D packages and

interconnects [14]. The simulation uses the MOSFET model

proposed in [15], which models the nonuniform current distribution in the JFET region by using a nonlinear controlled voltage source and a resistance network. VDR is the voltage across
the Schottky diode, and ISCH denotes the current through the
diode, which are both shown in the figure. Comparisons between experimental and simulated results are shown in Fig. 11
for inductive switching of the device GeneSiC 1200 V, 3 A.
Figs. 1215 are the inductive switching comparisons of the devices GeneSiC 1200, 7 A; Cree 1200 V, 20 A; GeneSiC 600 V,
50 A; and Cree 600 V, 4 A (PT), respectively.

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Fig. 8. Comparison of simulated (dashed lines) with experimental (solid lines) CV characteristics of SiC Schottky diodes measured at frequency = 1 MHz.
(a) GeneSiC 1200 V, 3 A. (b) GeneSiC 1200, 7 A. (c) Cree 1200 V, 20 A. (d) GeneSiC 600 V, 50 A. (e) Cree 600 V, 4 A (estimated from datasheet).

VI. D ISCUSSION
The proposed Schottky diode model is a simple physicsbased model whose parameters are extracted using a combination of IV and CV measurements, without the need for
device manufacturing information.
The parameter extraction procedure proposed in this paper
is based on the assumption that the carrier mobility at room
temperature 300 in the drift region is known. The critical
point of the procedure is to obtain the slope S1 from the IV
characteristics and slope S2 from CV measurement so that the
drift region parameters ND , LD , and A can be extracted. These
parameters are critical for the accuracy of the proposed Schottky diode model under both static and dynamic conditions. For
PT devices, the parameter extraction procedure is the same as
that of the NPT devices. The only difference is that the PT
point voltage is used in place of the breakdown voltage in the
equation used to determine the drift region thickness. The IV
characteristics and CV characteristics can be either obtained
from datasheets, as shown in Fig. 6 for the 600-V 4-A PT
device, or measured experimentally, as shown in Fig. 7(a)(d)
for the other four devices.
The results of the parameter extraction procedure are shown
in Table II. The values of doping concentration and drift
region thickness appear reasonable for SiC and show fairly
similar design choices. Table III shows a comparison of the

diode designs based on the extracted parameters of Table II.

Notice the similar values of rated current density JF , in
the range of 140180 A/cm2 , except for the fourth device,
which has a significantly larger current density. The second
column shows the calculated peak electric field Emax at rated
voltage, calculated using the triangular electric field profile
of Fig. 2(b) for the NPT devices and a trapezoidal profile
for the PT device. This electric field is approximately one
half of the critical electric field (Ec = 2.8 E 6 V/cm) for
a doping concentration of 3E15 cm3 [16]. The last two
columns show the specific diode resistance calculated using (2)
and the capacitance per unit area at rated voltage calculated
using (5).
Fig. 7 shows pretty good agreement between simulated and
experimental results of IV static characteristics for all devices
at different temperatures, especially in the linear regions occurring at high current levels. At low current levels, some discrepancies can be seen. These discrepancies could be reduced
by using a nonunity ideality factor n extracted from the IV
characteristics, whereas the ideality factor n of the model is
chosen to be unity for simplicity in this paper. Since the low
current region does not play an important role in determining
conduction losses and during switching transients, the simple
model appears to be adequate for modeling of SiC Schottky
diodes for switching converter applications.

FU et al.: PARAMETER EXTRACTION PROCEDURE FOR A PHYSICS-BASED POWER SiC SCHOTTKY DIODE MODEL

3565

Fig. 9. Corresponding comparisons of simulated (dashed lines) with experimental (solid lines) 1/C2 V characteristics of SiC Schottky diodes measured at
frequency = 1 MHz. (a) GeneSiC 1200 V, 3 A. (b) GeneSiC 1200, 7 A. (c) Cree 1200 V, 20 A. (d) GeneSiC 600 V, 50 A. (e) Cree 600 V, 4 A (estimated from
datasheet).

Fig. 10. Equivalent circuit used for inductive switching simulation.

Figs. 8 and 9 show the comparisons between simulated and

experimental results of CV measurements of four different
SiC Schottky diodes. Some discrepancies appear at low voltage
in Fig. 8. One reason for this is overestimating the active
area of the Schottky diodes by using the proposed parameter
extraction procedure based on a pure Schottky diode structure
while some tested Schottky diodes are actually JBS or MPS.
Another reason may be that the quantity used in the extraction
procedure is the slope S2 of the curves 1/Cr2 versus Vr and not
the absolute capacitance values. Fig. 9 shows the curves 1/Cr2
versus Vr , which are very close to straight lines, as expected
from (7), indicating that the doping concentration in the drift
region is uniform. Some nonlinear features appear in Fig. 9
at low voltage, possibly due to the JBS structure. To improve
the Schottky diode model, one could take into account these
nonlinear features at low voltage in the parameter extraction
procedure. This is left as future work. Note that the plots in
Fig. 9 tend to overemphasize discrepancies at high voltages:
for example, the flat asymptote for the PT capacitance in
Fig. 9(e) shows a large visual discrepancy; however, the relative
capacitance error with respect to the low-voltage capacitance is
less than 5%.

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Fig. 11. Simulated (dashed) and experimental (solid) waveforms of inductive

switching for Schottky diode GeneSiC 1200 V, 3 A. (a) Turn-on. (b) Turn-off
(2 A/div, 100 V/div).

Fig. 12. Simulated (dashed) and experimental (solid) waveforms of inductive

switching for Schottky diode GeneSiC 1200 V, 7 A. (a) Turn-on. (b) Turn-off
(5 A/div, 100 V/div).

Fig. 13. Simulated (dashed) and experimental (solid) waveforms of inductive

switching for Schottky diode Cree 1200 V, 20 A. (a) Turn-on. (b) Turn-off
(5 A/div, 100 V/div).

Fig. 14. Simulated (dashed) and experimental (solid) waveforms of inductive

switching for Schottky diode GeneSiC 600 V, 50 A. (a) Turn-on. (b) Turn-off
(5 A/div, 100 V/div).

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VII. C ONCLUSION
The proposed parameter extraction procedure includes the
extraction of doping concentration, active area, and thickness
of the drift region, which are needed for the proposed physicsbased power Schottky diode model. The main advantage is
that this procedure does not require any knowledge of device
fabrication. The only measurements required for the parameter
extraction are simple static IV characterization and CV measurements. Validity of the approach is verified by comparison of
simulated and experimental results at temperatures from 25 C
to 175 C for five different devices from two different manufacturers. Inductive switching validation also shows that the model
provides a fairly good match with experiments. This shows that
the parameter extraction procedure and model presented in this
paper are generally applicable to SiC Schottky diodes.
ACKNOWLEDGMENT
The authors would like to thank GeneSiC Inc. for providing
some of the diodes used in this work.
R EFERENCES

Fig. 15. Simulated (dashed) and experimental (solid) waveforms of inductive

switching for Schottky diode Cree 600 V, 4 A (PT). (a) Turn-on (2 A/div,
100 V/div). (b) Turn-off (5 A/div, 100 V/div).
TABLE III
D EVICE C OMPARISON BASED ON E XTRACTED PARAMETERS

The inductive switching validations in Figs. 1115 for the

five different Schottky diodes show good agreements in the
turn-on and turn-off transients. The simulation results in
Figs. 13 and 14 show more ringing compared with the experimental results. The ringing is caused by the interaction between
the diode and the rest of the circuit, including the SiC MOSFET,
the bus capacitors, and the PCB traces. Accurate prediction of
this ringing requires accurate modeling of all of these elements
and is beyond the scope of this paper.
In conclusion, the proposed Schottky diode model can be
generally used for a wide range of devices with different
blocking voltage and current ratings and is capable of accurately describing device operation under static and dynamic
conditions.

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3568

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 50, NO. 5, SEPTEMBER/OCTOBER 2014

Ruiyun Fu received the B.S. and M.S. degrees in

electrical engineering from Huazhong University of
Science and Technology, Wuhan, China, in 2004 and
2007, respectively, and the Ph.D. degree from the
University of South Carolina, Columbia, SC, USA,
in 2013.
She is currently an Assistant Professor with the
School of Engineering, Mercer University, Macon,
GA, USA. Her research is focused on modeling and
simulation of power semiconductor devices.

Alexander E. Grekov received the M.S. degree from

Taganrog State University of Radio Engineering,
Taganrog, Russia, in 1996 and the Ph.D. degree in
electrical engineering from the University of South
Carolina (USC), Columbia, SC, USA, in 2005.
He is currently a Research Associate with the
Department of Electrical Engineering, USC. His research interests include design, simulation, and modeling of SiC power devices and circuits.

Kang Peng received the B.S. degree in electrical engineering from Hunan University, Changsha, China,
in 2008 and the M.S. degree in electrical engineering
from Huazhong University of Science and Technology, Wuhan, China, in 2011. He has been working
toward the Ph.D. degree at the University of South
Carolina, Columbia, SC, USA, since August 2011.
His research interests include power semiconductor device modeling and applications.

Enrico Santi (S90M94SM02) received the

Dr.Ing. degree in electrical engineering from the
University of Padua, Padova, Italy, in 1988 and
the M.S. and Ph.D. degrees from the California Institute of Technology, Pasadena, CA, USA, in 1989
and 1994, respectively.
He was a Senior Design Engineer with TESLAco
from 1993 to 1998, where he was responsible for the
development of various switching power supplies for
commercial applications. Since 1998, he has been
with the University of South Carolina, Columbia,
SC, USA, where he is currently an Associate Professor with the Department of
Electrical Engineering. He has published over 100 papers on power electronics
and modeling and simulation in international journals and conference proceedings. He is the holder of two patents. His research interests include switchedmode power converters, advanced modeling and simulation of power systems,
modeling and simulation of semiconductor power devices, and control of power
electronics systems.