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4.a) What is clock skew? Explain how clock skew affects the digital
system. What is the maximum allowable skew for the parameters
T =10 ns, tpr = 1 ns, tsr = 1 ns, tsl = 1 ns, tpl = 5 ns, tp = 5 ns. What
is the minimum allowable clock period under these conditions?
b) What is ATPG? DFT? Generate a set of Sequential tests for the
“01” – string recognizer which test for all stuck – at – 0/1 faults,
assuming you don’t know the initial state.
Contd….2
Code No: 54105/MT -2-
8.a) How would you translate a register transfer structure into a legal
2-phase latched sequential machine?
b) Write short notes on any two of the following:
i) Differentiate the devices PAL, PLA and FPGA
ii) Cross-talk
iii) Placement and routing in floor planning.
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