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Global Institute & Technology

ITS-2, EPIP, IT-Park Jaipur 302022


Ph.0141-2770445
E-mail: support@gitjaipur.com

Estd. 2002

COURSE FILE
Subject Name:
Code:

-1-

Name

: Bharti Sharma

Branch

: ECE

Semester

: VII

CAD for VLSI


7CS4

Session

: 2011-2012

Year : 4th
Global Institute Technology, Jaipur

Index - Course File

(Approved by AICTE and Affiliated to RTU, Kota)

S. No.

Content /Item no.

Page No.

Performance of Students in
Mid Term Exams
COURSE FILE
1

Time Table

Syllabus

Performance of Students in
Mid Term Exams
LECTURE PLAN

Objective/Outcomes

16

19

The Schedule for the


Course / Subject
COURSE
SCHEDULE(Unit Wise)
LECTURE PLAN

ASSIGNMENT SHEET

61

10

10

20
25

Performance of Assignment 66

11

Question Bank

68

12

Objective Question Bank

73

13

Mid term Question Papers

80

14

Model Test Papers

82

-2-

Sem : VII

Remarks
Faculty

HOD

Dean

Year : 4th
COURSE FILE
Global Institute Technology, Jaipur
(Approved by AICTE and Affiliated to RTU, Kota)

Subject: CAD for VLSI

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

Sem : VII

Course Details
Name of the Programme

B.Tech

Batch

2008-2012

Branch

CSE

Semester

VII

Title of the Subject

CAD for VLSI

Subject Code : 7CS4

CORE Subject

No. of Students: 72

Note to the Faculty Member on how to use this course file format?
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.

-3-

Time Table and syllabus copy must be enclosed.


Please attach the Marks List of the Students in respect of MTE I (Mid Term Exam), and MTE II for this subject
in your Course File.
TFTT (Time Frame Time Table/ Course Plan).
Lecture Plan.
Tutorial Sheet (If required, as per the syllabus).
List of Assignments / Seminar Topics given to students should also be included in the Course File.
Unit Test.
Lab manual if required.
Model Question Paper of the subject which would be distributed to the students, should be included in the
Course File Papers (Question Bank of important Questions).
Question of previous years (University) .
Mid Term Question Paper ( I & II).
Performance of the unit test should the enclosed.
Grading of Assignment.
Photocopy of the best and the average answer sheets of MTE I & II, should be included in the Course File.
Photocopy of the best and the average assignment copies should be enclosed in the course file.
Any additional resources like OHP transparencies, handouts used may also be enclosed.

Year : 4th
COURSE FILE
Global Institute of Technology,
Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

1.

TARGET ACHIEVED:
Percentage a) Passing the Examination
b) Scoring above 60%

2.

:
: .

COURSE PLAN
(Please write how you intend to cover the syllabus: i.e. coverage of Units by lecturers, guest lecturers, design
exercises, solving numerical problems, demonstration of models, model preparation, or by assignment, etc.)

METHOD OF EVALUATION
3.1

Mid Term Examinations (MTE I & II)

3.2

Assignment / Semesters

3.3

Mini Projects

3.4

Quiz

3.5

Term End Examination

3.6

Others (Unit Test Papers)

List out any new topic (s) or any innovation you would like to introduce in teaching the subject in this semester

Signature of Head of the Department

Signature of Faculty

Date

Date

-4-

Year : 4th
COURSE FILE
Time Table

Global Institute of Technology,


Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

Time
/ Day

08:1008:55
I

Mon

CAD for VLSI


(7 CS)
(LH-65)

8:55-9:50
II

9:5010:45
IV

10:4511:40
IV

11:4012:20
V-A

12:2001:15
V-B

01:1502:10
VI

CAD for VLSI


(7 CS)
(LH-65)

Tue
B
R
E
A
K

Wed

CAD for VLSI


(7 CS)
(LH-65)

Thus
Fri

Signature of Head of the Department

-5-

Signature of Faculty

02:1003:05
VII

Date

Date

Year : 4th
COURSE FILE
Global Institute of Technology,
Jaipur

Syllabus

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

Unit I
Complexity in microelectronic circuit design and Moores Law, design styles Full custom design,
standard-cell design, Programmable Logic Devices, Field Programmable Gate Arrays, Design Stages,
Computer-Aided Synthesis and Optimizations, design flow and related problems.
Unit II
Boolean functions and its representations co-factor, unite, derivatives, consensus and smoothing; tabular
representations and Binary Decision Diagram (BDD), OBDD, ROBDD and Bryants reduction algorithm
and ITE algorithm. Hardware abstract models structures and logic networks, State diagram, data-flow
and sequencing graphs, hierarchical sequencing graphs. Compilation and behavioral optimizations.
Unit III
Architectural Synthesis Circuit description and problem definition, temporal and spatial domain
scheduling, synchronization problem. Scheduling algorithms ASAP and ALAP scheduling algorithms,
scheduling under constraints, relative scheduling, list scheduling heuristic. Scheduling in pipelined
circuits.
Unit IV

-6-

Resource Sharing & Binding in sequencing graphs for resource dominated circuits, sharing of registers
and busses; binding variables to registers. Two-level logic optimization principles definitions and exact
logic minimizations.
Positional cube notations, functions with multi-valued logic. List-oriented manipulations.
Unit V
Physical Design. Floor planning goals and objectives. Channel definition, I/O and power planning.
Clock Planning. Placement goals and objectives. Placement algorithms. Iterative improvement
algorithms. Simulated Annealing. Timing-driven Placement. Global routing goals and objectives. Global
routing methods. Timingdriven global routing. Detailed Routing goals and objectives. Left-edge
algorithm. Constraints and routing graphs. Channel routing algorithms. Via minimization. Clock routing,
power routing, circuit extraction and Design Rule Checking

Textbooks:
1. BK1. G.D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill
2. BK2. Michael John Sebastian Smith. Application-Specific Integrated Circuits. Addison-Wesley

(Downloaded at: http://iroi.seu.edu.cn/books/asics)


References:
1. BK4. S. Sait and H. Youssef,VLSI Physical Design Automation theory and practice

Signature of Head of the Department

-7-

Signature of Faculty

Date

Date

Year : 4th

Performance of Students in
Mid Term Exams

Global Institute Technology, Jaipur


(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

S. No.

Roll No.

Student Name
1Term

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

-8-

Sem : VII

Max. Marks:- 20
2Term
Average

08EGJCS001

AAKRITI RAMAN

19

19

08EGJCS002

ABHIJEET JAIN

20

19

08EGJCS003

ABHIJEET SHARMA

14

18

08EGJCS004

ABHISHEK SHARMA

18

14

08EGJCS005

ABHINAV GUPTA

14

12

08EGJCS006

AMBIKA TRIPATHI

20

19

08EGJCS007

ANCHAL GANGWAL

17

11

08EGJCS008

ANISH KUMAR YADAV

18

14

08EGJCS009

ANISHA AGARWAL

18

19

08EGJCS010

ANKIT KUMAR JAIN

19

17

08EGJCS011

ANSHUMAN TIWARI

12

14

08EGJCS012

ARCHANA GUPTA

14

15

08EGJCS013

ARJUN KUMAWAT

18

17

08EGJCS014

ASHISH JAIN

18

14

08EGJCS015

ASHISH RAWAT

11

10

08EGJCS016

CHITRAKSH VYAS

16

14

08EGJCS017

DEEPTI SINGH

14

16

08EGJCS018

DIVYANSH KASLIWAL

16

19

08EGJCS019

GAGAN UTREJA

17

18

08EGJCS020

GAURAV SALUJA

16

AB

08EGJCS021

GAURAV SHARMA

14

13

08EGJCS022

GAURAV SINGHAL

16

12

08EGJCS023

HASIN

19

17

08EGJCS024

HIMANSHI SANDHANI

17

18

08EGJCS025

JASARAJ KHATRI

16

14

08EGJCS026

JYOTI CHOTIA

19

18

08EGJCS027

KANIKA BANSAL

17

12

08EGJCS028

KHUSHBOO POKHARNA

16

14

08EGJCS029

KOMAL NAGPAL

20

20

08EGJCS030

KOMAL SONI

16

18

19
20
16
16
13
20
14
16
19
18
13
15
18
16
11
15
15
18
18
8
14
14
18
18
15
19
15
15
20
17

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

08EGJCS031

KRITI JAIN

16

12

08EGJCS032

KRITIKA JAIN

11

18

08EGJCS033

MANISH KUMAR

20

20

08EGJCS034

MOHIT JAIN

19

15

08EGJCS035

NAVEEN BHARDWAJ

12

12

08EGJCS036
08EGJCS037

NEERAJ PARETA
NEHA GUPTA

10

12

19

18

08EGJCS038

NIKET JAIN

18

17

08EGJCS039

NIKHIL BHARADWAJ

14

13

08EGJCS040

NIKITA SHARMA

20

16

08EGJCS041

NIRMAL KUMAR

12

13

08EGJCS042

NITIN AGARWAL

19

18

08EGJCS043

PRASHANT JAIN

18

17

08EGJCS044

PRASHANT JINDAL

16

15

08EGJCS045

PRIYA BANSAL

14

13

08EGJCS046

PRIYANKA SHARMA

20

13

08EGJCS047

PUNEET AGARWAL

20

19

08EGJCS048

RAGHAV VYAS

18

19

08EGJCS049

RAJNEESH SINGH

17

17

08EGJCS050

RAVI NYATI

13

08EGJCS051

RIDUM KULSHRESTHA

20

19

08EGJCS052

RITA BALA

19

20

08EGJCS053

ROHIT AGARWAL

19

19

08EGJCS054

ROHIT ARORA

18

15

08EGJCS055

ROHIT GUPTA

15

13

08EGJCS056

SANYA AGGARWAL

17

18

08EGJCS057

SONAL SHARMA

19

19

08EGJCS058

SUPRIYA JAIN

19

19

08EGJCS059

SURBHI JODHA

18

17

08EGJCS060

TANMAY GUPTA

19

18

08EGJCS061

TANMAY MISHRA

12

12

08EGJCS062

VAIBHAV SAXENA

18

15

08EGJCS063

VERSHA GUPTA

19

19

08EGJCS064

VINAYAK PANCHOLI

14

18

08EGJCS065

VISHAL AGRAWAL

18

17

08EGJCS066

VIVEK SONI

16

14

09EGJCS200

ARVIND KUMAR UPPADHYAY

18

17

09EGJCS201

BIJENDRA SINGH

16

16

09EGJCS202

MADHUSUDAN PRAJAPATI

18

19

09EGJCS203

ROHATSH SINGH

19

18

09EGJCS204

SUDEEP KUMAR

17

19

09EGJCS205

YOGESH GAUTAM

13

16

14
15
20
17
12
11
19
18
14
18
13
19
18
16
14
17
20
19
17
10
20
20
19
17
14
18
19
19
18
19
12
17
19
16
18
15
18
16
19
19
18
15

Signature of Head of the Department

Signature of Faculty

Date

Date

-9-

Year : 4th
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date:
1.

Subject

: CAD for VLSI

Subject Code: 7CS4

2.

Lesson No.

:I

Duration of Lesson: 7

3.

Title

: Introduction to Microelectronics Circuits

S.NO.

Topic:

Time
Allotted

Introduction, Complexity in microelectronic circuit design and Moores


Law

Design Styles Full-custom design, Semi Custom Design styles


standard-cell design

3
4
5
6
7

Programmable Logic Devices,

Field Programmable Gate Arrays

design flow and related problems

Design Stages,

Computer-Aided Synthesis and


Optimizations

Level of Difficulty (for faculty):


Teaching Aids:Teaching Points:Reference Readings:-

- 10 -

1
Tough

Easy

Year : 4th
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date:
1.

Subject

: CAD for VLSI

Subject Code: 7CS4

2.

Lesson No.

: II

Duration of Lesson: 6

3.

Title

: Boolean functions and its representations

S.NO.
1

Time
Allotted

Topic:
Boolean functions and its representations co-factor, unite,
derivatives,consensus and smoothing

tabular representations and Binary Decision Diagram (BDD)


2
3
4
5
6

1
OBDD, ROBDD and Bryants reduction algorithm and ITE algorithm
Hardware abstract models structures and logic networks, State
diagram
data-flow and sequencing graphs, hierarchical sequencing graphs
Compilation and behavioral optimizations.

Level of Difficulty (for faculty):


Teaching Aids:Teaching Points:Reference Readings:-

- 11 -

Tough

1
1
1
1

Easy

Year : 4th
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date:
1.

Subject

: CAD for VLSI

Subject Code: 7CS4

2.

Lesson No.

: IV

Duration of Lesson: 8

3.

Title

: Architectural Synthesis

S.NO.
1
2
3
4
5
6
7
8

Time
Allotted

Topic:
Architectural Synthesis Circuit description and problem definition
temporal and spatial domain scheduling

Synchronization problem.

Scheduling algorithms ASAP and ALAP scheduling algorithms


scheduling under constraints

Scheduling with resource constraints , list scheduling heuristic


Heuristic scheduling, Scheduling in pipelined circuits

Reference Readings:-

- 12 -

1
1

relative scheduling

Level of Difficulty (for faculty):


Teaching Aids:Teaching Points:-

Tough

1
1

Easy

Year : 4th
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date:
Subject Code: 7CS4

1.

Subject

: CAD for VLSI

2.

Lesson No.

: IV

3.

Title

: Resource Sharing & Binding

S.NO.
1

Duration of Lesson: 6
Time
Allotted

Topic:
Resource Sharing & Binding in sequencing graphs for resource
dominated circuits

sharing of registers and busses


2
3
4
5
6
7

1
binding variables to registers.

Two-level logic optimization principles

definitions and exact logic minimizations

Positional cube notations, functions with multi-valued logic


List-oriented manipulations

Level of Difficulty (for faculty):


Teaching Aids:Teaching Points:Reference Readings:-

- 13 -

1
1

Tough

Easy

Year : 4th
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date:
Subject Code: 7CS4

1.

Subject

: CAD for VLSI

2.

Lesson No.

:V

3.

Title

: Physical Design

S.NO.
1
2
3
4
5
6

Duration of Lesson: 8
Time
Allotted

Topic:
Physical Design. Floor planning goals and objectives

Channel definition, I/O and power planning, Clock Planning.


Placement
Placement algorithms. Iterative improvement algorithms

1
1

Simulated Annealing. Timing-driven Placement. Global routing


goals and objectives
Global routing methods. Timing-driven global routing
Detailed Routing goals and objectives Lef-edge algorithm

1
1
1

Constraints and routing graphs, Channel routing algorithms. Via


minimization

Clock routing, power routing, circuit extraction and Design Rule


Checking

Level of Difficulty (for faculty):


Teaching Aids:Teaching Points:-

Tough

Easy

Reference Readings:-

Year : 4th
- 14 -

COURSE FILE
Global
of

Institute

Sem : VII

Technology, Jaipur
(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

Guidelines to Study the Subject

The design of electronic circuits can be achieved at many different


refinement levels from the most detailed layout to the most abstract
architectures. Given the complexity of Very Large Scaled Integrated
Circuits

(VLSI)

which

is

far

beyond

human

ability,

computers

are

increasingly used to aid in the design and optimization processes. It is no


longer efficient to use manual design techniques, in which each layer is
hand etched or composed by laying tape on film due to the time consuming
process and lack of accuracy. Therefore, Computer Aided Design (CAD)
tools are heavily involved in the design process. In todays market, there
are plenty of VLSI CAD tools; however, most of them are expensive and
require high performance platforms. Selecting an appropriate CAD tool for
academic use is considered as one of the key challenges in teaching VLSI
design courses. In this paper, number of open-source and freeware CAD
tools are presented and evaluated. Based on the objectives of the user,
this subject

furnishes guidelines that help in selecting the most

appropriate open-source and freeware VLSI CAD tool for teaching a VLSI
design course.

Prerequisite
(3CS5) Digital Electronics
(5CS2) Digital Logic Design
- 15 -

Year : 4th
COURSE FILE
Objective/Outcomes

Global Institute of Technology,


Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

On completion of this Subject / Course the students shall be able to :


S.No. Objectives
1.
Ability to apply knowledge of basic digital

2.
3.

4.

Outcomes
Introduction, Design Styles, Computer-

electronics, physical science, Graph theory, Basic

Aided Synthesis and Optimizations,

concepts in VLSI CAD to model and analyze some

Design Stages, Programmable Logic

Digital Circuits
Ability to design implement and analyze basic digital

Devices
Complexity in microelectronic circuit

components and circuits

design, FPGAs, Architectural Synthesis

Basic skill in methods of design and analysis across a

Boolean functions and its representations,

broad range of electronicsl and computer engineering

Hardware abstract models, Compilation

areas

and behavioral optimizations, Physical

Advance expertise in design , analysis and

Design
Scheduling algorithms, Resource Sharing

fabrication techniques within a student selected

& Binding, Two-level logic optimization

electrical and computer engineering concentration

principles, Floor planning, Placement,

area

Global routing,
Detailed Routing and circuit extraction

Ability to use techniques, Skills and modern tools

and Design Rule Checking


Architectural Synthesis, Physical Design,

necessary for engineering practice

Two-level logic optimization


Signature of Faculty

- 16 -

Date

Note : For each of the OBJECTIVE indicate the appropriate OUTCOMES to be achieved.

Year : 4th
COURSE FILE
Global Institute of Technology,
Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

:
The expected outcomes of the Course / Subject are :
S.No.
a

General Categories of Outcomes


Specific Outcomes of the Course
Ability to apply knowledge of basic digital Study of Basics of CAD VLSI
electronics, physical science, Graph theory,
Basic concepts in VLSI CAD to model and

b
c

analyze some Digital Circuits


Ability to design implement and analyze Study of Basics of Digital Systems and their
Implementation
basic digital components and circuits
Basic skill in methods of design and analysis
across a broad range of electrical and
computer engineering areas

Advance expertise in design , analysis and


fabrication techniques within a student
selected electrical and computer engineering

concentration area
Ability to use techniques, Skills and modern Synthesis of Tools used for CAD VLSI and Design
Methodologies
tools necessary for engineering practice

Objectives Outcome Relationship Matrix (Indicate the relationship by x mark).


- 17 -

Outcomes

a
Objectives

1
2
3
4
5

- 18 -

Year : 4th
COURSE FILE
Schedule

Global Institute of Technology,


Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

The Schedule for the Course / Subject is:


S.No.
1

Description/Units
Unit 1Introduction to
Microelectronics
Circuits
Unit-2- Boolean
functions and
its
representations
Unit-3-

Architectural
Synthesis

Unit-4Resource Sharing
& Binding

Expected Date of
Completion
18/08/11

Revision Date

Total No. of
Periods

18/08/11
7

01/09/11

01/09/11

26/09/11

26/09/11

17/10/11

17/10/11

08/11/11

08/11/11

Unit-5Physical Design

Total No. of Instruction Periods available for the course: Hours / Periods

- 19 -

Year : 4th
COURSE SCHEDULE(Unit Wise)
Global Institute of Technology,
Jaipur

UNIT - I

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

S.No.

Date
25/7/11

26/7/11

No. of
Periods

Topics / Sub Topics

Objectives
& Outcome
Nos.

Introduction, Complexity in
microelectronic circuit design and
Moores Law
Design Styles Full-custom design,
Semi Custom Design styles
standard-cell design

Reference (Text Book,


Journal.) Page
No.to
BK-1/3-5
BK-1/6-11

01/08/11

Programmable Logic Devices,

http://iroi.seu.edu.cn/
books/asics/Book2/CH01/
CH01.1.htm#pgfId=1331

02/08/11

Field Programmable Gate Arrays

08/08/11

design flow and related problems

12/08/11

Design Stages,

BK-1/12-14

18/08/11

Computer-Aided Synthesis and


Optimizations

BK-1/14-19

18/08/11

Remedial Class

Signature of Faculty
Date
Note :

1.
2.
3.

ENSURE THAT ALL THE TOPICS SPECIFIED IN THE COURSE ARE MENTIONED.
ADDITIONAL TOPICS COVERED, IF ANY, MAY ALSO BE SPECIFIED IN BOLD.
MENTION THE CORRESPONDING COURSE OBJECTIVE AND OUTCOME NUMBERS AGAINST EACH TOPIC.

- 20 -

Year : 4th
COURSE SCHEDULE(Unit Wise)
Global Institute of Technology,
Jaipur

UNIT II

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

2.

Designation

: Assistant Professor

3.

Department

: ECE

S.No.

Date

19/08/11

23/08/11

25/08/11

26/08/11

29/08/11

01/09/11

01/09/11

No. of
Periods

Bharti Sharma

Topics / Sub Topics

Objectives &
Outcome
Nos.
2

Boolean functions and its


representations co-factor, unite,
derivatives,consensus and smoothing
tabular representations and Binary
Decision Diagram (BDD)
OBDD, ROBDD and Bryants
reduction algorithm and ITE
algorithm
Hardware abstract models
structures and logic networks, State
diagram
data-flow and sequencing graphs,
hierarchical sequencing graphs
Compilation and behavioral
optimizations.
Remedial Class

Reference (Text
Book, Journal.)
Page No.to
BK-1/67-74
BK-1/73-75
BK-1/76-83
BK-1/115-119
BK-1/119-125
BK-1/126-136

Signature of Faculty
Date
Note :

1.
2.
3.

ENSURE THAT ALL THE TOPICS SPECIFIED IN THE COURSE ARE MENTIONED.
ADDITIONAL TOPICS COVERED, IF ANY, MAY ALSO BE SPECIFIED IN BOLD.
MENTION THE CORRESPONDING COURSE OBJECTIVE AND OUTCOME NUMBERS AGAINST EACH
TOPIC.

- 21 -

Year : 4th
Global
Institute
of Technology, Jaipur
COURSE SCHEDULE(Unit Wise)
(Approved by AICTE and Affiliated to RTU, Kota)

UNIT IV

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE
No. of
Periods

Topics / Sub Topics

Sem : VII

S.No.

Date

Objectives
Reference (Text
& Outcome Book, Journal.)
Nos.
Page No.to
3
BK-1/143-146

02/09/11

Architectural Synthesis Circuit


description and problem definition

05/09/11

BK-1/146-153

08/09/11

temporal and spatial domain


scheduling
Synchronization problem.

12/09/11

BK-1/187-190

15/09/11

Scheduling algorithms ASAP and


ALAP scheduling algorithms
scheduling under constraints

6
7

15/09/11
16/09/11

26/09/11

BK-1/193-197
BK-1/198-202
BK-1/202-209
BK-1/211-215
BK-1/211-215

26/09/11

relative scheduling
Scheduling with resource constraints ,
list scheduling heuristic
Heuristic scheduling, Scheduling in
pipelined circuits
Remedial Class

BK-1/154-155

BK-1/190-193

Signature of Faculty
Date
Note :

1.
2.
3.

ENSURE THAT ALL THE TOPICS SPECIFIED IN THE COURSE ARE MENTIONED.
ADDITIONAL TOPICS COVERED, IF ANY, MAY ALSO BE SPECIFIED IN BOLD.
MENTION THE CORRESPONDING COURSE OBJECTIVE AND OUTCOME NUMBERS AGAINST
EACH TOPIC.

- 22 -

Year : 4th
COURSE SCHEDULE(Unit Wise)
Global Institute of Technology,
Jaipur

UNIT IV

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

: ECE

S.No.

Date

No. of
Periods

Topics / Sub Topics

Objectives
Reference (Text
& Outcome Book, Journal.)
Nos.
Page No.to
BK-1/230-240
3

03/10/11

04/10/11

Resource Sharing & Binding in


sequencing graphs for resource
dominated circuits
sharing of registers and busses

07/10/11

binding variables to registers.

BK-1/245-250

10/10/11

BK-1/270-276

11/10/11

14/10/11

17/10/11
17/10/11

Two-level logic optimization


principles
definitions and exact logic
minimizations
Positional cube notations, functions
with multi-valued logic
List-oriented manipulations
Remedial Class

BK-1/240-245

BK-1/277-283
BK-1/288-291
BK-1/291-294

Signature of Faculty
Date
Note :

1.
2.
3.

ENSURE THAT ALL THE TOPICS SPECIFIED IN THE COURSE ARE MENTIONED.
ADDITIONAL TOPICS COVERED, IF ANY, MAY ALSO BE SPECIFIED IN BOLD.
MENTION THE CORRESPONDING COURSE OBJECTIVE AND OUTCOME NUMBERS AGAINST EACH
TOPIC.

- 23 -

Year : 4th
COURSE SCHEDULE(Unit Wise)
Global Institute of Technology,
Jaipur

UNIT V

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

2.

Designation

: Assistant Professor

3.

Department

: ECE

S.No.

Date

18/10/11

21/10/11

31/10/11

01/11/11

03/11/11

04/11/11

07/11/11

08/11/11

08/11/11

No. of
Periods

Bharti Sharma

Topics / Sub Topics

Objectives
Reference (Text
& Outcome Book, Journal.)
Nos.
Page No.to
http://iroi.seu.edu.cn/
4
books/asics/Book2/
CH16/CH16.htm

Physical Design. Floor planning


goals and objectives
Channel definition, I/O and power
planning, Clock Planning. Placement
Placement algorithms. Iterative
improvement algorithms
Simulated Annealing. Timing-driven
Placement. Global routing goals
and objectives
Global routing methods. Timingdriven global routing
Detailed Routing goals and
objectives Lef-edge algorithm
Constraints and routing graphs,
Channel routing algorithms. Via
minimization
Clock routing, power routing, circuit
extraction and Design Rule Checking
Remedial Class

Signature of Faculty
Date
Note :

1.
2.
3.

ENSURE THAT ALL THE TOPICS SPECIFIED IN THE COURSE ARE MENTIONED.
ADDITIONAL TOPICS COVERED, IF ANY, MAY ALSO BE SPECIFIED IN BOLD.
MENTION THE CORRESPONDING COURSE OBJECTIVE AND OUTCOME NUMBERS AGAINST EACH
TOPIC.

- 24 -

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 01/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:1

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

Introduction,

Complexity in microelectronic circuit design

15

Moores Law

10

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 25 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 02/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:2

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

Design Styles

Full-custom design, Semi Custom Design styles

30

standard-cell design

10

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 26 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 03/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:3

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
Programmable Logic Devices,

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 27 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 04/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:4

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
Field Programmable Gate Arrays

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 28 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 05/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:5

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
20

Topic:

design flow and

related problems to Design flow

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 29 -

30

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 08/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:6

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
Design Stages

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 30 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 09/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:7

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

Computer-Aided Synthesis

Optimizations

15

Reviews

30

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 31 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 10/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:8

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

Boolean functions

Representation of Boolean functions

25

co-factor, unite, derivatives,consensus and smoothing

15

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 32 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 16/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:9

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

Tabular representations and

Binary Decision Diagram (BDD)

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 33 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 16/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 10

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

OBDD,

ROBDD

20

Bryants reduction algorithm

10

ITE algorithm

10

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 34 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 17/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 11

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
20

Topic:

Hardware abstract models,

structures and logic networks

10

State diagram

20

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 35 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 19/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 12

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

data-flow and sequencing graphs,

hierarchical sequencing graphs

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 36 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : V

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 23/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 13

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
20

Topic:

Compilation and behavioral optimizations.

Reviews

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 37 -

30

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 01/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 14

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

Architectural Synthesis

Circuit description and problem definition

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 38 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 02/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 15

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

temporal domain scheduling

spatial domain scheduling

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 39 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 03/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 16

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
Synchronization problem.

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 40 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 04/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 17

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
Scheduling algorithms ASAP and ALAP scheduling algorithms

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 41 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 05/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 18

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
scheduling under constraints

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 42 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 08/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 19

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
relative scheduling

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 43 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 09/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 20

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

Scheduling with resource constraints

list scheduling heuristic

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 44 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 10/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 21

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

Heuristic scheduling

Scheduling in pipelined circuits

10

Reviews

30

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 45 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 16/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 22

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

Resource Sharing for resource dominated circuits

Binding in sequencing graphs for resource dominated circuits

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 46 -

Tough

25

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 16/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 23

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

sharing of registers

sharing of busses

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 47 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 17/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 24

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
binding variables to registers.

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 48 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 01/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 25

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
Two-level logic optimization principles

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 49 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 02/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 26

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
definitions and exact logic minimizations

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 50 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 03/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 27

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
20

Topic:

Positional cube notations

functions with multi-valued logic

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 51 -

30

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 04/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 28

Duration of Lecture

: 55 minutes

S.NO.
1

Time
Allotted
50

Topic:
List-oriented manipulations

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 52 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 05/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 29

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
20

Topic:

Physical Design.

Floor planning goals and objectives

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 53 -

30

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 08/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 30

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

Channel definition, ,

I/O and power planning

10

Clock Planning.

20

Placement

10

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 54 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 09/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 31

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

Placement algorithms.

Iterative improvement algorithms

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 55 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 10/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 32

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

Simulated Annealing.

Timing-driven Placement.

25

Global routing goals and objectives

15

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 56 -

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 16/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

:33

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
25

Topic:

Global routing methods.

Timing-driven global routing

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 57 -

25

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 16/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 34

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
30

Topic:

Detailed Routing goals and objectives

Lef-edge algorithm

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 58 -

20

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 17/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 35

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
20

Topic:

Constraints and routing graphs,.

Channel routing algorithms Via minimization

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 59 -

30

Tough

Easy

Year : IV
LECTURE PLAN
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Date: 19/08/11
1.

Subject

: CAD for VLSI

Subject Code

: 7CS4

2.

Lecture No.

: 36

Duration of Lecture

: 55 minutes

S.NO.

Time
Allotted
10

Topic:

Clock routing, ,

power routing

10

circuit extraction

10

Design Rule Checking

20

Level of Difficulty (for faculty):


Teaching Aids:Reference Readings:-

- 60 -

Tough

Easy

Year : 4th
ASSIGNMENT SHEET-I
Sem : VII

Global Institute of Technology, Jaipur


(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE
Date of Assignment: .
Date of Submission: ..

This Assignment corresponds to Unit No.I

Q1. What is Moores Law? Explain Design Styles of Microelectronic Circuits


Q2. Explain Programmable Logic Devices in detail
Q3. Explain FPGA (Field Programmable Gate Arrays)? How it is Different from MPGA
(Mask Programmable Gate Arrays).
Q4. Give Advantages of computer Aided Synthesis and optimization
Q5. Differentiate Custom Design Style with Semicustom Design Style

Signature of Head of the Department

Signature of Faculty

Date

Date

- 61 -

Year : 4th
ASSIGNMENT SHEET-II
Sem : VII

Global Institute of Technology, Jaipur


(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

E CE

Date of Assignment: .
Date of Submission: ..
This Assignment corresponds to Unit No.II

Q1.What is Boolean Function? Explain how Boolean functions can be represented


Q2. Explain ROBDD in detail also give its Algorithm
Q3. Explain Bryants reduction algorithm and ITE algorithm in detail
Q4. Explain State Diagrams and Data Flow Diagrams with the help of an Example
Q5. Describe Compilation and Behavioral Optimization in detail

Signature of Head of the Department

Signature of Faculty

Date

Date

- 62 -

Year : 4th
ASSIGNMENT SHEET-III
Sem : VII

Global Institute of Technology, Jaipur


(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE
Date of Assignment: .
Date of Submission: ..

This Assignment corresponds to Unit No.III

Q1. What is Architectural Synthesis? Explain with the help of an Example


Q2. Explain Temporal Domain Scheduling and Spatial Domain Scheduling
Q3. What is Synchronization Problem? Explain with the help of an example
Q4. Describe Resources and Constraints with their types
Q5. How scheduling can be achieved in pipelined circuits? Explain with the help of an example

- 63 -

Signature of Head of the Department

Signature of Faculty

Date

Date

Year : 4th
ASSIGNMENT SHEET-IV
Sem : VII

Global Institute of Technology, Jaipur


(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE
Date of Assignment: .
Date of Submission: ..

This Assignment corresponds to Unit No.IV

Q1. Explain Sequencing graphs? How Resource sharing is done in sequential graphs
Q2. Explain binding with the help of an example also explain how it is differ from partial
Binding
Q3. Explain two level logic optimization principles
Q4. What is the difference between single valued logic and multi valued logic
Q5. Explain Positional Cube Notations with the help of an Example

Signature of Head of the Department

Signature of Faculty

Date

Date

- 64 -

Year : 4th
ASSIGNMENT SHEET-V
Sem : VII

Global Institute of Technology, Jaipur


(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE
Date of Assignment: .
Date of Submission: ..

This Assignment corresponds to Unit No.V

Q1. Explain Floor Planning with its Goals and Objectives


Q2. Describe Placement Algorithms with its Applications
Q3. What is Global Routing? Explain with its Goals and Objectives
Q4. Explain Left-Edge Algorithm
Q5. What is Circuit Extraction and Design Rule Checking? Explain

Signature of Head of the Department

- 65 -

Signature of Faculty

Date

Date

Year : 4th

Performance of Assignment
Sem : VII

Global Institute of Technology, Jaipur


(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

S. No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

- 66 -

Roll No.

ECE

Student Name

08EGJCS001

AAKRITI RAMAN

08EGJCS002

ABHIJEET JAIN

08EGJCS003

ABHIJEET SHARMA

08EGJCS004

ABHISHEK SHARMA

08EGJCS005

ABHINAV GUPTA

08EGJCS006

AMBIKA TRIPATHI

08EGJCS007

ANCHAL GANGWAL

08EGJCS008

ANISH KUMAR YADAV

08EGJCS009

ANISHA AGARWAL

08EGJCS010

ANKIT KUMAR JAIN

08EGJCS011

ANSHUMAN TIWARI

08EGJCS012

ARCHANA GUPTA

08EGJCS013

ARJUN KUMAWAT

08EGJCS014

ASHISH JAIN

08EGJCS015

ASHISH RAWAT

08EGJCS016

CHITRAKSH VYAS

08EGJCS017

DEEPTI SINGH

08EGJCS018

DIVYANSH KASLIWAL

08EGJCS019

GAGAN UTREJA

08EGJCS020

GAURAV SALUJA

08EGJCS021

GAURAV SHARMA

08EGJCS022

GAURAV SINGHAL

08EGJCS023

HASIN

08EGJCS024

HIMANSHI SANDHANI

08EGJCS025

JASARAJ KHATRI

08EGJCS026

JYOTI CHOTIA

08EGJCS027

KANIKA BANSAL

08EGJCS028

KHUSHBOO POKHARNA

08EGJCS029

KOMAL NAGPAL

Grades
#1 #2
A
A
A
A+
A
B
A
A+
A+ A
A
A+
A
A
A
B
A
A+
B
A
B
C
A
A
A
B
A+ A
A
B
A
B
A+ A
A
B
A+ A
B
B
A
B
A
A+
A+ A
A
A
A
A+
B
B
A+ A
A
A
A+ A+

Average
#3
A+
A
B
A
A
A+
A
A
A
A
B
A
A+
A
B
A
A
B
A+
B
B
A+
A
B
B
A
A+
A
A+

#4
A+
A
A
A
A
A+
A
A
B
B
C
A
A
A
A
A
A
A
A
A
A
B
A
A
A
B
A
A+
A

#5
A+
A+
B
A
A+
A
A
B
B
B
C
A
A
A+
B
B
A+
A
A+
B
B
B
A+
A+
A
A
A+
A
A

A+
A
B
A
A
A+
A
A
A
B
C
A
A
A
B
A
A
A
A
B
B
A
A
A
A
B
A
A
A+

30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

08EGJCS030

KOMAL SONI

08EGJCS031

KRITI JAIN

08EGJCS032

KRITIKA JAIN

08EGJCS033

MANISH KUMAR

08EGJCS034

MOHIT JAIN

08EGJCS035

NAVEEN BHARDWAJ

08EGJCS036
08EGJCS037

NEERAJ PARETA
NEHA GUPTA

08EGJCS038

NIKET JAIN

08EGJCS039

NIKHIL BHARADWAJ

08EGJCS040

NIKITA SHARMA

08EGJCS041

NIRMAL KUMAR

08EGJCS042

NITIN AGARWAL

08EGJCS043

PRASHANT JAIN

08EGJCS044

PRASHANT JINDAL

08EGJCS045

PRIYA BANSAL

08EGJCS046

PRIYANKA SHARMA

08EGJCS047

PUNEET AGARWAL

08EGJCS048

RAGHAV VYAS

08EGJCS049

RAJNEESH SINGH

08EGJCS050

RAVI NYATI

08EGJCS051

RIDUM KULSHRESTHA

08EGJCS052

RITA BALA

08EGJCS053

ROHIT AGARWAL

08EGJCS054

ROHIT ARORA

08EGJCS055

ROHIT GUPTA

08EGJCS056

SANYA AGGARWAL

08EGJCS057

SONAL SHARMA

08EGJCS058

SUPRIYA JAIN

08EGJCS059

SURBHI JODHA

08EGJCS060

TANMAY GUPTA

08EGJCS061

TANMAY MISHRA

08EGJCS062

VAIBHAV SAXENA

08EGJCS063

VERSHA GUPTA

08EGJCS064

VINAYAK PANCHOLI

08EGJCS065

VISHAL AGRAWAL

08EGJCS066

VIVEK SONI

09EGJCS200

ARVIND KUMAR UPPADHYAY

09EGJCS201

BIJENDRA SINGH

09EGJCS202

MADHUSUDAN PRAJAPATI

09EGJCS203

ROHATSH SINGH

09EGJCS204

SUDEEP KUMAR

09EGJCS205

YOGESH GAUTAM

Signature Faculty
- 67 -

A
A
A
A+
A
A
B
A
A+
A
A
A
A+
A
A
A
A
A+
A
A
A
A
A
B
A
A
A+
A
A
A
A+
B
A
A+
A
A
A+
A
A
A
A
A
A

B
B
B
A
A+
B
A
B
A
B
B
A
A
A
A
A
B
A
B
A
A
B
B
A
A+
B
A
B
B
B
A
B
B
A
B
B
A
A
B
A
B
B
B

B
B
A
A
B
B+
B
A+
A
B
A
A+
A
B
A
B
A
A
A
A
B
B
A
A
A
A
A
B
B
B
A
B
A
A
A
B
A
B
B
A
B
B
A

A
A
A
A
A
A
B+
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
A
A
A
A
A
A
A
A

Signature HOD

B
B
B
A+
A
B
B
A
A+
A
B
A
A+
A
B
A
A
A+
B
B
B
B
B
A
A
A
A+
B
B
A
A+
B
A
A+
B
B
A+
A
B
A
B
B
B

B
B
A
A
A
B
B
A
A
A
B
A
A
A
B
A
A
A
A
A
A
B
A
B
A
A
A
B
B
A
A
B
A
A
B
B
A
A
B
A
B
B
A

Year : 4th
Question Bank
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE

Unit-1
Q1. What is Moores Law? Explain Design Styles of Microelectronic Circuits
Q2. Explain Programmable Logic Devices in detail
Q3. Explain FPGA (Field Programmable Gate Arrays)? How it is Different from MPGA
(Mask Programmable Gate Arrays).
Q4. Give Advantages of computer Aided Synthesis and optimization
Q5. Differentiate Custom Design Style with Semicustom Design Styles
Q6 Explain the Difference between FPGA & MPGA
Q7 what are the problems related to the Design flow
Q8 Explain Various types of Optimizations in Microelectronic circuits
Q9 Explain Cell based design Styles with its Types
Q10 Explain Arrayl based design Styles with its Types

- 68 -

Year : 4th
Question Bank
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE

Unit-II
Q1.What is Boolean Function?
Q2. Explain ROBDD in detail also give its Algorithm
Q3. Explain Bryants reduction algorithm in detail
Q4. Explain State Diagrams
Q5. Describe Compilation and Behavioral Optimization in detail
Q6 Explain Data Flow Diagrams with the help of an Example
Q7 Explain how Boolean functions can be represented
Q8 Explain ITE algorithm in detail
Q9 Explain Hierarchical Sequencing Graphs with the help of an example
Q10 write Short notes on structures and logic networks

- 69 -

Year : 4th
Global

Institute of
Technology, Jaipur

Question Bank
Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE

Unit-III
Q1. What is Architectural Synthesis? Explain with the help of an Example
Q2. Explain Temporal Domain Scheduling
Q3. What is Synchronization Problem? Explain with the help of an example
Q4. Describe Resources and Constraints with their types
Q5. How scheduling can be achieved in pipelined circuits? Explain with the help of an example
Q6 Explain ASAP scheduling algorithms with the help of an Example
Q7 Explain ALAP scheduling algorithms
Q8 Explain Spatial Domain Scheduling
Q9 what is list scheduling heuristic? Explain
Q10 Explain Force Directed scheduling

- 70 -

Year : 4th
Question Bank
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE

Unit-IV

Q1. Explain Sequencing graphs in detail


Q2. Explain binding with the help of an example
Q3. Explain two level logic optimization principles
Q4. What is the difference between single valued logic and multi valued logic
Q5. Explain Positional Cube Notations with the help of an Example
Q6 How Resource sharing is done in sequential graphs
Q7 explain how Partial Binding is differ from partial Binding
Q8 What is List Oriented Manipulation? Explain
Q9 How Registers and busses can be shared? Explain

- 71 -

Year : 4th
Question Bank
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE

Unit-V

Q1. Explain Floor Planning with its Goals and Objectives


Q2. Describe Placement Algorithms with its Applications
Q3. What is Global Routing? Explain with its Goals and Objectives
Q4. Explain Left-Edge Algorithm
Q5. What is Circuit Extraction ? Explain
Q6 What is Design Rule Checking? Explain
Q7 Explain detailed Routing
Q8 Explain Channel Routing Algorithms
Q9 Write Short note on Simulated Annealing
Q10 Write Short note on Clock Planning

- 72 -

Year : 4th
Objective Question Bank
Global Institute of Technology, Jaipur

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE

1. The voltage levels for a negative logic system


(a) must necessarily be negative
(b) could be negative or positive
(c) must necessarily be positive
(d) must necessarily be either zero or 5 V
2. The output Qn of a J-K flip-flop is zero. It changes to 1 when a clock pulse is applied. The inputs Jn and
Kn are respectively
(a) 1 and X
(b) 0 and X
(c) X and 0
(d) X and 1
3. The larger the RAM of a computer, the faster is its speed, since it eliminates
(a) need for ROM
(b) need for external memory
(c) frequency disk I/O s
(d) need for a data-wide path
4. DB, DW and DD directives are used to place data in particular location or to simply allocate space
without preassigning anything to space. The DW and DD directories are used to generate
(a) offsets
- 73 -

(b) full address of variables


(c) full address of labels
(d)offsets of full address of labels and variables
5. The number of bits needed to address 4K memory is
(a)6
(b) 8
(c)12
(d) 16
6. The ESC instruction of 8086 may have two formats. In one of the formats, no memory operand is used.
Under this format, the number of external op-codes (for the co-processor) which can be specified is?
(a) 64
(b) 128
(c) 256
(d) 512
7. The TRAP is one of the interrupts available its INTEL 8085. Which one of the following statements is
true of TRAP?
(a) It is level triggered
(b) It is negative edge triggered
(c) It is positive edge triggered
(d) It is both positive edge triggered and level triggered
8. In a 16-bit microprocessor, words are stored in two consecutive memory locations. The entire word can
be read in one operation provided the first
(a) word is even
(b) word is odd
(c) memory location is odd
(d) memory address is even
9. A 3 x 8 decoder with two enable inputs is to be used to address 8 blocks of memory. What will be the
size of each memory block when addressed from a sixteen bit bus with two MSBs used to enable the
decoder
- 74 -

(a) 2K
(b) 4K
(c)16K
(d) 64K
The following . items consist of two statements, one labeled as Assertion A and the other labeled the
Reason R. You are to examine these two statements carefully and decide if the Assertion A and the
Reason R are individually true and if so, whether the Reason is a correct explanation of the Assertion.
Select your answers to these items using the codes given below and mark your answer sheet accordingly:
Codes:
(a) Both A and R are true and R is the correct explanation of A.
(b)Both A and Rare true but R is NOT a correct explanation of A.
(c) A is true but R is false
(d)A is false but R is true
10. Assertion (A): TTL and CMOS cannot be normally used together.
Reason (R) : .TTL operates on a (5 0.25) V regulated supply voltage and some mA, while the CMOS
operates on unregulated supply voltage of +3 to +15 and some microA.
11. Assertion (A): Machine language program is written in hexadecimal.
Reason (R) : Microprocessor can understand hexadecimal number system.
12.A JK flip-flop has its J input connected to logic level 1 and its K input to the Q
output. A clock pulse is fed to its clock input. The flip-flop will now
(a) change its state at each clock pulse
(b) go to state 1 and stay there
(c) go to state 0 and stay there
(d) retain its previous state
13.A decade counter requires
(a) 10 flip-flops
(b) 4 flip-flops
(c) 3 flip-flops
- 75 -

(d) 2 flip-flops.
14 The decimal value for the BCD coded number 00010010 is
(a) 6
(b) 10
(c)12
(d)18.
15. The Boolean expression (A+CD) (B+D+C)
may be simplified as
(a) AB + CB
(b)AB+C+D
(c) A+BC+D
(d) A+B+CD.
16. An adder takes. Input/s and produces. Output/s
(a) one, two
(b) two, two
(c) three, two
(d) two, three.
17.1 Increasing the precision of the REAL data type requires using at least one additional bit in
(a) the mantissa
(b) the exponent
(c) both the mantissa and the exponent
(d) none of the above.
18. Let * be the binary operation on rational numbers given
a*b=a+b+2ab. Which of following are true?
I. * is commutative
II. There is a rational number that is a*identity
- 76 -

III. Every rational number. has as a* inverse.


(a) I only
(b) II only
(c) I and II
(d) I,II and III
19..How many 1 are present in the binary
representation of 15 x 256 + 5 x 16 + 3?
(a) 8
(b) 9
(c) 10
(d)11
20. Which of the following combinations of gates does not allow the implementation
of an arbitrary Boolean function?
(a) OR gates and inverters only
(b) NAND gates only
(c) OR gates and exclusive OR gates only
(d) OR gates and NAND gates.
21.Which logic circuit is the fastest?
(a) TTL
(b) DTL
(c) RTL
(d) All have same speed.
22.A half adder has
(a) 2 inputs and 2 outputs
(b) 2 inputs and 3 outputs
(c) 3 inputs and 3 outputs
- 77 -

(d) None of the above.


23. The main advantage of flip-flops over transistor circuit is
(a) immunity from noise
(b) low heating
(c) low propagation delay time
(d) high propagation.
24. The Integrated injection Logic has higher density of integration than TTL because it
(a) does not require transistors with high current gain and hence they have smaller geometry
(b) uses bipolar transistor
(c) does not require isolation diffusion
(d) uses dynamic logic instead of static logic.
25.In a positive edge triggered JK flip-flop, a
low J and a low K produce the. state A
high J and a high K mean that the output
will .on the rising edge of the clock
(a) active. race
(b) inactive dead
(c) inactive ..toggle
(d) active ..constant
26.How many bits does one need to encode all twenty-six letters, ten symbols, and ten
numerals?
(a) 5
(b) 6
(c) 7
(d) 46
27. Consider the representation of six-bit numbers by twos complement, ones
- 78 -

complement, or by sign = and magnitude.In which representation is there overflow


from the addition of the integers 1000 and 011000 ?
(a) Twos complement only
(b) Sign and magnitude and ones complement only
(c) Twos complement and ones complement only
(d) All three representations.
28. Which of the following sets represents a universal logic family?
(a)NAND
(b)XOR
(c)NAD
(d) None of the above.
29. The maximum propagation value in case of 7400 NAND gates is
(a) 1 second
(b) 20 milli seconds
(c) less than 20 nano seconds
(d) less than 20 pico seconds.
30 . The total number of Boolean functions which can be realized with your variables
Is ?
(a) 4
(b)16
(c) 256
(d) 65,536

Year : 4th

- 79 -

Global Institute of Technology, Jaipur

Mid Term Question Papers

Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

1.

Name of the Faculty

: Bharti Sharma

2.

Designation

: Assistant Professor

3.

Department

ECE

Roll No. :

Date : ..

Global Institute of Technology


B.Tech -4th Year VII SEM, Computer Science
Ist Mid Term
Tuesday, 25-09-2012
CAD FOR VLSI DESIGN
Duration: 1:30 Hrs

Maximum Marks: 40

Attempt all the Questions. All Questions carry Equal Marks


Unit-1

1)
a) What are the circuit models? Discuss of the classification of models on the basis of levels and
views.Explain gjaski y-chart for the three view of a circuit?
8
b) Explain different microelectronics circuit design styles?

Or
a) Compare between full custom and semi custom design styles ?
8
b) Explain abstraction levels of a circuit representation and also discuss corresponding views with
the help of a circuit example?
8
Unit-2

2)
a) What is the Boolean function and also discuss its representation classified in tabular, logic
expression and BDDs.
8
b) What do you understand by circuit optimization? Explain its need and the process .
8

Or
a) Explain physical design cycle with appropriate diagram?
a) Differentiate between behavioral, structural and physical views in circuit models?
- 80 -

8
8

Unit-3

3) Write short note on


a) Global routing method
b) Clock definition and clock planning

4
4

Or
a) Power planning
a) Detailed routing

4
4

Roll No. :

Date : ..

Global Institute of Technology


B.Tech -4th Year VII SEM, Computer Science
2nd Mid Term
CAD FOR VLSI DESIGN
Duration: 1:30 Hrs

Maximum Marks: 40

Attempt all the Questions. All Questions carry Equal Marks


Unit-2

4)
5)

Consider function f= ab +bc and g=ac draw ROBDD corresponding to f xor g?8
Describe any two feature of hardware description language given one distinctions between
behavioral HDL and structure HDL?
8

Unit-3

6) Given the following netlist show two other possible representation?

M1: n1,n2,n4
M2: n2,n3,n5
M3:n3,n1,n4,n5
M4:n1,n2,n3

7) Write short note on


- 81 -

b)

Unate function

c)

Force directed scheduling

Unit-4

8)

Explain Resource sharing and resource binding ? what are compatibility and conflicts graph?
8

9) Discuss sharing and binding for resource dominated circuit (both hierarchical and nonhierarichal sequence)?

Year : 4th
Global Institute of Technology, Jaipur

Model Test Paper


Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Rajasthan Technical University


B.Tech IV Year VIII Sem, Information Technology
CAD for VLSI (Set-A)
Duration: 3Hrs

Maximum Marks: 80

Attempt all the Questions. All Questions carry Equal Marks


Unit-1
Q1 What is Moores Law? Explain various phases of creating Microelectronics chips
OR
What is the difference between FPGA and MPGA? Explain PLDs

16

Q2 Consider function f = ab + bc + ca. Find out the cofactors with respect toc, and Boolean

difference, Consensus and Smoothing, then represent the function in 3 D Boolean space
OR
Explain all the modeling styles of VHDL with the help of an Appropriate Example

- 82 -

16

Q3. Explain ASAP and ALAP Scheduling algorithm


OR
Explain Multiprocessor Scheduling algorithm in detail

16

Q4 Write the Algorithm for exact logic minimization with an example also explain unite functions
OR
Explain logic Optimization Principles with necessary Definitions

16

Q5 Explain Channel Routing Algorithm and Iterative Improvement Algorithm


OR
. Explain Integer Linear Programming model with the help of an example

16

Year : 4th
Global Institute of Technology, Jaipur

Model Test Paper


Sem : VII

(Approved by AICTE and Affiliated to RTU, Kota)

Rajasthan Technical University


B.Tech IV Year VIII Sem, Information Technology
CAD for VLSI (Set-A)

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Duration: 3Hrs

Maximum Marks: 80

Attempt all the Questions. All Questions carry Equal Marks


Unit-1
Q1 Make a Comparison Study of design styles of Microelectronic circuits
OR
Explain the various methods of representation of Boolean functions

16

Q2 Explain a process for the design system of digital system using appropriate block diagram
OR

Explain Dataflow and Sequencing graph with the help of an example

16

Q3. Explain List Scheduling Algorithm in detail


OR
Explain Force Directed Scheduling Algorithm algorithm in detail

16

Q4 Write the Algorithm for logic minimization with an example also explain unite functions

OR
Explain logic Optimization Principles with all the necessary Definitions

16

Q5.What is Circuit Extraction, explain it in context to Design Rule Checking


OR

Explain Global Routing along with the goals and objectives

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16