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I.
INTRODUCTION
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In order to obtain the gate-to-source and drainto-source switching parasitic inductances, the 3-D
inductance extraction program FastHenry was
used. FastHenry is a software program which
computes the frequency-dependent resistances and
inductances of complicated three-dimensional
packages and interconnects, assuming operating
frequencies up to the multi-gigahertz range [9].
Fig.4 shows the X-Y image of PCB traces of the
switching loops in FastHenry. Fig. 5 shows the
extracted resistances in gate-to-source and drain-tosource switching loop. Fig.5 and Fig.6 show the
extracted self-inductances in gate-to-source
switching loop and drain-to-source switching loop,
respectively. LR1 is the inductance due to the
interconnecting trace connected to the positive
terminal of the input capacitor. LDM is the total
trace inductance from the inductor or resistor load
to the SiC MOSFET socket. LDD is the trace
inductance from the SiC MOSFET socket to the
SiC Schottky diode socket which is the parasitic
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Fig.11 SiC DMOSFET simulated (dashed) and experimental
(solid) turn-on transient of resistive switching.
(a) Comparison of VDS and IDS; (b) comparison of VGS and IGS
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Fig.12 SiC DMOSFET simulated (dashed) and experimental
(solid) turn-off transient of resistive switching.
(a) Comparison of VDS and IDS; (b) comparison of VGS and IGS
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Fig.14 SiC DMOSFET simulated (dashed) and experimental
(solid) turn-on transient of inductive switching.
(a) Comparison of VDS and IDS; (b) comparison of VGS and IGS
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Fig.15 SiC DMOSFET simulated (dashed) and experimental
(solid) turn-off transient of inductive switching.
(a) Comparison of VDS and IDS; (b) comparison of VGS and IGS
V. D ISCUSSION
As mentioned before, the effects of parasitic
impedances such as parasitic inductances and
parasitic capacitances can be very significant in
high-frequency
high-efficiency
switching
converter. In order to accurately predict the
performance of the switching converter, besides the
accurate device model, it is also necessary to
extract the specific parasitic impedances in the
switching loop, including the parasitic parameters
of the semiconductor devices, IC chips, sensors,
interconnectors and PCB layout. In other words,
the factors that affect the accuracy of the prediction
include:
REFERENCES
[1]
[2]
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[5]
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[7]
[8]
[9]
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