CMOS Logic Circuit Design

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Link: CMOS

Static and Dynamic CMOS Design

Basic Considerations
Important Technical Concepts

Basic Considerations

Transfer (DC) Characteristic and Switching Point

Transient (AC) Characteristic as well as Rise-Time, Fall-Time and Delay Time
Fan-In and Fan-Out

Static CMOS-Logic

Conventional Complementary MOS Logic

Pseudo n-MOS Logic
Pass-Transistor Logic

Dynamic CMOS-Logic

Precharge-Evaluate (PE) Logic

NP Domino Logic
CMOS Domino Logic
Mattausch, CMOS Design, H20/4/25

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Meaning of Static and Dynamic CMOS Logic

Logic
Output

Noise

Noise

Noise

Static Logic

VDD
(1)

Dynamic Logic

VSS
(0)

Time

Static CMOS logic actively restores the logic output values,

while dynamic CMOS logic does not.
Mattausch, CMOS Design, H20/4/25

Advantages of Static and Dynamic CMOS Design

static design

dynamic design

- high functional reliability

- high switching speed

Important Technical Concepts

- Transfer (DC) Characteristic and

- small area consumption
Switching
Point
- low power dissipation
- unlimited
validity of
logic outputs
- easy circuit design

The most important design goals determine, whether a

static or a dynamic design technology is chosen.
Mattausch, CMOS Design, H20/4/25

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Transfer (DC) Characteristic

(Example Inverter)

Inverter Circuit

Inverter Transfer Characteristic

VOH = high output voltage
VOL = low output voltage
VIL = max. low input voltage
VIH = min. high input voltage
VIL -VSS =low noise margin
VDD - VIH = high noise margin

The transfer characteristic of CMOS logic is analog. The

region between points A and B (slope = 1) is logically invalid.
Mattausch, CMOS Design, H20/4/25

Switching Point VSP

(Example Inverter)

Switching-Point Definition

Switching-Point Condition
ID, n MOS = ID, p MOS
n

(V

VSP =

SP

VTH, n ) =
2

(VDD V

VTH ,p )

SP

n
VTH, n + (VDD VTH, p )
p
n
1+
p

p n ; VTH , p VTH, n

VDD
VSP
2

At the switching point both transistors M1 and M2 are

in the saturation region and have equal conductance.
Mattausch, CMOS Design, H20/4/25

Transfer Characteristic and Transistor-Size

(Example Inverter)
Correlation between and
MOS-transistor parameters

p- and n-MOS transistor design

influences the transfer characteristic

SP1
<<1

SP2
SP3

W
t ox L

n 3 p

p n

= carrier mobility
= gate-insulator permittivity
tox = gate-insulator thickness
W = MOS transistor width
L = MOS transistor length

Wp 3Wn

>>1

The choice of MOS-transistor length L and width W is a

major design freedom in CMOS circuit design.
Mattausch, CMOS Design, H20/4/25

Transfer Characteristic of NAND Gates

N-input NAND Gate

Switching-point N-input NAND Gate

SPN-NAND
, N-NAND

SPinv

<<1

,inv

n
VSP =

VTH ,n + (VDD VTH , p )m

N p
1+

; m = 1~2

N p

To keep the switching point of the N-input NAND gate

at about VDD/2, it is necessary to choose Wn~NWp/3.
Mattausch, CMOS Design, H20/4/25

Transfer Characteristic of NOR Gates

N-input NOR Gate

Switching-point N-input NOR Gate

,inv

Important Technical Concepts

, N-OR

>>1

SPinv

- Transient (AC) Characteristic as well as

Rise-Time, Fall-Time and Delay Time
SPN-OR

N m n
VSP =

VTH, n + (VDD VTH, p )

N mn
1+

; m = 1~2

To keep the switching point of the N-input NOR gate at

about VDD/2, it is necessary to choose Wp~3NWn.
Mattausch, CMOS Design, H20/4/25

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Rise-, Fall- and Delay-Time of Logic Circuits

Logic Gate Transient
Input and Output

Rise-, Fall- and Delay-Time

Rise-Time tr

VDD
50% (VDD/2)

Time for a transient waveform to rise from

10% to 90% of its steady state values.

Fall-Time tf
VDD

Time for a transient waveform to fall

from 90% to 10% of its steady state
values.

Delay-Time td
Time difference from the 50% transition
level of the input waveform to the 50%
transition level of the output waveform.

Rise-, fall and delay time are the main quantities for
characterizing the performance of a logic CMOS circuit.
Mattausch, CMOS Design, H20/4/25

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Simple AC Model/Equations for CMOS Logic

fall time: pull-down network

rise time: pull-up network

VDD

VDD

Important Technical Concepts

- Fan-In and Fan-Out
VSS

VSS

CL
t f = kf ;

pd,eff VDD

CL1tr = k r; t dr 2 tr
pu ,eff VDD

t df 1 t f2
t dr + tdf
t d,av

; kf and kr depend on fabrication technology (~2-4)

Pull-down, pull-up network and the load capacitance CL

determine the AC-performance of the CMOS logic circuit.
Mattausch, CMOS Design, H20/4/25

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Definition of Fan-In and Fan-Out for Logic Gates

fan-in = m

fan-out = k
1

1
2
3

m-1
m

The fan-in of a logic gate is the number of its inputs.

The fan-out of a logic gate is the number of its output
connections to other gates.
Mattausch, CMOS Design, H20/4/25

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Delay-Time Effect of Fan-In (m) and Fan-Out (k)

(Constant n-MOS and p-MOS transistor W/L-ratios, respectively)

NAND-Gate
Static CMOS-Logic

NOR-Gate

t
= m t + k t
= m (m t + kComplementary
t )
-t Conventional
MOS
(CMOS) Logic
t
= m (m t + k t
= m t n-MOS
+ k t
-t Pseudo
Logic
- Pass-Transistor Logic
df,NAND

dr,NAND

fin

rin

fex

rex

df,NOR

fin

dr,NOR

fex

rin

rex

tfin and trin are internal fall- and rise-time of a minimum sized inverter, due to its own
gate and drain capacitances, respectively.
tfex and trex are external fall- and rise-time of a minimum sized inverter, due the external
load of a minimum sized inverter with typical routing capacitance, respectively.

The fan-in has a quadratic impact on NAND-Gate fall

times as well as NOR-Gate rise times.
Mattausch, CMOS Design, H20/4/25

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Conventional Static CMOS Logic

Conventional CMOS principle
A

Pull-Up
Network

Fu (A, B,, N)

Example with fan-in equal 5

Pull-Up
Network
Z = A (E + D) + (B C) (E + D)

Fd (A, B, ,N)
= Fu (A, B,, N)
Pull-Down
Network

Pull-Down
Network
Z = A (B+ C) + (D E)

Fd (A, B, ,N)

Conventional CMOS logic is static because 1 and 0 are

restored by pull-up and pull-down network, respectively.
Mattausch, CMOS Design, H20/4/25

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Pseudo n-MOS Logic

Principle:
Use only the pull-down network.
Example with fan-in equal 5
Chose pull-up strength of p-MOS smaller
than pull-down strength of network.
A

VDD

VSS

Pull-Down
Network
Fd (A, B, ,N)

Z = A (B+ C) + (D E)

Pull-Down
Network
N

Fd (A, B, ,N)
VSS

Advantage: Less transistors and lower input capacitance.

Disadvantage: High power dissipation and low pull-up speed.
Mattausch, CMOS Design, H20/4/25

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Pass-Transistor Logic
V1

V2

Vk

P1
P2

FP =
P1 (V1 ) + P2 (V2 ) + + Pk (Vk )

Pk
Pass-Transistor Logic Gate

Any logic function FP can be constructed by controlling a set

of pass signals Pi by another set of control signals Vi.
Mattausch, CMOS Design, H20/4/25

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2-Input Pass-Transistor Gate Example

Realization Table of 2-Input Gates

Dynamic CMOS-Logic
Operation

P1

P2

P3

P4

NOR(A,B)
XOR(A,B)
NAND(A,B)
AND(A,B)
OR(A,B)

0
0
0
1
1

0
1
1
0
1

0
1
1
0
1

1
0
1
0
0

Implementation with n-MOS

and p-MOS transistors

- Precharge-Evaluate (PE) Logic

- NP Domino Logic
- CMOS
Domino
Implementation
with n-MOS
transistors Logic
(Disadvantage: Noise-margin of high level reduced by Vth,n)

The pass-transistor logic has a good implementation density,

but may have slow switching speed.
Mattausch, CMOS Design, H20/4/25

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Precharge-Evaluate (PE) Logic

Principle:
Use only the pull-down network.
clock=0: Precharge output to 1.
clock=1: Evaluate pull-down network.

Example with fan-in equal 5

VDD

Z = A (B+ C) + (D E)

Fd (A, B, ,N)
A
B

Pull-Down
Network

Pull-Down
Network
Fd (A, B, ,N)

clock
VSS

Advantage: Low power dissipation and high speed.

Disadvantage: Low reliability and difficult design.
Mattausch, CMOS Design, H20/4/25

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NP Domino Logic
Alternating cascade of PE-logic with pull-up/pull-down networks.

VDD

VDD

VDD

Pull-Up
Network
F2

A
B
Pull-Down
Network
F1

Pull-Down
Network
F3

N
clock

clock

clock
VSS

VSS

VSS

Low power and high speed, but difficult to design.

Mattausch, CMOS Design, H20/4/25

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CMOSDomino
DominoLogic
LogicCircuit
Gate
CMOS

VDD
VDD

VDD

Buffer and
high level restoring VDD
elements

Fd (A, B, ,N)

A
B

A
B
Pull-Down
Network

Fd1

clock

Pull-Down
Network

Pull-Down
Pull-Down
Network Network

Fd 3

Fd (A, B, ,N) Fd 2
clock

clock
VSS
clock

VSS

VSS

VSS

a good
of switching
ACMOS
CMOSdomino
dominologic
logicachieves
circuit uses
onlybalance
pull-down
networks.
speed, area/power consumption and design reliability.
Mattausch, CMOS Design, H20/4/25

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