LABORATORY REPORT 2

LOGIC GATE AND-OR

ECE 135

Gerfel Philip C. Gonzales

FEBRUARY, 2015

Objective: Layout a LOGIC GATE with the given specifications

Specifications:

This are the specifications given. I made the logic gate with only this specifications
but the presimulation was better than the postsimulation. Thus, the layout was not good
enough. Therefore, I made another logic gate with using 4 multiples on the inverter.
Inverter Schematic Diagram and Symbol

NOR Gate Schematic Diagram and Symbol

NAND Gate Schematic Diagram and Symbol

AND-OR Schematic Diagram

AND-OR Layout

Design Rule Check

Layout Versus Schematic

Layout Parasitic Extraction

Testbench

Waveform Result

Shown above are the waveforms output OUTPUT, input A, input B, and input C.

Truth Table
A B C
OUTPUT
0 0 0
0
0 0 1
1
0 1 0
0
0 1 1
1
1 0 0
0
1 0 1
1
1 1 0
1
1 1 1
1
Shown above is the computed truth table of the logic gate AND-OR.

From the waveform shown above and the truth table, therefore, the
finished layout of the logic gate AND-OR is correct.

Comparison

Postsimulation

Presimulation

Shown above is are the waveforms of the presimulation and postsimulation. Also,
the rise time and fall time are measured. The postsimulation has lesser rise time and fall
time than the presimulation. Thus, clearly, the layout is better than the rf018l.
Zoomed on the Rising Edge

PRESIMULATION

POSTSIMULATION

RISE TIME

10.4 ns

3.77 ns

FALL TIME

4.46 ns

4 ns

SLEW RATE RISE

TIME

SW =

1.8V
( 10.4 ns ) ( 1 x 106 )

173.08V /s
SLEW RATE
FALL TIME

SW =

1.8 V
( 4.46 ns ) ( 1 x 10 6 )

403.59 V / s

SW =

1.8V
( 3.77 ns ) ( 1 x 106 )

477.45 V / s
SW =

1.8 V
( 4 ns ) ( 1 x 106 )

450.00 V / s

Conclusion
The specification that was assigned has 1 multipliers. I made the logic gate with
only this specifications but the presimulation was better than the postsimulation indicating
that the layout was not good. Therefore, I made another logic gate using 4 multiples on
the inverter. The result was astonisihing. Postsimulation got better.
The performace of a logic gate is measured by the slew rate or the rise time and fall
time of the signal output. The greater the slew rate, the better the device. Slew rate is the
maximum rate of change of the output amplitude per unit time. The lessser the rise time
or fall time, the better the device.
As shown in the table of comparison above, clearly, the postsimulation of the logic
gate has greater slew rate than the presimulation. Also, the rise time and fall time of the
postsimulation are lesser than the presimulation. Therefore, with the data gathered, the
postsimulation or the layouted logic AND-OR Gate is better than the presimulation.
I also made another conclusion, the more the multiplier, the better is the transistor.