Professional Documents
Culture Documents
An SR Latch
S
Q
R = Reset, S= Set
Comment
1/0
0/1
Set state
Reset state
Illegal inputs
A clocked D-latch
Clock C
Q
Q (not Q)
D-latch
C
Master-Slave D flip-flop
D
Clock
D-latch
D-latch
Clock
Clock pulse
Abstract view
Register
A 8-bit register is an array of 8 D-flip-flops.
Data input
D- F/F
D-F/F
D-F/F
Q
D-F/F
Q
write
Data out
Binary counter
Counts 0, 1, 2, 3,
D
D-F/F
C
write
a modulo-2 counter
D3
D2
D1
D0
Q3
Q2
Q1
Q0
A 4-bit counter
(mod-16 counter)
4-bit adder
14
13
A shift register
D
D- F/F
D-F/F
Shift (right)
D-F/F
Q
D-F/F
Q
Hardware Multiplication
Multiplicand
Multiplier
Product
D- F/F
D-F/F
D-F/F
Q
D-F/F
Q
Shift (right)
With each clock pulse on the shift line, data moves one
place to the right.
Executing r1:= r2
How to implement a simple register transfer r1:= r2?
R2
32-bit reg
32
Write
R1
Clock
32-bit reg
Executing r1:= r1 + r2
R2
32-bit reg
32
32-bit
Adder
SUM
32
32
CLOCK
R1
32-bit reg
Write
A Hardware Multiplier
Occupies the
right half
Shift left
Multiplicand
0
64-bit reg
64
64-bit
ALU
Add
Right shift
Multiplier
LSB
Initially 0
64
64
Product
64-bit reg
Control
Write
Division
The restoring division algorithm follows the simple
idea from the elementary school days. It involves
subtraction and shift. Here is an implementation by
hardware
Shift right
Divisor
0s
64-bit
64
64-bit
ALU
64
Subtract/Add
Quotient
Left
Shift
64
Dividend / Remainder
64-bit
Control
Write