ARM9

The ARM9 is a group of 32-bit RISC ARM processor Switching to a Harvard architecture entailed a non-unied
cores licensed by ARM Holdings.
cache, so that instruction fetches do not evict data (and
vice versa). ARM9 cores have separate data and address
bus signals, which chip designers use in various ways. In
most cases they connect at least part of the address space
1 Overview
in von Neumann style, used for both instructions and data,
usually to an AHB interconnect connecting to a DRAM
With this design generation, ARM moved from a von interface and an External Bus Interface usable with NOR
Neumann architecture (Princeton architecture) to a ash memory. Such hybrids are no longer pure Harvard
Harvard architecture with separate instruction and data architecture processors.
buses (and caches), signicantly increasing its potential
speed. Most silicon chips integrating these cores will
package them as modied Harvard architecture chips,
combining the two address buses on the other side of sep- 2 Cores
arated CPU caches and tightly coupled memories.
There are two subfamilies, implementing dierent ARM The ARM MPCore family of multicore processors
support software written using either the asymmetric
architecture versions.
(AMP) or symmetric (SMP) multiprocessor programming paradigms. For AMP development, each central
processor unit within the MPCore may be viewed as an
1.1 Dierences from ARM7 cores
independent processor and as such can follow traditional
[2]
Key improvements over ARM7 cores, enabled by spend- single processor development strategies.
ing more transistors, include:[1]
Decreased heat production and lower overheating 2.1 ARM9TDMI
risk.
ARM9TDMI is a successor to the popular ARM7TDMI
Clock frequency improvements. Shifting from a core, and is also based on the ARMv4T architecture.
three-stage pipeline to a ve-stage one lets the clock Cores based on it support both 32-bit ARM and 16-bit
speed be approximately doubled, on the same sili- Thumb instruction sets and include:
con fabrication process.
ARM920T with 16 KB each of I/D cache and an
MMU

Cycle count improvements. Many unmodied

ARM7 binaries were measured as taking about 30%
fewer cycles to execute on ARM9 cores. Key improvements include:

ARM922T with 8 KB each of I/D cache and an

MMU

Faster loads and stores; many instructions now

cost just one cycle. This is helped by both the
modied Harvard architecture (reducing bus
and cache contention) and the new pipeline
stages.

ARM940T with cache and a Memory Protection

Unit (MPU)

2.2 ARM9E

Exposing pipeline interlocks, enabling compiler optimizations to reduce blockage be- ARM9E, and its ARM9EJ sibling, implement the batween stages.
sic ARM9TDMI pipeline, but add support for the
ARMv5TE architecture, which includes some DSPAdditionally, some ARM9 cores incorporate Enhanced esque instruction set extensions. In addition, the multiDSP instructions, such as a multiply-accumulate, to sup- plier unit width has been doubled, halving the time report more ecient implementations of digital signal pro- quired for most multiplication operations. They support
cessing algorithms.
32-bit, 16-bit, and sometimes 8-bit instruction sets.
1

5
ARM926EJ-S with ARM Jazelle technology, which
enables the direct execution of 8-bit Java bytecode
in hardware, and an MMU
ARM946
ARM966
ARM968

Chips

NXP Semiconductors
LPC2900, LH7A

DOCUMENTATION

LPC3200,

LPC3100,

Freescale Semiconductor i.MX1x and i.MX2x

Marvell Kirkwood
Qualcomm Atheros AR6400
Samsung S3C24xx
STMicroelectronics STR9 series,[3] Nomadik
Texas Instruments OMAP 1
Texas Instruments Sitara AM1x
Via WonderMedia 8505 and 8650
MediaTek MT6516, MT6573
Zilog Encore! 32

4 Products
5 Documentation
Nintendo DSi has a chip with an ARM9 and ARM7 cores

The amount of documentation for all ARM chips is

daunting, especially for newcomers. The documentation
for microcontrollers from past decades would easily be
inclusive in a single document, but as chips have evolved
so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since
it consists of documents from the IC manufacturer and
documents from CPU core vendor (ARM Holdings).
A typical top-down documentation tree is: high-level
marketing slides, datasheet for the exact physical chip,
a detailed reference manual that describes common peripherals and other aspects of physical chips within the
same series, reference manual for the exact ARM core
processor within the chip, reference manual for the ARM
architecture of the core which includes detailed description of all instruction sets.

Lego Mindstorms EV3 brick has an ARM9 TI Sitara AM1x

Documentation tree (top to bottom)

This list is incomplete; you can help by
expanding it.

1. IC manufacturer marketing slides.

2. IC manufacturer datasheets.

Atmel AT91SAM9, AT91CAP9

3. IC manufacturer reference manuals.

CSR Quatro 4300

4. ARM core reference manuals.

Cypress Semiconductor EZ-USB FX3

5. ARM architecture reference manuals.

Digi NS9215, NS9210

IC manufacturer has additional documents, including:

Nintendo NTR-CPU (Nintendo DS CPU), TWL- evaluation board user manuals, application notes, getting
CPU (Nintendo DSi CPU; same as the DS but started with development software, software library docclocked at 132 MHz instead of 66 MHz)
uments, errata, and more.

See also
ARM architecture, List of ARM microprocessor
cores
Microcontroller, List of common microcontrollers
Embedded system, Single-board microcontroller
Interrupt, Interrupt handler, List of real-time operating systems
JTAG

References

[1] Performance of the ARM9TDMI and ARM9E-S cores

compared to the ARM7TDMI core, Issue 1.0, dated 9
February 2000, ARM Ltd.
[2] MPCore Sample Code
[3] STR9 Website; STMicroelectronics.
[4]
[5] VTech V.Flash product page from ARM
[6] http://zyxel.nas-central.org/wiki/Category:NSA-310
[7] http://zyxel.nas-central.org/wiki/Category:NSA-320

External links

ARM Holdings
Ocial website
Quick Reference Cards
Instructions: Thumb (1), ARM and Thumb-2 (2),
Vector Floating Point (3)
Opcodes: Thumb (1, 2), ARM (3, 4), GNU Assembler Directives 5.
Yurichev, Dennis, An Introduction To Reverse Engineering for Beginners including ARM assembly. Online book: http://yurichev.com/writings/
RE_for_beginners-en.pdf

9 TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES

Text and image sources, contributors, and licenses

9.1

Text

ARM9 Source: http://en.wikipedia.org/wiki/ARM9?oldid=644974581 Contributors: David spector, Nixdorf, Ds13, Ferdinand Pienaar,
Abdull, Imroy, Acb, LudovicPerrine, Gantry, Unixxx, WadeSimMiser, Arunib, Gavinatkinson, King of Hearts, YurikBot, Meira, Rykotsusei, SmackBot, Frap, JonHarder, Flibble, Saxbryn, Blakegripling ph, Kunkunuzzi, Paul Foxworthy, Josemi, BetacommandBot, Thijs!bot,
Nick Number, Nisselua, CPMartin, Jhsounds, Dougher, BJ Axel, Mike Kao, Belamp, Cvf-ps, CultureDrone, Nn123645, Lockalbot, Addbot, Mortense, Rutepoint, Dupondt, Yobot, Sjoos, SassoBot, FrescoBot, Brian the Editor, Mikzat, Tanzen90, ZroBot, Sbmeirow, Mannermagmaneben, Everlasting enigma, Mikhail Ryazanov, Wbm1058, KJClayton, ChrisGualtieri, Cognoscent, Lagoset, Sephirothkefka and
Anonymous: 77

9.2

Images

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2.5 Contributors: Originally from the English Wikipedia; description page is/was here. Original artist: The Opte Project
File:Lego_Mindstorms_EV3_brick.jpg Source: http://upload.wikimedia.org/wikipedia/commons/f/fd/Lego_Mindstorms_EV3_brick.
jpg License: CC BY-SA 3.0 Contributors: Own work Original artist: Klaus-Dieter Keller
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9.3

Content license

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