Sequence Detector with 8-Bit Data Input

Laboratory Activity #2
EE 278
FIELD PROGRAMMABLE GATE ARRAYS

by
Rovil S. Berido
Master of Science in Electrical Engineering
Iligan Institute of Technology of the Mindanao State University
January 20, 2014

DESIGN

The sequence detector for this lab activity receives as input a sequence of data. In this
design, each input is an 8-bit data The detector outputs a 1 whenever it detects the
sequence which is prespecified in the design. Note that, there are two types of
sequence detector: the overlap and non-overlap. In the first type, the final bits of one
sequence can be the start of the next sequence. This is not the case for the non-overlap
where the next sequence cannot start from the final bits of the first sequence.

The sequence for the design is 33-33-33-ff-11 (in hexadecimal notation). In this case,
it is not important to specify whether overlap or non-overlap sequence detector will be
used. In the first place, no overlapping event will take place since the sequence 33-3333-ff-11 that will be used in the design is not composed of repeating two or more data
wide frames. Overlapping takes place whenever a repeating two or more data wide
frame sequence is used. For example, the sequence 33-ff-33-ff , 33-ff-33-ff-11 and
33-ff-22-33-ff-22 have the possibility of the final bits of its first sequence be the start
bits of its second sequence.

To start the design with, the state diagram is derived as well as the state table. As
specified, the sequence is composed of five(5) 8-bit data. Hence a minimum of five
(5) states is neeeded for the state of the design. Since, a synchronous, active high reset
was included, an additional state for this reset was added a. All in all, six states were
used namely: idle, state1, state2, state3, state4, state4 and state5. The state idle is the
initial state. The state diagram is drawn below. On violet arrows are the transition
details for the expected sequence while the blue arrows are the details for inputs that
break the sequence.

Below

is

the
discussion
which
details the
handling
of

the

expected
sequence
as will as in handling the inputs that breaks the sequence.

IDLE

State Idle is the initial state. It waits for a data input of 33. In the case

that it does not receive a 33, the machine remains in the same state until

it finally

receives a 33.
STATE1 State State1 is the next state It waits for a another data input of 33.
the case that it does not receive a 33, the machine goes back to the

In
idle state.

STATE2 State State2 is the next state It waits for yet another data input of 33.
case that it does not receive a 33, the machine goes back to the

In

the

idle state.

STATE3 State State3 is the next state It waits for a data input of ff. It it fails to
receive an ff and receives a 33 instead, it remains in the same state. It
in this state as long as the input is 33. If it receives an input

remains
which is neither

ff nor 33, it goes back to the idle state.

STATE4 State State4 is the next state It waits for a data input of 11. In the case

that

it does not receive a 11, the machine goes back to the idle state.
STATE5 State State5 is the next state It waits for another data input before
proceeding to the next state. If it receives a 33, it immediately proceeds
state1. Otherwise, it returns to its idle state.

to

The state table below summarizes the above discussion: On yellow highlights, are the events that
make the sequence.

Present State

Idle
State1
State2
State3
State4
State5

INPUT=33

Next State/Output
INPUT=FF
INPUT=11

Other

State1/0
State2/0
State3/0
State3/0
Idle0
State1/1

Idle/0
Idle/0
Idle/0
State4/0
Idle/0
Idle/1

Specified
Idle/0
Idle/0
Idle/0
Idle/0
Idle/0
Idle/1

Idle0
Idle0
Idle0
Idle0
State5/0
Idle/1

than

The next process is assigning an n-bit number (state vector) to each state. The design used one-hot
encoding and each of the states were given the state vector as below.

The code for the implementation of the state transition above is shown below:

The code for the implementation of the output for each state is shown below:

The state is updated ever

positive edge of the clock
cycle as shown below:

TESTBENCH
The design was simulated by coding and running a testbench and then simulating the
result using Modelsim-Altera. The clock has a period of 4 unit time. The data input is
saved in a file data.txt and read through readmemh function. It is stored in 500element array which are 8-bit wide each. The data input is updated every positive
edge of the clock. The testbench code is shown below.

RESULTS