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8086/88DeviceSpecifications

8086/88DeviceSpecifications
BotharepackagedinDIP(DualInLinePackages).
8086:16bitmicroprocessorwitha16bitdatabus
8088:16bitmicroprocessorwithan8bitdatabus.

Bothare5Vparts:
8086:Drawsamaximumsupplycurrentof360mA.
8086:Drawsamaximumsupplycurrentof340mA.
80C86/80C88:CMOSversiondraws10mAwithtempspec40to
225degF.

Input/Outputcurrentlevels:

Yieldsa350mVnoiseimmunityforlogic0(Output
maxcanbeashighas450mVwhileinputmaxcan
benohigherthan800mV).
Thislimitstheloadingontheoutputs.
8086/88Pinout

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8086/88Pinout
Pinfunctions:
AD15AD0
Multiplexedaddress(ALE=1)/databus(ALE=0).
A19/S6A16/S3(multiplexed)
Highorder4bitsofthe20bitaddressORstatus
bitsS6S3.
M/IO
IndicatesifaddressisaMemoryorIOaddress.
RD
When0,databusisdrivenbymemoryoranI/O
device.
WR
Microprocessorisdrivingdatabustomemoryor
anI/Odevice.When0,databuscontainsvalid
data.
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ALE(Addresslatchenable)

When1,addressdatabuscontainsamemoryor
I/Oaddress.
DT/R(DataTransmit/Receive)
Databusistransmitting/receivingdata.
DEN(DatabusEnable)
Activatesexternaldatabusbuffers.
8086/88Pinout
Pinfunctions:
S7,S6,S5,S4,S3,S2,S1,S0
S7:Logic1,S6:Logic0.
S5:IndicatesconditionofIFflagbits.
S4S3:Indicatewhichsegmentisaccessedduring
currentbuscycle:

S2,S1,S0:Indicatefunctionofcurrentbuscycle
(decodedby8288).

8086/88Pinout
Pinfunctions:
http://www.ece.unm.edu/~jimp/310/slides/8086_chipset.html

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INTR

When1andIF=1,microprocessorpreparesto
serviceinterrupt.INTAbecomesactiveafter
currentinstructioncompletes.
INTA

InterruptAcknowledgegeneratedbythe
microprocessorinresponsetoINTR.Causesthe
interruptvectortobeputontothedatabus.
NMI

Nonmaskableinterrupt.SimilartoINTRexceptIF
flagbitisnotconsultedandinterruptisvector2.

CLK

Clockinputmusthaveadutycycleof33%(high
for1/3andlowfor2/3s)
VCC/GND

Powersupply(5V)andGND(0V).
8086/88Pinout
Pinfunctions:
MN/MX

Selectminimum(5V)ormaximummode(0V)of
operation.
BHE

BusHighEnable.Enablesthemostsignificant
databusbits(D15D8)duringareadorwrite
operation.

READY

Usedtoinsertwaitstates(controlledbymemory
andIOforreads/writes)intothemicroprocessor.
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8086/88DeviceSpecifications

RESET

Microprocessorresetsifthispinisheldhighfor4
clockperiods.
InstructionexecutionbeginsatFFFF0HandIF
flagiscleared.

TEST

AninputthatistestedbytheWAITinstruction.
Commonlyconnectedtothe8087coprocessor.
8086/88Pinout
Pinfunctions:
HOLD
Requestsadirectmemoryaccess(DMA).When1,
microprocessorstopsandplacesaddress,data
andcontrolbusinhighimpedancestate.
HLDA(HoldAcknowledge)
Indicatesthatthemicroprocessorhasenteredthe
holdstate.
RO/GT1andRO/GT0
Request/grantpinsrequest/grantdirectmemory
accesses(DMA)duringmaximummodeoperation.

LOCK

Lockoutputisusedtolockperipheralsoffthe
system.ActivatedbyusingtheLOCK:prefixon
anyinstruction.
QS1andQS0

Thequeuestatusbitsshowstatusofinternal
instructionqueue.Providedforaccessbythe
numericcoprocessor(8087).
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8086/88DeviceSpecifications

8284AClockGenerator
Basicfunctions:
Clockgeneration.
RESETsynchronization.
READYsynchronization.
Peripheralclocksignal.

Connectionofthe8284andthe8086.

8284AClockGenerator

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8284AClockGenerator
Clockgeneration:
CrystalisconnectedtoX1andX2.
XTALOSCgeneratessquarewavesignalat
crystal'sfrequencywhichfeeds:
Aninvertingbuffer(outputOSC)whichisusedtodrivetheEFI
inputofother8284As.
2to1MUX
F/CselectsXTALorEFIexternalinput.

TheMUXdrivesadivideby3counter(15MHzto
5MHz).
Thisdrives:
TheREADYflipflop(READYsynchronization).
Aseconddivideby2counter(2.5MHzclkforperipheral
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components).
TheRESETflipflop.
CLKwhichdrivesthe8086CLKinput.
8284AClockGenerator
RESET:
Negativeedgetriggeredflipflopappliesthe
RESETsignaltothe8086onthefallingedge.
The8086samplestheRESETpinontherising
edge.

CorrectresettimingrequiresthattheRESETinput
tothemicroprocessorbecomesalogic1NO
LATERthan4clocksafterpowerupandstayhigh
foratleast50us.
BUSBufferingandLatching
DemultiplexingtheBuses:
Computersystemshavethreebuses:
Address
Data
Control
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TheAddressandDatabusaremultiplexed
(shared)duetopinlimitationsonthe8086.
TheALEpincontrolsasetoflatches.

AllsignalsMUSTbebuffered.
LatchesbufferforA0A15.
ControlandA16A19+BHEare
bufferedseparately.
Databusbuffersmustbebidirectional
buffers(BB).

BHE:Selectsthehighordermemorybank.
BUSBufferingandLatching

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8086/88DeviceSpecifications

BUSTiming
Writing:
Dumpaddressonaddressbus.
Dumpdataondatabus.
Issueawrite(WR)andsetM/IOto1.

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BUSTiming
Reading:
Dumpaddressonaddressbus.
Issuearead(RD)andsetM/IOto1.
Waitformemoryaccesscycle.

BUSTiming
BusTiming:
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BUSTiming
DuringT1:
TheaddressisplacedontheAddress/Databus.
ControlsignalsM/IO,ALEandDT/RspecifymemoryorI/O,
latchtheaddressontotheaddressbusandsetthedirectionof
datatransferondatabus.
DuringT2:
8086issuestheRDorWRsignal,DEN,and,forawrite,thedata.
DENenablesthememoryorI/Odeviceto
receivethedataforwritesandthe8086to
receivethedataforreads.
DuringT3:
Thiscycleisprovidedtoallowmemorytoaccessdata.
READYissampledattheendofT2.
Iflow,T3becomesawaitstate.
Otherwise,thedatabusissampledatthe
endofT3.
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DuringT4:
Allbussignalsaredeactivated,inpreparationfornextbuscycle.
Dataissampledforreads,writesoccurforwrites.
BUSTiming
Timing:
EachBUSCYCLEonthe8086equalsfoursystem
clockingperiods(Tstates).
Theclockrateis5MHz,thereforeoneBusCycle
is800ns.
Thetransferrateis1.25MHz.

Memoryspecs(memoryaccesstime)mustmatch
constraintsofsystemtiming.

Forexample,bustimingforareadoperation
showsalmost600nsareneededtoreaddata.
However,memorymustaccessfasterdue
tosetuptimes,e.g.Addresssetupanddata
setup.
Thissubtractsoffabout150ns.
Therefore,memorymustaccessinatleast
450nsminusanother3040nsguardband
forbuffersanddecoders.

420nsDRAMrequiredforthe8086.
BUSTiming
READY:
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Aninputtothe8086thatcauseswaitstatesfor
slowermemoryandI/Ocomponents.
Awaitstate(TW)isanextraclockperiod
insertedbetweenT2andT3tolengthenthebus
cycle.
Forexample,thisextendsa460nsbus
cycle(at5MHzclock)to660ns.

Textdiscussesroleof8284Aandtiming
requirementsforthe8086.
MINandMAXMode
ControlledthroughtheMN/MXpin.
Minimummodeischeapersinceallcontrolsignalsformemory
andI/Oaregeneratedbythemicroprocessor.
Maximummodeisdesignedtobeusedwhenacoprocessor
(8087)existsinthesystem.

Someofthecontrolsignalsmustbegeneratedexternally,
duetoredefinitionofcertaincontrolpinsonthe8086.
Thefollowingpinsarelostwhenthe8086operates
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inMaximummode.
ALE
WR
IO/M
DT/R
DEN
INTA

Thisrequiresanexternalbuscontroller:The8288Bus
Controller.
8288BusController

SeparatesignalsareusedforI/O(IORCandIOWC)and
memory(MRDCandMWTC).
Alsoprovidedareadvancedmemory(AIOWC)andI/O(
AIOWC)writestrobesplusINTA.
MAXMode8086System

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