ARTICLE IN PRESS

Microelectronics Journal 41 (2010) 9398

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

A novel spread-spectrum clock generator for suppressing conducted EMI in

switching power supply
Haiyan Guo a,b,, Haizhou Wu a, Bo Zhang a, Zhaoji Li a
a
b

State Key Laboratory of Electronic Thin Films and Integrated devices, University of Electronic Science and Technology of China, Chengdu 610054, China
Information Engineering School, Southwest University of Science and Technology, Mianyang 621000, China

a r t i c l e in fo

abstract

Article history:
Received 31 May 2009
Received in revised form
11 December 2009
Accepted 16 December 2009
Available online 18 January 2010

In this paper, a novel spread spectrum clock generator (SSCG) which spreads spectrum with variable
current is presented. The proposed SSCG circuit not only occupies a small area but also minimizes effect
caused by leakage current. The proposed SSCG circuit has been fabricated in a 0.5 mm BCD process and
applied to a y-back converter. The effectiveness of the proposed SSCG circuit in terms of peak EMI
reduction is demonstrated theoretically and conrmed with experimental results.
& 2009 Elsevier Ltd. All rights reserved.

Keywords:
Spread spectrum clock generator (SSCG)
Switching power supply
EMI suppressing
Spread-spectrum frequency modulation
(SSFM)

1. Introduction
Each switching power supply typically relies on an oscillator
switching at a xed switching frequency which results in
increasingly outstanding EMI problems. In the last 10 years,
many schemes for suppressing EMI are proposed, such as adding a
decouple capacitance [1], slew-rate control technique [2], reducing package inductance [3], applying robust input [4,5], substrate
isolation [6], spread spectrum clocking [7] and so on. Among these
techniques, the spread spectrum technique can omit extra noise
ltering components associated with the EMI lter. It reduces
peak powers of harmonics to reduce peak EMI effectively.
In most available literatures, the spread spectrum clock
generator is realized by a phase-locked loop (PLL) or combining
multiphase outputs of clock source and special digital processing
circuits to achieve spread spectrum function [8,9]. Reference [10]
puts forward a jittering control circuit with variable current, but it
is in structure-level. In this paper, a spread spectrum clock
generator is realized by adding four switches and four current
mirror branches into a conventional clock generator to accomplish spread spectrum function. The proposed SSCG circuit has
been fabricated in a 0.5 mm BCD process and applied to a y-back
converter in which the SSCG circuit occupies an area of

 Corresponding author at: State Key Laboratory of Electronic Thin Films and
Integrated devices, University of Electronic Science and Technology of China,
Chengdu 610054, China.
E-mail address: guohy5@sina.com (H. Guo).

0026-2692/$ - see front matter & 2009 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mejo.2009.12.012

0.23  0.14 mm2. Furthermore, because the leakage current can

act as a fraction of supplemental current, this proposed SSCG
circuit minimizes effect caused by leakage current.

2. Circuit design and analysis

2.1. Whole circuit structure analysis
The proposed oscillator with a SSCG circuit mainly consists of
three parts: a conventional oscillator circuit, a variable current
generating circuit and a counter circuit. In Fig. 1, the counter is
clocked by the output of oscillator while outputs of the counter
control switches which connect the supplemental current
sources. The capacitance charging current consists of a main
current Imain and four binary weighted secondary current I1, I2, I3
and I4, that is I4 =2I3 = 4I2 = 8I1, among which the largest secondary
current is less than 1/10th of Imain. Different outputs of counter
decide different switch statuses, so that the intensity of
capacitance charging current changes with outputs of counter.
As a result, the variable capacitance charging current spreads
frequency within a narrow range to reduce peak EMI by spreading
the energy over a wider frequency. So the peak EMI measured by
the EMI measurement equipment is reduced. Fig. 1 is the block
diagram of the proposed SSCG while Fig. 2 shows transistor-level
realization of the proposed SSCG.
In Fig. 2, the ratio of I1, I2, I3 and I4 is 1:2:4:8 which results in
same ratio of frequency deviation by turning on I1, I2, I3 and I4,

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H. Guo et al. / Microelectronics Journal 41 (2010) 9398

VCC

Variable current generating circuit

Imain

Vref1

I1

I2

VCC

VCC

MP2

IN2

I3

VCC

I4

VCC

COM_1
EN1
INV3

INV1 IN1

MP1
Vcc

VC0

D 1 D 2 D3 D 4

EN2

Vref2

CLK

C0

COM_2

MN1
INV2

MN2

Vss

Fig. 1. Block diagram of the proposed SSCG.

Vcc
MP13 MP12
X15

MP17

Y10
VCC

MP18

Vref1
MP20

Imain

VCC
MP14

IN2(EN2)
Vcp

IN1(EN1)

MP22

VCC

MP23 VCo

MP9

MP10

I1
MP3

I2

I3
I4
MP4 MP5 MP6
VCC
VCC
VCC
VCC

INV1
VCC

IN1
MN7

MP1

MP2

Vco
Co

MN5 MN6

MP8

INV3

MP21

Vref2

MP7

MP15

MP16

MP19

MP11

MN4 MN3
Vss

MN1 MN2

IN2
INV2 D1 D2 D3 D4
counter
CLK

Fig. 2. Transistor-level realization of the proposed SSCG.

respectively. The working frequency of this switching power

supply is 132 kHz while the maximal frequency deviation is
15 kHz, hence turning on I1, I2, I3 and I4, respectively, will lead to
frequency deviation 1, 2, 4, and 8 kHz. A combination state of D1,
D2, D3 and D4 is corresponding to an output frequency. The output
frequency of oscillator varies with increasing the state D1D4, of
within 16 clock cycles, after that the process will repeat itself. In
this design, the output frequency versus time is shown in Fig. 3.

2.2. The oscillator circuit discussions

In Fig. 1, Vref1 and Vref2 are reference voltages. Assuming
Vref1>Vref2, EN1 and EN2 are enabling ports of two comparators,

respectively, which work effectively on low level. MP1, MP2, MN1,

MN2 and C0 compose the charge/discharge circuit. IN1 and IN2 is
a pair of reversed control signals. Assuming the initial status of
VC0 is low, IN1 is low too. EN1 is low while EN2 is high. At this
time, comparator 1 works while comparator 2 is suspended. MP1
is closed while MP2, MN1, MN2 are open. The current charges the
capacitance through MP1 until VC0 4Vref1when IN1 ips. EN1 is
turnover so that comparator 1 is disabled while comparator 2
works. As a result, MP1 is open while MP2, MN1, MN2 are closed.
The capacitance is discharged through MN1 until VC0 oVref2 when
IN1 changes back to low again. This process swings back and forth
so that capacitance C0 generates triangular wave while the output
of oscillator is rectangular wave. Assuming MP1 and MP2 have the
same width and length ratio, and ((W/L)MN1)/((W/L)MN2)= k, so the

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H. Guo et al. / Microelectronics Journal 41 (2010) 9398

95

Fig. 3. The output frequency of oscillator versus time.

capacitance charge/discharge currents are obtained as follow:

Icharge Itail

In this design, mf can be expressed as

1
mf

Idischarge Itail k

where
Itail Imain

4
X

D i Ii

Dfc
fm

2N
1 2Imain =

tup

vref1 vref2 C0
Itail

tdown

vref1 vref2 C0
kItail

1
Itail k

tup tdown
vref1 vref2  C0  1 k

fc

4
P

Ii
fmax fmin
k
i1

2
2k 1 C0 Vref1 Vref2

4
P
Ii
fmax fmin
k
i1

Dfc
2
2k 1 C0 Vref1 Vref2

fm

fc
N

P
2Imain 4i 1 Ii
k 1 C0 Vref1 Vref2

k
N1

10

Formula (9) indicates that large N and high deviation Dfc

should be chosen in terms of EMI suppressing, but large N leads to
high cost, so a balance point should be chosen in circuit design
and it is obvious that high deviation may penalize output ripple of
SMPS, which can be solved by using a combination of interleaving
and SSFM to multiply the frequency of a group of parallel
converters.

where tup is charge time, tdown is discharge time, f represents

oscillator output frequency.
In this design, the switch is realized by PMOS, so when D1, D2,
D3, D4 are all low, four secondary current branches are all turned
on while the output frequency of oscillator reaches maximum and
vice versa. Therefore in this circuit fc and Dfc can be expressed as
2Imain

i 1 Ii

where N represents stage number of D triggers in the counter; fm

is the frequency of modulating prole, in this design, which is
given as

i1

Di represents output signal of the counter, the value of which is

zero or one. Icharge is denoted as charge current while Idischarge
represents discharge current
Assuming Vref1>Vref2

P4

Modulation index mf whose denition is given by mf = Dfc/fm is

also a very important parameter to describe characteristics of the
modulated signal in modulation theory.

2.3. The counter circuit design and analysis

In this design, the counter in Fig. 1 is a 7-bit counter. The gatelevel realization of each stage is shown in Fig. 4(a). It consists of
four transmission gates, two nand gates and two inverters. The
CKB and CK is a pair of reversed input ports. Q and QB is a pair of
complementary outputs. RB is an enabling port. When RB is 0,
output port Q is reset to 1, otherwise the counter works normally.
Under normal working condition, assuming the initial status of Q
is 1, when CK is 0, transmission gates T1 and T2 are closed while
T3 and T4 are open. At this moment, Q remains 1. In case of CK
ipping to 1, T1 and T2 are disconnected while T3 and T4 are
connected therefore Q converts to 0. When the initial status of Q is
0, using same reasoning method, same turnover trend will be
obtained. In a conclusion, this circuit realizes two divided
frequency. Fig. 4(b) shows transistor-level realization of each
stage.

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H. Guo et al. / Microelectronics Journal 41 (2010) 9398

CKB

T4

CK

CK

T1
CKB

CK
T2

NAND1

CKB

INVI
Q

INV2

NAND2

QB

RB
T3

CKB

CK
CK
CKB

QB

Vcc
Vsst

Vcc

Vcc
Vss

Vss

Vss
RB
CK
CKB

Vss

Vss

Vss

Vss
Fig. 4. The realization of each stage of the counter: (a) gate level circuit of each stage of the counter and (b) transistor level realization of each stage of the counter.

Fig. 5. The microphotograph of oscillator.

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H. Guo et al. / Microelectronics Journal 41 (2010) 9398

3. Application and measurement

The experiment is set up in Fig. 6. The input voltage is 220 V

while the output voltage is 5 V. The proposed SSCG circuit was
embedded into IC which is used in an AC-to-DC y-back switching
converter. This chip consists of reference source, regulator,
current limit state machine, current limit comparator, autostarting count circuit, enabling inspection, over voltage and under
voltage protection circuit, oscillator and so on. To reduce the peak
EMI, the proposed SSCG circuit is embedded into oscillator whose
working frequency is 132 kHz while maximal frequency deviation
is 15 kHz.
The oscillator output wave is simulated by Hspice just as Fig. 7
and the spectrum magnitude comparison with and without SSFM
circuit is shown in Fig. 8. Fig. 7 shows oscillator output frequency
is changed within a narrow range and the proposed SSCG circuit
works normally. Fig. 8 indicates that energies of harmonics are

The proposed circuit has been fabricated in a 0.5 mm BCD

process. The layout of oscillator is shown in Fig. 5. The area of
whole oscillator chip is 1.1  0.51 mm2 while the proposed SSCG
circuit occupies an area of 0.23  0.14 mm2 which is more
compact than many other spread spectrum circuits. Because the
charge/discharge circuit in this oscillator is differential pair
transistor structure, P1 and P2 must be accurately matched to
reduce the effect from substrate noises. In Fig. 5, P1 and P2 are
broken into two sections which are both in ABBA arrangement.
Dummy cell is used at two terminals of PMOS for guarding all
PMOS having same process environment. In this layout, P channel
stopping ring is put outside PMOS differential pair transistors to
decrease the disturbance from digital units.

RF1
8.6O
DR1
11N4005

0.1uF

H
33uH

D
22mH

AC Input
220V

97

C1

DC
C2
100uF/30V Output

Cout
LTV817

D1
IC

510O
100O

C 0.1uF

10KO

0.1uF
TL431

Fig. 6. The control chip is applied to y-back switching converter.

Fig. 7. Oscillator output wave when t = 251 Vcc = 5.85 by simulation.

Fig. 8. The contrast spectrum amplitude with and without SSFM circuit by simulation.

10KO

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H. Guo et al. / Microelectronics Journal 41 (2010) 9398

frequencies after using the proposed SSCG. Based on the law of

conservation of energy, the total energy is constant so the spread
spectrum scheme has a wider spectrum and lower peak EMI. By
changing the oscillator frequency back and forth, the peak EMI
measured by the EMI measurement equipment is reduced
considerably. The experiment results show the proposed SSCG
circuit works effectively.

4. Conclusions

Fig. 9. Switching voltage output wave by measurement.

In this paper, a kind of spread spectrum clock generator (SSCG)

which spreads frequency with variable current is presented and
has been fabricated in 0.5 mm BCD process. Only four switches and
four current mirror branches are added into a conventional clock
generator to accomplish spread spectrum function. The proposed
SSCG circuit is on a small area. Furthermore, the circuit minimizes
effect caused by leakage current so that this circuit can be
maintained even at high temperature. The proposed circuit has
been applied to a y-back converter and the measured results
show the proposed architecture does achieve spread spectrum
function as expected.

Acknowledgement
This research was supported by Natural Science Fund of
60436030
References

Fig. 10. The spectrum of the switching voltage output wave by measurement.

centralized in nonspread-spectrum scheme but when SSCG is

introduced, peak EMI is lowered indeed.
Figs. 9 and 10 show switching voltage output wave and the
spectrum of it by measurement. Fig. 10 indicates initial energies
of harmonics are spread along a comparatively wide band of

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