ChallengesWithPackage

onPackage(
onPackage(PoP
PoP)
)
T h l
Technology
Greg Caswell
Sr. Member of the Technical Staff
CTEA meeting
21 February 2012

2004 2010

A
Agenda
d
PoP Background
g
Configurations and
Examples
PoP compared to SiP
Assembly
Warpage Issues
Drop Testing Impact
Thermal Cycles
Reliability
Underfill

Root Cause
Next Generation PoP
Through Mold Via

B
BenefitsofPoP
Benefitsof
fit f PoP
P P
The benefits of PoP are well known. They include
Less board real estate
Better performance (shorter communication paths
between the micro and memory)
Lower
L
junction
j
ti
temperatures
t
t
(at
( t least
l
t compared
d to
t
stacked die)
Greater control over the supply chain (opportunity to
upgrade memory and multiple vendors)
Easier to debug and perform F/A (again, compared to
stacked die or multi-chip module or system in package)
Ownership is clearly defined: Bottom package is the
logic manufacturer, the top package is the memory
manufacturer, and the two connections (at least for onepass) are the OEM

P k
PackageonPackage(PoP)
P k
(P P)
A configuration
g
where two p
packaged
g
integrated
g
circuits are placed directly on top of each other
o Can also be known as stacked packages
Interconnects are between the top package and
the bottom package and the bottom and the PCB
o Top package traditionally contains multiple or
stacked die
o Bottom package traditionally contains smaller /
thinner die

P
PoP(StackedBGAs)
P (St k d BGA )

Bottom Package
o Has land pads on top perimeter
to allow for top PoP attach
o Molded using special process to
keep perimeter clear
o Requires thin die and mold cap to
allow for top package clearance

Top Package
o Based on conventional stacked die BGA but larger ball size
and thinner mold body
o Ball pitch and size constrained by need to clear bottom
package
Packages must be capable of being placed on the printed
circuit board (PCB) and reflowed simultaneously to each
other and to the board
5

PoPStackedBGAs(cont.)
P P St k d BGA (
t)

Both packages are relatively thin

o Maximum
i
height
i
typically
i
1.4 to 1.6 mm
o Focus tends to be on slimming top package

Thinning
Thi i
off bottom
b tt
package
k
can be
b difficult
diffi lt

o Thinner substrate can increase warpage

o Smaller ball size can impact drop testing and temp
cycle

Standard package sizes

o 15x15 mm
mm, with 14x14 and 12x12 also available
o 0.65mm pitch, with 0.5mm and 0.4mm available
o Ball size can vary from 0.45 to 0.35mm

PoPExamples
p

Stacked Package on Package (PoP): The placement is often

arranged through a soldering operation, but can also be performed
with other interconnect technology
Example of
package on
package
k
d
device
i
from Samsung

Example of package
on package devices,
with
ith stacked
t k d die
di in
i
each package, from
Mitsubishi

PoPExamples(cont.)
P PE
l (
t)

Texas Instruments
8

WhyPoP
Why
PoP??

Yield / Flexibility / Ownership

No issues with known good die

(KGD)

Memory can be easily

upgraded
o Also allows for multiple
sourcing

Ownership is clearly defined

o Bottom package: Logic
manuf.
o Top package: Memory
manuf.
o Board level connection: OEM
9

ThermalComparison
p

10

P P U
PoPUses
Dominant use
o Integration of digital logic device in bottom
package with combination memory devices (i.e.
DRAM and flash) in top package
o Top package typically stacked die
Some pure memory PoP solutions also available
Cameras / mobile devices are main users
o Increasing interest from high rel industries

11

P PA
PoPAssemblyProcess
bl P
Assembly of PoP can be
through one or two reflows
o Most commonly single
reflow (aka, one-pass)
Top package is typically
dipped before placement
o Flux (sticky) or solder paste

12

P PA
PoPAssembly(cont.)
bl (
t)
PoP can also be offered
as a two-pass assembly
o IDM assembles top and
bottom package and places
them in a carrier for boardboard
level assembly
Other assembly options include use of solder on
pad (SoP) on bottom package
13

S ld
SolderonPad(SoP)
P d (S P)

Consists of solder balls

on the topside of the
bottom package

Designed to induce a
larger solder joint collapse
to absorb package warpage

Difficulties
o Balls must be well aligned
(limited self-alignment)
o Top package can slide off the balls
during placement or reflow,
reflow
leading to a poor solder joint or bridging
14

Design Factors Impacting Warpage

Mold

Die
Die size

Material property

Die Thickness

Shrinkage
Sh i k
Thickness

Die
Di attach
tt h
Material property
Thickness

2011 Amkor Technology, Inc.

Amkor restricted release to SMTA

Laminate
L i t Substrate
S b t t
Properties
Thickness
Cu ratio
Routing
June 2011, SMTA LSMIT

Warpage
Warpage

Many technical challenges present in PoP assembly

o Improper
I
reflow
fl
profiles
fil can lead
l d to
t solder
ld balls
b ll dislodging
di l d i
or migrating off the pad
o Excessive warpage can lead to solder ball bridging, solder
p g, head and p
pillow defects,, or open
p
jjoints
slumping,

Number one challenge in assembly is controlling and

matching warpage of top and bottom packages
o More than 90% of the defects in PoP assembly are due to
package warpage (cit. KIC)

Minimizing warpage is a trade off between materials,

materials
temperature control and time
o The extent and degree of warpage is increasing as
substrates become thinner
16

PackageWarpage
Package
Warpage

Due to mismatch in CTE

between the substrate, mold
compound and die
o Die attach can also play
a role

High Tg mold compounds

are used to balance CTE
mismatch between die and
substrate
b t t

Effect of mold compound

b
becomes
negligible
li ibl att reflow
fl
temperatures

17

Warpage (cont.)

General warpage trend at room temp.

o Inconclusive

Some claim bottom is smiling (positive,

concave) while top is crying
(negative, convex)
o Others claim the reverse

Partially dependent if CTE of mold

compound is more / less than
substrate

Example: Periphery of bottom

package is devoid of mold compound
o At reflow temperature,
temperature exposed
substrate could expand more
compared to substrate under the
mold compound

Desirable to have matching warpage

18

W
Warpage
andYields
d Yi ld

19

Warpage Drivers:Die
Drivers: Die

Thinner die and smaller die tend to minimize

warpage
o Larger / thicker die tend to drive crying at RT

20

WarpageandReflow
P fil
Profile

Ramkumar, 2008 European Electronic Assembly Reliability Summit

21

Reliability:DropTesting/Warpage
Reliability:DropTesting/
y
p
g Warpage
p g

Each board was dropped

200 times
ti
per JEDEC JESD11JESD11
B22
o 1500g for 0.5ms

The bottom package was

always first to fail
o Inline with other studies

No significant differences in
top package reliability
o Reliability seemed to be
independent of yields
p g
and warpage
22

Reliability:DropTesting/Warpage
Reliability:DropTesting/
Warpage

Test vehicle was a mechanical dummy of a cell phone

The drop-test was 3 cycles on six sides = 18 drops from 1.5m
Process Development and Reliability Evaluation for Inline Package-on-Package (PoP) Assembly (Flextronics)

23

DropTesting/Warpage
(
(cont.)
t)

Four different failure modes

observed during drop testing

Failure mode 4 was only found

on combination B

Combination B

Low yield with ENIG surface

finish
Poor warpage alignment
24

Underfill
Typically a filled epoxy
o High
g modulus ((>10 GPa))
o Range of coefficient of thermal expansion (CTE)
values (16ppm 30ppm)
Improves drop test performance
o Reduces stress on interconnect due to substrate
bending
Improves thermal cycling robustness
o Reduce shear stress on solder
o Links die and substrate to reduce thermal
expansion mismatch
25

Underfill Design
C
Considerations
id ti
Design
g Considerations for Package
g on Package
g
Underfill
In PoP, the top and bottom packages are usually
the same size.
Both levels must be underfilled for good reliability.
They also must be filled simultaneously.
The
Th top
t
layer
l
underfills
d fill more slowly
l l than
th
the
th bottom
b tt
layer because of the thermal delta between the top
and bottom levels.
In order to underfill both levels simultaneously, the
fluid must reach the top of the second level gap.

26

Reliability:Underfill
Reliability:
Underfill andThermalCycling
Temp cycle

27

Underfill andThermalCycling(cont.)

28

Underfill andTemperatureCycling

Rapid time to failure for underfills D / F / G

Best reliability
o No underfill or underfill with Tg > 110C (A and C)
29

Reliability
y
Underfill is increasingly being considered for
PoP
o Improves 2nd level reliability under drop testing

However, increasing indications that use of

underfill may greatly reduce reliability under
temperature cycling
Case Study (-40 to 125C)
o With underfill: 300 cycles
o Without underfill: >1000 cycles

30

Warpage Resolution

High Density PoP (Packageon-Package) and Package

Stacking Development
Ways around package
warpage
o Solder on pad (SOP)
While previous PoP BLR
investigations showed a
tendency to failure at the
bottom joints we see that the
finer pitch resulted in
numerous failures on the top
joints early in the testing in
leg 3. For this reason a better
composition of top package
ball and bottom package
SOP was selected in leg4
which improved the BLR
reliability
31

D
Device
Dyynamics

Pacckaging S
System Dyn
namics
Chaallenges

Next Gen PoP: Increased - Integration,

Miniaturization, Performance & Collaboration
Signal processing
P integration Bband + applications - increased pin counts
P core speed 2 3X w/ each node (1GHz @ 45nm)
Transition to FC accelerates from 65nm
Memory Interface
Higher speed memory interface SDRAM DDR > LP DDR2
Wider memory bus 16 32
Shared to split bus to (2 channel) architectures
Increased pin counts with size reduction requires 0.4mm pitch top and bottom
Warpage control with thinner / higher density PoP stacks
Signal
S
g
integrity
eg y op
optimization,
o , decoup
decoupling
g ccap
p integration
eg
o
Power efficiency and thermal mngmt
Si / pkg co-design for PoP to optimize for cost / performance

Processor I/O
P
CMOS Node
Peak Power
Ave Die Size
Ave.

400
65nm
400mW
64mm
64mm
2008

2011 Amkor Technology, Inc.

Amkor restricted release to SMTA

600
45nm
800mW
50mm
50mm
2010

800
28nm
1.2 W
50mm
50mm
2012
June 2011, SMTA LSMIT

Thru Mold Via Technology (TMV)

Enabling technology for next generation PoP reqmts

Improves warpage control and PoP thickness reduction

TMV removes bottlenecks for fine pitch memory interfaces
Increases die to package size ratio (30%)
Improves fine pitch board level reliability
Supports Wirebond, FC, stacked die and passive integration

2011 Amkor Technology, Inc.

Amkor restricted release to SMTA

June 2011, SMTA LSMIT

Construction and package stack-up for the TMV PoP

Test Vehicle reported at SMTAI 2008

Reference : "Surface Mount Assembly and Board Level Reliability for High
Density PoP (Package on Package) Utilizing Through Mold Via
Interconnect Technology - Joint Amkor and Sony Ericsson", Paper
2011 Amkor Technology, Inc.

Amkor restricted release to SMTA

June 2011, SMTA LSMIT

Viking RAMStack

2011 Amkor Technology, Inc.

Amkor restricted release to SMTA

June 2011, SMTA LSMIT

Summary

390million PoP components shipped in 2010 up from < 5

million in 2005. Forecasted to grow at same high rate as
Smartphones

DDR2 2 channel and other new memory architectures

driving higher density PoP memory interfaces

Amkor pioneered 1st Generation PoP (PSvfBGA) and now

leading in Next Gen high density PoP with TMV
technology shipping in HVM

One pass SMT PoP stacking enables optimization of supply

/ logistics and lowest total cost of ownership

Amkor and Universal Instruments planning 14mm 620 / 200

TMV PoP SMT stacking study and industry report to
facilitate SMT yield / quality optimization

2011 Amkor Technology, Inc.

Amkor restricted release to SMTA

June 2011, SMTA LSMIT