Registers and Counters

Register : A Group of Flip-Flops.

N-Bit Register has N flip-flops.

Each flip-flop stores 1-Bit Information. So N-Bit Register
Stores N-Bit Information.
Register may have combinational gates to perform data
processing tasks.

Counter:

It is a Register that goes through

predetermined sequence of states upon the application of
input pulses.

Registers:

Simplest form is one without any external gates.

4-Bit Register with D-type Flip-Flop and Common Clock
Pulse Input CP.
Four Inputs I1, I2, I3, I4 and Four Outputs A1, A2, A3
and A4.

Triggering
(a)

Level Triggered.

When Clock=1, Output Q follows Input D as long as Clock=1

When Clock=0, information at Input D Just before the
transition is retained at the Output Q.
This Flip-Flop is sensitive to pulse duration, and output is
enabled as long as Clock=1
A flip-flop that responds to the pulse duration is commonly
called a Gated Latch.

Triggering
(b)

Edge Triggered.
When Clock transits to Positive Level, during Positive Edge Transition Input
D Just Before the transition is sampled by flip flop.
Here D=1 before transition, so Q=1 as soon as positive edge transition
occurs.
Once flip-flop is Positive Edge triggered, now it keep the same value until
next Positive Edge Comes.
At next Positive edge, the value of Input D just before the Positive Edge
transition is sampled.
Here it is 0, so Q=0 till the next transition.
Flip-flop triggered by edge is called Register.

Register with Parallel Load:

Transfer of new Information into a register is called loading.
If all Inputs (Bits) are simultaneously transferred with a single clock
pulse it is called parallel loading as shown in fig.
When CP=0, content of register left unchanged.
When CP to 1, Input bits are loaded to ip-flops.
Here Transition takes place during Positive Edge. If it takes place at
Negative edge than in Figure, small circle under the triangle of clock
pulse line will be shown.

Register with Parallel Load:

LOAD

I4

I3

I2

I1

CP

If Control of Loading is to be done for specific clock pulses, then

Clock is ANDed with such control signal.
So when that control signal LOAD is 0, O/P of register remain
unchanged. When LOAD is 1, at every Clock Pulse Positive Edge
Information loaded to register is updated.

Register with Parallel Load:

LOAD

I4

I3

I2

I1

CP

But ANDing Master Clock adds Gate Propagation Delay

in Clock Path to Flip-flop Input Clock Pulses. If this delay
is varied over the different flip-flops, then
synchronization of circuit fails.
So Gates are used in other control signals, and clocks are
directly given to each flip-flop.

Register with Parallel Load:

Load Input is ANDed with

Inputs to the Flip-Flops.
Buffer is used to Increase
the Fan-out Capacity of Load
Input.
Even Clock is present,
Loading is controlled by
Keeping Load=1.
With Load=0 Inputs to S and
R of each Flip-Flop is 0. So
No change in Output at any
clock pulse.
4 Bit Register With Parallel load (RS Flip-Flops)

Register with Parallel Load:

Clear input via NonInverting Buffer goes to one

terminal on each flip-flop.
0 on this clears all
registers asynchronously.
Clear Input is used to clear
Register before clocked
operation.

4 Bit Register With Parallel load (RS Flip-Flops)

Register with Parallel Load:

Clock Pulse CP is given to

each Flip-Flop via Inverter.
Thus it is Negative Edge
Triggering.
Clock Input is using only one
inverter to reduces load on
Clock Generator.

4 Bit Register With Parallel load (RS Flip-Flops)

Register with Parallel Load:

For Each I=1, with Load=1,
corresponding inputs to F/F
are S=1 and R=0, so
Corresponding output A will
Set at next clock pulse.
For Each I=0, with Load=1,
Corresponding inputs to F/F
are S=0 and R=1, will clear
corresponding o/p A.

4 Bit Register With Parallel load (RS Flip-Flops)

Register with Parallel Load:

Clock and Clear Inputs are
same as Register using RS FlipFlops.
When Load Input is 1, Inputs
are transferred to registers on
the next clock pulse.
When Load Input is 0, circuit
inputs are inhibited, and D flipflops are reloaded with their
present value (via feedback).
Feedback
Connection
is
necessary as there is no No
Change input condition in D
4 Bit Register With Parallel load (D Flip-Flops)
Flip-Flop.

Sequential Circuit using Registers with parallel load.

Design a Sequential Circuit having given State Table

Output Equation and Next

State Equations from table

Using the Minterms placed in K-Map for each of the above equation

Sequential Circuit using Registers with parallel load.

Logic Diagram

Shift Registers

Register capable of shifting its binary information

to the left or right is called shift register.

Flip-Flops are in Cascade Configuration. O/P of One F/F to

the I/P of Next F/F.
Simplest form is one shown in Fig. which uses no gates,
only flip-flops.
Each Clock Pulse shifts contents of register one bit
position to right.
Serial Input Determines what goes into left most flip-flop
during shift.

Shift Registers
Serial Shift Right Register.
Here Information is 5 Bit
long, and is saved after 5
Clock Pulses.

Shift Registers
Serial Transfer:
In one Shift Register, One bit
Information is passed from output
of one flip-flop to next flip-flop.
Serial Transfer of Information of Nbits from one Register to another
register is done using Shift Registers
connected as shown in Fig.
Serial Output (SO) of Register A
connected to Serial Input of
Register B.
Serial Bits Information of Register A
is circulated to A to avoid loss of
information.

Shift Registers
Serial Transfer:
Initial Information contained in
Register B is Shifted out through
its serial output SO and is lost if
not captured by third shift
register connected to it.
Shift Control Determines when
and how many times registers
are shifted.
AND gate allows clock pulses to
pass into CP terminal only when
Shift Control is 1.

Shift Registers
Serial Transfer:
For Shift Registers having 4 Bits
Each.
4 Bits to be shifted from One
Register to Another register.
1 bit is shifted in one clock
pulse.
So 4 Clock Pulses are required
for 4 bit shift.

Shift Registers
Serial Transfer:
Shift Control is Kept High for
duration equal to 4 clock pulses.
It is synchronized with Clock
and change its value just after
Negative edge of clock pulse.
CP Terminal Produces 4 Pulses
T1, T2, T3 and T4.
At 4th Pulse Shift Control
changes to 0 and CP is disabled.

Shift Registers

Binary Content of A before the shift : 1011

Binary Content of B before the shift : 0010

Serial Transfer:
At T1 Rightmost Bit of A is Shifted in to Leftmost Bit of B. Also it
is Circulated in to leftmost position of A. Other Bits of A and B are
shifted one position to right. Previous Serial Output from B is lost
and its value changes to 1.
In Next three clock pulses, identical shift operations are performed,
shifting the bits of A into B.
Serial
Output
of B

0
1
0
0
1

Shift Registers
Serial Transfer:

After the fourth Shift, Shift Control goes to 0 and both registers
A and B have the value 1011.
Content of Register A is Transferred to Register B, while content
of Register A remain unchanged.
Serial
Output
of B

0
1
0
0
1

Bidirectional Shift Register with Parallel Load

A shift Register Capable of shifting both left and right is called
Bidirectional Shift Register.
Register having both Shift and Parallel Load Capability is
called Shift Register with Parallel Load
How to get both operations ?
Serial to Parallel
If access to o/p of each flip-flop of shift register then serially
entered information by shifting can be taken out in parallel
form from the o/p of flip-flops.
Parallel to Serial
Similarly Parallel Load Capability added to shift register allows
to take out the parallel entered data in serial fashion by
shifting data stored in register.

Bidirectional Shift Register with Parallel Load

Most general Shift register is having all capabilities like:
1. A Clear Control to clear register to 0.
2. A CP input for clock pulses to synchronize all operations.
3. A shift-right control to enable the shift-right operation and
the serial input and output lines associated with shift-right.
4. A shift-left control to enable the shift-left operation and the
serial input and output lines associated with shift-left.
5. A parallel-load control to enable a parallel transfer and n
input lines associated with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves information in the register
unchanged even though clock pulses are continuously
applied.

Bidirectional Shift Register with Parallel Load

Serial Addition
4 Bits of Each Input x and y
are serially entered and
stored in Register A and
Register B initially.
Carry Flip Flop is Cleared. This
carry is entered as z in Full
Adder Circuit.
Serial Output Bits SO of Each
Shift Register Provides a pair
of LSBs of two inputs x and y
for Full Adder Circuit.

Serial Addition
With Shift-right Control
Input is 1, at every clock
pulse One bit from A,
from B are shifted right.
At the same time Shift
Right Enables D Flip-Flop
to give output, which is
carry input z to full
adder.

Serial Addition
At every clock pulse Input
bits are entered in Full
Adder, Sum bit generated
is circulated back to the
Register A and If carry
generated than, it is added
during next clock pulse,
with next two successive
bits.
After four clock cycles Shift
right disables clock pulse
CP, so Sum is retained in
Register A.

Serial Addition
To add a new number
with contents of A, it is
first serially transferred
to B, and then Shift Right
initiates Serial Addition
Operation

Serial Adder using Sequential Circuit and Shift Registers

Previous
Carry

Carry

C=Q(Next State)

Sum

Serial Adder using Sequential Circuit and Shift Registers

C = Q (Next State)

Counters
Ripple Counter :
Flip-flop output transition serves as a source of triggering
other flip-flops.
CP input to all flip-flops ( Except first flip-flop) are triggered
not by incoming clock pulse but rather by transition that
occur in other flip-flops.
Synchronous Counter:
Input pulses are applied to CP Inputs of all flip-flops.
Change of state or a particular flip-flop is dependent on
present state of other flip-flops.

Ripple Counter :

4 Bit Binary Ripple Counter

Clock Pulse is Negative edge triggering Type.

JK flip-flops with both J and K equal to 1 toggles output
at next negative edge transition of clock.

It is Up Counter. For Down Counter (1111 to 0000) , O/P taken

from Q or Positive Edge triggering used.

Ripple Counter :

4 Bit Binary Ripple Counter

Ripple Counter :

4 Bit BCD Ripple Counter

Q8 Q4

State Diagram of BCD Counter

Q1 Complements every Clock Pulse negative edge

Q2 is complemented when Q8=0 and Q1 goes from 1 to 0.
Q2 is cleared when Q8=1 and Q1 goes from 1 to 0.
Q4 is complemented when Q2 goes from 1 to 0.
Q8 is complemented when Q4Q2=11 and Q1 goes from 1 to 0.
Q8 is cleared when either Q4 or Q2 is 0 and Q1 goes from 1 to 0.

Q2

Q1

Ripple Counter :

4 Bit BCD Ripple Counter

Timing Diagram :
Other way to verify operation of Counter.
Draw Timing Diagram of Counter with Clock
Transitions.

Decade Counter

BCD Counter is Decade Counter, as it counts from 0 to 9 and then repeat.

To Count Decimal from 00 to 99, two BCD Counters ( Decade Counters) are
required.
Multiple Digit Decade Counters can be made by connecting them in
Cascade.

When Q8 goes from 1 to 0 , Next Decade Counter receives

Negative Edge as Clock Pulse in first flip-flop.

Synchronous Counter
4 Bit Synchronous Binary Counter
Input pulses are applied to CP Inputs of
all flip-flops.
For 1st JK Flip-Flop to toggle at every
Clock Negative Edge, Count Enable Input
is Kept 1 and connected to J and K.
A2 toggles when Count Enable and A1
are 1.
A2 remains unchanged when A1 is 0.
A3 toggles when Count enable, A1 and
A2 all are 1.
A3 remains unchanged when either A1 or
A2 or both are zero.
A4 toggles when Count Enable, A1, A2
and A3 all are 1.
A4 remains unchanged when any of the
A1, A2, A3 are zero or all are zero.
Here Clock Pulse is independent so can
be Positive or Negative Edge Triggering.

Binary Up-Down
Synchronous
Counter
T flip-flop is used for Counter.
A0 Toggles for Up or Down any
Sequence.
For Up Counter, Q of Each Flip-Flop is
ANDed with Up Input & its o/p is
Connected to OR Gate.
For Down Counter Q of Each Flip-Flop is
ANDed with Down Input Connected to
OR gate.

BCD Counter
Output y is used as Input to Next Decade
Counter Count Input.
As in Synchronous Counter, Clock Pulses are
given synchronously to each flip-flop, y is
required here for next decade counter to
start with.

Binary Counter with Parallel Load

Binary Counter with

Parallel Load
Load = 1 then Count is
Disabled. Information on
I0, I1, I2, I3 are transferred to
Each flip-flop.
Load = 0 then Inputs are
not allowed to enter in flipflops.
If Count=0, Register retain
previous value. (JK=00)
If Count=1, JK=11, so flipflop toggles its input at
next clock positive edge.
Circuit Operates as Counter.

Binary Counter with

Parallel Load
A1 flip-flop toggles when
Count=1, Load=0,
A0=1
A2 flip-flop toggles when
Count=1, Load=0,
A0,A1=1
A3 flip-flop toggles when
Count=1, Load=0,
A0, A1, A2=1
C_out = 1 when,
Count=1,
A0, A1, A2 and A3 = 1.

Binary Counter with Parallel Load

Function Table

Modulo-N Counter
N is the Number up to which the counting is done
For Binary Counter of 4 bits, it is called Modulo -16 Counter,
From Modulo-16 Counter, any N Between 1 to 16 Count Counter can be
constructed.
Modulo-6 Counter Counts from 0 to 5 or 1 to 6 or 2 to 7 or so on up to 10 to 16.
Binary counter with parallel load capability can be used to design such counter.

Modulo-6 Counter

Modulo-6 Counter

Modulo-6 Counter