E Cad Lab Manual

VLSI 1
LABORATORY MANUAL
(R13) I M. Tech., i-Semester
ECE VLSI
Name of the Student:

H. T. No:
Academic Year:
2013-14
D E P A R TM E N T O F E L E C TR O N I C S A N D C O M M U N I C A TI O N E N G I N E E R I N G
R AM A CH AN DR A C O LL E GE O F E N GI NE E RI N G, EL U RU 5 3 4 0 0 7
West Godavari District, Andhra Pradesh
VLSI 1
LABORATORY MANUAL
Design and review by
Prof. JAGAN MOHAN RAO S.

Professor & Head
Prepared by
Mr. Md. Baig Mohammad

Associate Professor
Mr. PRASADA RAO A.
R AM A CH AN DR A C O LL E GE O F E N GI NE E RI N G, EL U RU 5 3 4 0 0 7
VLSI LAB 1
(R13) I M. Tech., ECE-VLSI, i-Semester
Index
S. No.
Name of the Experiment
1.
Design of Logic gates using Xilinx ISE Simulator/

Mentor Graphics Questa Simulator
2.
Design of Parity Encoder using Xilinx ISE Simulator/

Mentor Graphics Questa Simulator
3.
Design of Synchronous RAM using Xilinx ISE

Simulator/ Mentor Graphics Questa Simulator
4.
Design of ALU using Xilinx ISE Simulator/ Mentor

Graphics Questa Simulator
5.
Design of Sequence Detector using Xilinx ISE

Simulator/ Mentor Graphics Questa Simulator
6.
Design and implement the Layout of Inverter using

CMOS 130nm Technology with Mentor Graphics Tool
7.
Design and implement the Layout of Half Adder using

8.
Design and implement the Layout of Full Adder using

9.
Design and implement the Layout of D Flip-flop using

Date
Marks
Signature
10.
R A M A C H A N D R A C O L L E GE O F E N G I N E E R I N G , E L U R U 5 3 4 0 0 7
R A M A C H A N D R A C O L L E GE O F E N G I N E E R I N G , E L U R U 5 3 4 0 0 7
GENERAL INSTRUCTIONS:
1. The experiments have been designed to be performed with in the 3-hour
laboratory time.
2. To successfully complete the experiment in one lab turn, come prepared to
the laboratory.
3. Read the experiment in advance.
4. List and collect the components for the experiment.
5. Be sure that the specifications and values of the components are as per
design.
6. Follow the experimental steps judiciously.
7. Record stepwise observations using proper test instruments.
8. Get the observation signed by the instructor.
9. Always take safety precautions while performing experiments.
GUIDANCE FOR THE LABORATORY REPORT:
1. Format of the report
Exp. No:
Date:
Expt. Title:
Objective:
List of instruments and components:
Theory in brief
Procedure, Observations, Graph if any
Result
2. Write the experimental observations and measurements stepwise.
3. Plot the graph neatly. Always label the axes and indicate units too.
Wherever frequency response is to be drawn, use the semi-log graph paper.
4. Compare the results with theoretical values with remarks/comments.
5. Wherever necessary, sketch the circuit diagram neatly and label the
components.
Expt. #:
Date:
Sheet #:
PART A:
The students are required to design the logic circuit to perform the
following experiments using necessary simulator (Xilinx ISE Simulator/
Mentor Graphics Questa Simulator) to verify the logical /functional
operation and to perform the analysis with appropriate synthesizer (Xilinx
ISE
synthesizer/Mentor Graphics Precision RTL) and then verify the
implemented logic with different hardware modules/kits (CPLD/FPGA kits).
1. Realization of Logic gates.
2. Parity Encoder.
3. Synchronous RAM.
4. ALU.
5. Sequence Detector
PART B:
The students are required to design and implement the Layout of the
following experiments of any FOUR using CMOS 130nm Technology with
Mentor Graphics Tool
1. Inverter Characteristics.
2. Full Adder.
3. RS-Latch, D-Latch and Clock Divider.
4. Synchronous Counter and Asynchronous Counter.
Dept. of Electronics and Communication Engineering
RAMACHANDRA COLLEGE OF ENGINEERING - ELURU
Expt. #:
Date:
Sheet #:
1. LOGIC GATES
AIM:
To simulate and synthesize various logic gates like AND, OR, NOT,
NAND, NOR, XOR and XNOR and verify the results and obtain the
simulation waveforms and synthesis report.
HDL Used: VERILOG/VHDL

EDA TOOLS:
i) For Simulation: ModelSim PE 5.7f
ii) For Synthesis: Xilinx ISE 12.1i
DESCRIPTION:
Basically a gate is one which has two inputs and one output. The basic
gates that we use in general are AND, OR, NOT, NAND, NOR, XOR, XNOR.
These gates are primarily used to design the digital system. NAND and NOR
gates are called Universal Gates because any gate can be implemented with these
gates. These gates are simulated using the verilog programming language
according to their following the various gates.
Program:
Library IEEE;
use IEEE.std_logic_1164.all;
entity gates is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
oor,oand,onor,onand,onot,oxor,oxnor: out STD_LOGIC
);
end
architecture behav1 of gates is
begin
oand<= x and y;
oor<= x or y;
Expt. #:
Date:
Sheet #:
onand<= x nand y;
onor<= x nor y;
onot<= not x;
oxor<= x xor y;
oxnor<= not(x xor y);
end behav1;
Wave Forms:
Expt. #:
Date:
Sheet #:
Synthesis Report:
Module Name:
Logic gates Project Status

Logic gates.ise
Current State:
Errors:
Gates
Target Device:
xc3s500e-4fg320
Product Version:
ISE, 8.1.03i
Project File:
Warnings:
Updated:
Synthesized
No Errors
No Warnings
Device Utilization Summary (estimated values)

Logic Utilization
Used
Available
Utilization
Number of Slices
3
4656
0%
Number of 4 input LUTs
6
9312
0%
Number of bonded IOBs
9
232
3%
Report Name
Synthesis Report
Translation Report
Map Report
Place and Route Report
Static Timing Report
Bitgen Report
Detailed Reports
Status
Generated
Current
Errors Warnings
0
0
Infos
0
Expt. #:
Date:
Sheet #:
Rtl schematic:
Expt. #:
Date:
Sheet #:
RESULT: The given digital circuit was simulated and synthesized successfully
using the software and simulation waveforms, synthesis report and circuit was
drawn.
Expt. #:
Date:
Sheet #:
2. Parity Generator and Checker

AIM: To simulate and synthesize Parity generator and verify the results to obtain
the simulation waveforms and synthesis report.
EDA TOOLS:
VHDL Program:
library ieee;
use ieee.std_logic_1164.all;
entity block1 is
port(a,b,i : in bit;
c,d : out bit);
end block1;
architecture block1 of block1 is
begin
process(a,b,i)
begin
if(i='1') then
d<= a;
c<=b;
else
c<=a;
d<=b;
end if;
end process;
end architecture;
Now create a new vhdl right click --> add new

here we create the full modeling of parity generator program :
library ieee;
use ieee.std_logic_1164.all;
Expt. #:
Date:
Sheet #:
entity parity1 is
port(q:in bit_vector(3 downto 0);
o: out bit_vector(4 downto 0));
end parity1;
architecture parity1 of parity1 is
component block1 is
port(a,b,i: in bit;
c,d: out bit);
end component block1 ;
signal t : bit_vector(8 downto 0);
signal e : bit_vector(1 downto 0);
begin
e(1) <='1';
e(0) <='0';
u1: block1 port map(e(1),e(0),q(3),t(0),t(1));
u2: block1 port map(t(0),t(1),q(2),t(3),t(4));
process(q)
begin
if(t(7)='0') then
o(4)<=q(3);
o(3)<=q(2);
o(2)<=q(1);
o(1)<=q(0);
o(0)<='0';
else
o(4)<=q(3);
o(3)<=q(2);
o(2)<=q(1);
o(1)<=q(0);
o(0)<='1';
end if;
end process;
end parity1;
Expt. #:
Date:
Sheet #:
Expected Results:
RESULT: The given digital circuit was simulated and synthesized successfully
using the software and simulation waveforms, synthesis report and circuit was
drawn
Expt. #:
Date:
Sheet #:
3. RAM
AIM: To write the VHDL code for IC 74X189read and write operations of
RAM
EDA TOOLS:
BLOCK DIAGRAM:
TRUTH TABLE:
VHDL code:
library IEEE;
use IEEE.std_logic_1164.all;
entity ram is
port (
rw : in STD_LOGIC;--read or write enable pin
en_l: in STD_LOGIC; --active low enable pin
Expt. #:
Date:
Sheet #:
datain: in STD_LOGIC_VECTOR (3 downto 0);--4-bit input data line

addr: in STD_LOGIC_VECTOR (3 downto 0); --4-bit address line
dataout: out STD_LOGIC_VECTOR (3 downto 0) --4-bit input data line
);
end ram;
architecture ram of ram is
subtype wtype is STD_LOGIC_VECTOR (3 downto 0);
type mem_type is array (15 downto 0) of wtype;
signal memory:mem_type; ;--creates 16 memory locations.Each location can store
--4-bits
function conv_integer(x:std_logic_vector) return integer is --function to convert
variable
result:integer; --binary to integer
begin
result:=0;
for i in x'range loop
if x(i)=1 then
result:= result+2**i;
else null;
end if;
end loop;
return result;
end conv_integer;
begin
process(en_l,rw,addr)
begin
if(en_l='0') then
if (rw ='0') then --performs write operation
memory(conv_integer(addr))<= datain;--stores the data in the
dataout<="ZZZZ"; -- corresponding memory
elsif (rw ='1') then -- the output performs read operation
dataout<=not memory(conv_integer(addr));--places the data on
end if; -- the given address line
else
dataout<=(others=>'Z'); --output is in inhibit state when en_l=1(i.e.Hi--impedence)
end if;
end process;
end ram;
Expt. #:
Date:
Sheet #:
Expected Simulation Results:
RESULT: The given digital circuit was simulated and synthesized successfully using the
software and simulation waveforms, synthesis report and circuit was drawn
Expt. #:
Date:
Sheet #:
4. ARITHMETIC LOGIC UNIT (ALU)

AIM: To design and implement the 8 bit ALU in FPGA / CPLD
EDA TOOLS:
BLOCK DIAGRAM:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
port( clk : in std_logic;
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
sig : in std_logic_vector(3 downto 0);
c : out std_logic_vector(7 downto 0);
carry : out std_logic);
end alu;
architecture Behavioral of alu is
signal reg1,reg2 : integer;
Expt. #:
Date:
Sheet #:
signal tmp : std_logic_vector(8 downto 0);

signal delay : std_logic_vector(2 downto 0):= 000;
begin
process(a,b,sig)
variable cnt :integer range 0 to 16 := 0;
begin
if rising_edge(clk) then
c <= "00000000";
carry addition
tmp(4 downto 0) <= conv_std_logic_vector((conv_integer(a) +
conv_integer(b)),5);
c(3 downto 0) <= tmp(3 downto 0);
carry subtraction tmp(4 downto 0) <= conv_std_logic_vector((conv_integer(a)
conv_integer(b)),5);
c(3 downto 0) <= tmp(3 downto 0);
carry Multiplication
c Division
c(3 downto 0)
reg1 <= conv_integer(a);
reg2 <= conv_integer(b);
delay
if(reg2 = 0) then
delay <= "011";
else
delay
if(reg1 >=reg2) then reg1 <= reg1-reg2; cnt:=cnt + 1; delay <= "010";
else
tmp(3 downto 0) <= conv_std_logic_vector(cnt,4);
delay tmp(3 downto 0) <= "0000";
delay cnt := 0;
delay
end case;
when 0100 => and gate
c(3 downto 0) or gate
c(3 downto 0) xor gate
c(3 downto 0) nand gate
c(3 downto 0) nor gate
c(3 downto 0) xnor gate
c(3 downto 0)<= a(3 downto 0) xnor b(3 downto 0);
when "1010" =
c(3 downto 0)
Expt. #:
Date:
Sheet #:
end case;
end if;
end process;
end Behavioral;
UCF FILE :
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET a LOC = p5 ;
NET a LOC = p4 ;
NET a LOC = p3 ;
NET a LOC = p2 ;
NET b LOC = p9 ;
NET b LOC = p8 ;
NET b LOC = p7 ;
NET b LOC = p6 ;
NET c LOC = p29 ;
NET c LOC = p28 ;
NET c LOC = p27 ;
NET c LOC = p25 ;
NET c LOC = p23 ;
NET c LOC = p22 ;
NET c LOC = p21 ;
NET c LOC = p20 ;
NET carry LOC = p38 ;
NET clk LOC = p44 ;
NET sig LOC = p15 ;
NET sig LOC = p14 ;
NET sig LOC = p12 ;
NET sig LOC = p10 ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
Expt. #:
Date:
Sheet #:
OUTPUT WINDOW:
Expt. #:
Date:
Sheet #:
5. SEQUENCE GENERATOR
Aim: To write a VHDL program to generate the 1010 sequence generator
EDA TOOLS:
Truth Table:
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SEQ_DETECTOR is
Expt. #:
Date:
Sheet #:
Port ( X : in STD_LOGIC;
CLK : in STD_LOGIC;
Z : out STD_LOGIC);
end SEQ_DETECTOR;
architecture Behavioral of SEQ_DETECTOR is
TYPE STATE_TYPE IS (S0,S1,S2,S3);
SIGNAL CURRENT_STATE,NEXT_STATE:STATE_TYPE;
BEGIN
PROCESS(CURRENT_STATE,X)
begin
CASE CURRENT_STATE IS
WHEN S0=>
IF X='0' THEN
Z<='0';
NEXT_STATE<= S0;
ELSIF X='1' THEN
Z<='0';
NEXT_STATE <=S1;
ELSE
Z<='0';
NEXT_STATE <=S0;
END IF;
WHEN S1=>
IF X='0' THEN
Z<='0';
NEXT_STATE <= S2;
ELSIF X='1' THEN
Z<='0';
NEXT_STATE <=S1;
ELSE Z<= '0';
NEXT_STATE <=S0;
END IF;
WHEN S2=>
IF X='0' THEN
Z<='0';
NEXT_STATE<= S0;
Expt. #:
Date:
Sheet #:
ELSIF X='1' THEN

Z<='0';
NEXT_STATE<=S3;
ELSE
Z<='0';
NEXT_STATE <=S0;
END IF;
WHEN S3=>
IF X='0' THEN
Z<='1';
NEXT_STATE<= S1;
ELSIF X='1' THEN
Z<='1';
NEXT_STATE<=S0;
ELSE Z<='0';
NEXT_STATE<=S0;
END IF;
END CASE;
WAIT UNTIL CLK='1'AND CLK'EVENT;
CURRENT_STATE<=NEXT_STATE;
END PROCESS;
end Behavioral;
Output Waveform:
Expt. #:
Date:
Sheet #:
PART B:
The students are required to design and implement the Layout of the
following experiments of any FOUR using CMOS 130nm Technology with
Mentor Graphics Tool
1.
2.
3.
4.
5.
Inverter Characteristics.
Half Adder
Full Adder.
D-Flip flop.
Expt. #:
Date:
Sheet #:
1. CMOS INVERTER
Aim:
To construct the CMOS Inverter in DSCH and to extract layout in MICROWIND
Tools used:
1. DSCH 2.6c (Digital Schematic Design and Simulation)
2. MICROWIND 2.6a
Procedure:
1. Open DSCH window.
2. Go to File New
3. Design the schematic using the tools
4. Run design and observe waveforms
5. Generate the Verilog file
6. Open MICROWIND window
7. Go to Compile Compile Verilog file
8. Extract the Layout
Schematic
Schematic diagram:
Expt. #:
Date:
Sheet #:
Wave Forms:
Verilog code:
module inverter( in1,out1);
input in1;
output out1;
pmos #(17) pmos(out1,vdd,in1); // 2.0u
0.12u
nmos #(17) nmos(out1,vss,in1); // 1.0u
0.12u
endmodule
// Simulation parameters in Verilog Format
always
#1000 in1=~in1;
// Simulation parameters
// in1 CLK 10 10
Expt. #:
Date:
Sheet #:
Layout diagram
Result:
The CMOS Inverter is constructed in DSCH, the LAYOUT is generated and
waveforms are verified.
Expt. #:
Date:
Sheet #:
2. HALF ADDER
Aim:
To construct the HALF ADDER in DSCH and to extract layout in MICROWIND
Tools used:
2. MICROWIND 2.6a
Procedure:
2. Go to File New
Schematic Diagram:
Expt. #:
Date:
Sheet #:
Waveforms:
Verilog Code:
module half adder( in1,in2,out1,out2);
input in1,in2;
output out1,out2;
xor #(16) xor2(out1,in1,in2);
nand #(16) nand2(w4,in2,in1);
not #(10) inv(out2,w4);
endmodule
always
#1000 in1=~in1;
#2000 in2=~in2;
// in1 CLK 10 10
// in2 CLK 20 20
Expt. #:
Date:
Sheet #:
Layout Diagram:
Result:
The half adder is constructed in DSCH, the LAYOUT was generated and
Expt. #:
Date:
Sheet #:
3. FULL ADDER
Aim:
To construct the FULL ADDER in DSCH and to extract layout in MICROWIND
Tools used:
2. MICROWIND 2.6a
Procedure:
2. Go to File New
Schematic Diagram:
Expt. #:
Date:
Sheet #:
Waveforms:
Verilog code:
module full adder( in1,in2,in3,out1,out2);
input in1,in2,in3;
output out1,out2;
xor #(16) xor2(w3,in1,in2);
xor #(16) xor2(out1,w3,in3);
nor #(13) nor3(out2,w6,w7,w8);
endmodule

always
#1000 in1=~in1;
#2000 in2=~in2;
#3000 in3=~in3;
// in1 CLK 10 10
Expt. #:
Date:
Sheet #:
// in2 CLK 20 20
// in3 CLK 30 30
Layout diagram:
Result:
The full adder is constructed in DSCH, the LAYOUT was generated and
Expt. #:
Date:
Sheet #:
4. D-FLIP FLOP
Aim:
To construct the D-FLIP FLOP in DSCH and to extract layout in MICROWIND
Tools used:
2. MICROWIND 2.6a
Procedure:
2. Go to File New
Schematic diagram:
Expt. #:
Date:
Sheet #:
Wave Forms:
Verilog Code:
module d ff( in2,clk1,out2,out1);
input in2,clk1;
output out2,out1;
nand #(16) nand2(w3,clk1,in2);
nand #(23) nand2(out1,out2,w3);
nand #(16) nand2(w7,w6,clk1);
nand #(23) nand2(out2,w7,out1);
end module
always
#1000 in2=~in2;
#1000 clk1=~clk1;
// in2 CLK 10 10
// clk1 CLK 10 10
Expt. #:
Date:
Sheet #:
Layout Diagram:
Result:
The D-Flip Flop is constructed in DSCH, the LAYOUT was generated and

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VLSI 1

Name of the Student:

Design and review by

Prof. JAGAN MOHAN RAO S.

Mr. Md. Baig Mohammad

Mr. PRASADA RAO A.

Name of the Experiment

Design of Logic gates using Xilinx ISE Simulator/

Design of Parity Encoder using Xilinx ISE Simulator/

Design of Synchronous RAM using Xilinx ISE

Design of ALU using Xilinx ISE Simulator/ Mentor

Design of Sequence Detector using Xilinx ISE

Design and implement the Layout of Inverter using

Design and implement the Layout of Half Adder using

Design and implement the Layout of Full Adder using

Design and implement the Layout of D Flip-flop using

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

HDL Used: VERILOG/VHDL

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Logic gates Project Status

Device Utilization Summary (estimated values)

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

2. Parity Generator and Checker

Now create a new vhdl right click --> add new

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

datain: in STD_LOGIC_VECTOR (3 downto 0);--4-bit input data line

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Expected Simulation Results:

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

4. ARITHMETIC LOGIC UNIT (ALU)

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

signal tmp : std_logic_vector(8 downto 0);

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

ELSIF X='1' THEN

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING - ELURU

Dept. of Electronics and Communication Engineering