FSK Demodulator Architectures

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4
FSK Demodulators

he previous chapter dealt with the theoretical aspect of Frequency Shift Keying demodulation. The conclusion from this analysis was that coherent demodulation will theoretically
perform best over non-coherent demodulation. But numerous unsolved problems arises
when trying to actually implement the coherent demodulation principle. This motivates a search for
non-optimal solutions to the demodulation problem that does not involve e.g. the phase
reconstruction problem. This chapter therefore describes some of the approaches to 1200 baud FSK
Demodulation found in literature, to judge the demodulation process from a more implementational
point of view. This traverse through already applied demodulation techniques might seem a bit
historical. But most attempts to implement monolithic modem circuits was reported in 1984 - 1988.

4.1 FSK Demodulation

In the following a summary is presented of three selected papers dated from the middle eighties.
The two first /Larber 84/ and /Apfel 84/ presents complete monolithic modem circuits whereas the
third /Fleige 88/ only discusses the properties of complex digital processing for demodulation of
FSK signals. The three papers are selected, because they represent three "levels" of complexity. I.e.
the effort spent into constructing the demodulator is raising through the three papers.

4.1.1 Zero-crossing Detector

Larber /Larber 84/ published in 84 a paper describing the design of "A monolithic 1200 Baud FSK
CMOS Modem". Larber describes the demodulator part of the FSK modem as being the most
critical section, and follows this statement with a selection of the zero-crossing demodulator for his
circuit.
The principle in a zero crossing detector is rather simple. The instantaneous frequency of the
incoming carrier is determined by counting the number of its zero crossings per unit time. It is
therefore crucial for this kind of detector to have a precise and high-performance front-end hard
limiter that can deliver low-jitter zero crossings even for minimum level input carriers. The block
diagram of the demodulator circuit is shown in Fig. 4.1.

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Chapter 4
Bias
distortion
trim

Digital
differentiator

Hard-Limited
Signal

and rectifier

Pulse

Switched Cap.

Data

Generator

Lowpass filter

Output

Clock

Fig. 4.1

Zero-crossing demodulator block diagram. The demodulator is made of a digital monostable, a

switched capacitor low-pass filter and a slicer comparator

Fig. 4.1 shows the zero-crossing demodulator. The hard-limited signal is digitally differentiated and
rectified in order to create a pulse every time the carrier crosses zero. This is implemented as shown
in Fig. 4.2 by a D-type flip-flop and an exclusive-OR gate. The pulse thus obtained is used to load
a down counter to create a pulse of fixed duration. This is corresponding to converting the
hardlimited FSK input to a Pulse Width Modulated (PWM) signal, from which the switched
capacitor filter then extracts the base band component. The switched-capacitor filter is a fifth-order
LC ladder whose amplitude response is approximately equal to a full-raised cosine function with
linear phase, thus minimizing intersymbol interference.

In

D flip-flop

Out

Clock

Fig. 4.2

Differentiator and rectifier. A positive pulse is generated for every input signal transition.

To handle different baud rates, the demodulator is clock and logic programmable. For using 1200
baud fsk, a 223721 Hz clock is applied, which puts the SC-filter cutoff frequency at 438Hz. After
the SC filter, the output is sliced by the comparator, to produce the demodulated output.
This demodulator is as seen reconfigurable to several baud rates, whereby it may be an alternative
for the DSC-ASIC demodulator. The switched capacitor filter is, however, by nature technology
dependent, and further more it may become sensitive to digital line noise, if proper cautions are not
taken to minimize digital interference in the DSC ASIC.

4.1.2 Product demodulator

Instead of using a zero crossing detector for demodulation, Apfel proposes a more complex scheme
in which he performs the demodulation process all digitally by use of small digital signal processor
(DSP) cores /Apfel 84/. Apfel implements the system shown in Fig. 4.3

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Receive
Carrier

Page 25

Analog
Lowpass filter

ADC

Lowpass
filter

Bandpass
Filters

Decimation

AGC

Data

Decision

Interpolator

90 deg phase
shift at f c

Fig. 4.3

The modem receiver with its hardware pieces dedicated to perform demodulation.

Fig. 4.3 shows a block diagram of the DSP modem receiver. The analog lowpass filter eliminates
energy which may alias into the passband after sampling by the analog-to-digital converter. The
analog to digital converter operates at a 496 kHz sampling rate, which thereby reduces the burden
on the prefilter, which is only a single-pole RC lowpass filter.

Bidirectional Databus

Mux and
Tri-state drivers
load
sel
Shift
code

Write BUF

load

Data
RAM

Data buf
zero

Mux
Shift REG

sel

Mux

Temp REG

load

Add/Sub
Output latch

Fig. 4.4

Block diagram of the DSP modem ALU /Apfel 84/.

The decimator then reduces the sampling rate down to the basic ALU signal processing rate, and
following the decimator, a group-delay equalized bandpass filter removes out-of-band energy which
may corrupt the demodulation process. The bandpass filters as well as the decimation is all
performed in the Signal processor core shown in Fig. 4.4. From the band-pass filter, the signal is
fed trough an automatic gain control (AGC) which ensures that the received signal is of the proper
signal strength to perform the demodulation. After gain control the actual demodulation is
performed. The signal is passed trough a 90 deg. phase shift at fc (1700Hz) and is then multiplied
by it self. This principle is known as a product demodulator, but some theory books may also refer
to this principle as a quadrature demodulator, as the signal is modulated by its own quadrature.
However the term product demodulator will be used here.
The result from multiplication is a baseband term containing the desired digital information, and
a useless double frequency component, which is removed by the following lowpass filter. The
succeeding interpolator is included for accurately detecting the zero crossings, thus reducing phase
jitter.
This demodulator principle is closer to what can be used in the DSC Asic. The principle uses digital
signal processing extensively, and the analogue front end is based on analogue-to-digital converters.
Furthermore the signal processor core which executes the demodulator algorithm could be
multiplexed by constructing faster versions which are capable of executing both the demodulation
as well as a modulation algorithm. But unfortunately Apfel does not report any performance
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Chapter 4

characteristics for this demodulation principle, which could have made it an obvious choice for the
DSC Asic project. In particular since standard programmable Digital Signal Processors have become
available

4.1.3 Complex Signal Processing.

In 88 Fleige published an article concerning the properties of digital band pass filters for FSK
modems /Fleige 88/. In this paper Fleige takes a "step up in complexity" by using complex signal
processing to perform the FSK demodulation. The schematic for this principle is shown in Fig. 4.5
exp( j ot )

FSK input
Signal

Fig. 4.5

lowpass
filter

Bandpass
filter

Data out

Demod

The demodulator principle suggested by Fleige /Fleige 88/.

The FSK input signal in Fig. 4.5 is given by: /Fleige 88/
(4.1)
where u(t)=1 for mark and u(t)=-1 for space. This signal is first multiplied by exp(-jct) where c
is the center frequency between the to signal frequencies, i.e. 1700Hz for V.23. Both the real and
imaginary part of this frequency shifted signal are filtered by means of low-pass filters resulting in
the complex envelope signal.
(4.2)
From this signal it is possible to extract the original baseband signal u(t) by using the configuration
shown in Fig. 4.6.
cos(t)
Lowpass
filter
FSK

d
dt
+

s(t)

x(t)

input

u(t)

Data

Lowpass
filter

d
dt

sin( t)

Fig. 4.6

Detailed block diagram over the complex digital signal processing involved in the demodulation
process.

The derivation of the demodulation principle shown in Fig. 4.6 is as follows. Considering
differentiation of the signal x(t):
(4.3)
which can be manipulated to equal:
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(4.4)

I.e the imaginary part of this product is equal to the baseband signal u(t), which is the tasks
performed on the signal x(t) in Fig. 4.6.
Fleige reports this scheme to have only one problem, namely the distortion introduced in the lowpass filters, which is why he pais a lot of attention to constructing phase linear FIR filters and
sample reductions.

4.2 Summary
Three "historical" methods of FSK demodulation has been presented. Ideally the principles should
be simulated and compared in order to form a basis for comparison to the modem solution which
is to be constructed later. However due to the fact that all these demodulator circuits have been
optimized in the intervening years, for use in other industry products, it would be a doubtful task
to merely simulate these demodulator configurations and conclude upon this simulation. This is
because minor unreported improvements might have changed the picture partly or completely.
In stead the demonstrated demodulation principles are used as inspiration for defining a new OnLine arithmetic CORDIC based architecture for the demodulation process. This is treated in more
details in chapter 7, but before the idea can be presented it is necessary to gain some insight into
the subjects CORDIC and On-Line arithmetic. Therefore the following two chapters take a sort of
"jump to something completely different"1.

Which, as will be shown in chapter 7, is not that completely different.

M.Sc Thesis - 1994