GATE MAPPING AUTOMATION FOR ASYNCHRONOUS

NULL CONVENTION LOGIC CIRCUITS

ABSTRACT:
Design automation techniques are a key challenge in the widespread application of
timing-robust asynchronous circuit styles. A new methodology for mapping multi rail logic
expressions to NULL convention logic (NCL) gate library is proposed. The new methodology is
then compared to another recently proposed mapping approach, demonstrating that the new
methodology can further reduce the area and improve the delay of NCL circuits. Also, in contrast
to the original approach, only targets area reduction. The results show that, depending on the test
circuit.

EXISTING SYSTEM:
Delay-insensitive circuits impose no timing assumptions, allowing arbitrary gate and
Wire delays. Unfortunately, the class of DI implementations is limited and impractical.Quasidelay-insensitive circuits partition wires into critical and noncritical categories. Designers of
such circuits consider forks in critical wires to be safe by assuming that the skew caused by their
wire delays is less than the minimum gate delay. Designers thus assume these wires to be
isochoric. In contrast, noncritical wires can have arbitrary Delays. Speed-independent circuits let
gates have any length of delay, but wire delays must be negligible.

EXISTING SYSTEM TECHNIQUE:

Basic Boolean Gates

EXISTING SYSTEM DRAWBACKS:

Power consumption high

occupied area high

PROPOSED SYSTEM:
We address the problem of mapping multi-rail logic expressions to an NCL gate library,
which is a form of technology mapping for a certain class of NCL design flows. Mapping multirail logic expressions to NCL gates is also an essential part of a custom NCL design flow and, in
contrast to mapping a Boolean logic expression to a limited set of basic Boolean gates, an
efficient manual mapping of multi-rail logic expressions to 27 NCL gates is not trivial, especially
when the logic expressions contain many product term.

PROPOSED SYSTEM BLOCK DIAGRAM:

NCL IMPLEMENTATION:

PROPOSED SYSTEM TECHNIQUE (ALGORITHM):

NULL Convention Logic

Mapping Algorithm

PROPOSED SYSTEM ADVANTAGES:

Easy Design Reuse

Data communication

They avoid all issues related to distributing a clock signal reliably

SOFTWARE REQUIREMENT:

ModelSim6.4c

Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3/ Spartan 3AN

REAL TIME APPLICATION:

Industrial Designs

Encryption Decryption circuits

Low Power Arithmetic Design

FUTURE ENHANCEMENT:
We can design a Cryptography part using asynchronous null convention logic circuits.

ALTERNATE TITLES:
Title 1: Efficient Asynchronous Null convention logic circuits Implementation on FPGA
Title 2: Asynchronous Null convention logic circuits based on Gate mapping automation
Title 3: Realization of Asynchronous Null convention logic circuits Using Verilog HDL

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification)