DESIGN OF DIGIT-SERIAL FIR FILTERS: ALGORITHMS,

ARCHITECTURES AND A CAD TOOL

ABSTRACT:
In the last two decades, many efficient algorithms and architectures have been introduced
for the design of low complexity bit-parallel multiple constant multiplications (MCM) operation
which dominates the complexity of many digital signal processing systems. On the other hand,
little attention has been given to the digit-serial MCM design that offers alternative low
complexity MCM operations albeit at the cost of an increased delay. In this paper, we address the
problem of optimizing the gate-level area in digit-serial MCM designs and introduce high level
synthesis algorithms, design architectures.

EXISTING SYSTEM:
In Existing Design Wallace and modified Booth multipliers, have been proposed, the full
flexibility of a multiplier is not necessary for the constant multiplications, since filter coefficients
are fixed and determined beforehand by the DSP algorithms. Hence, the multiplication of filter
coefficients with the input data is generally implemented under shift adds architecture, where
each constant multiplication is realized using addition/subtraction and shift operations in an
MCM operation.

EXISTING SYSTEM ALGORITHM:

Partial product sharing

EXISTING SYSTEM DRAWBACKS:

PROPOSED SYSTEM:
In this proposed system, we initially determine the gate-level implementation costs of
digit-serial addition, subtraction, and left shift operations used in the shift-adds design of digitserial MCM operations. Then, we introduce the exact CSE algorithm that formalizes the gatelevel area optimization problem as a 01 integer linear programming problem when constants are
defined under a particular number representation. We also present a new optimization model that
reduces the 01 ILP problem size significantly and, consequently, the runtime of a generic 01
ILP solver.

PROPOSED SYSTEM BLOCK DIAGRAM:

DIGIT-SERIAL DESIGN OF SHIFT-ADDS IMPLEMENTATION

PROPOSED SYSTEM ALGORITHM:

Exact CSE algorithm

Exact GB algorithm

PROPOSED SYSTEM ADVANTAGES:

Area efficient

Delay efficient

Power-efficient

SOFTWARE REQUIREMENT:

ModelSim6.4c

Xilinx 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3/ Spartan 3AN

REAL TIME APPLICATION:

Digital signal processing (DSP) systems

High-performance filters

FUTURE ENHANCEMENT:
We will implement a FIR Filter design by new constant multipliers and will be compared
with the proposed Design.

ALTERNATE TITLES:
Title 1: Efficient Design of Digit-Serial Fir Filters Implementation on FPGA
Title 2: Design of Fir Filters Implementation based on Digit-Serial Algorithm
Title 3: Realization of Digit-Serial Fir Filters Using Verilog HDL

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification)