V4 Advantage5-DSP Seminar

DSP Design Techniques
for Best Performance,

Power and Cost
Niall Battson
DSP Divisional Marketing
Virtex-4 DSP Advantages

LOWER POWER
(1/12 the power of V-II Pro)
HIGHER
PERFORMANCE
(2x the performance of
V-II Pro)
Virtex-4
XtremeDSP
Solution
SLICE
REDUCTION
(All designs in this
presentation use at
least 50% less slices
than V-II Pro)
MAXIMUM FLEXIBILTY
(Opmode of the XtremeDSP Slice provides over )
Prepared by : Niall Battson (Xilinx) 2004
DSP Design Techniques 2
www.xilinx.com/dsp
Agenda
Virtex-4 Family
The Xtreme DSP Slice
Filter Techniques
Case Studies
Digital Up Converter
2-D
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The Virtex-4 Family
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Virtex-4 Family
Virtex-4 is the first Xilinx family to introduce three separate platforms optimized
for different application domains. This fundamental shift provided the greatest
silicon efficiency and optimal cost.
Virtex-4 LX
Platform
Optimized for
high-performance
Logic
Virtex-4 FX
Platform
Virtex-4 SX
Platform
Optimized for
Embedded Processing
and high-speed
Serial Connectivity
Optimized for
high-performance
Signal Processing
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Virtex-4 SX
Note:
The SX family emphasizes
Xilinx commitment to DSP
applications by providing a
strong skew toward to
dedicated arithmetic units
versus logic.
4VSX25
2,650 CLB
128 BRAM
128 XtremeDSP Slices
Largest device - 4VSX55
6,144 CLB
320 BRAM
512 XtremeDSP Slices
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The XtremeDSP Slice

(also known as DSP48)
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The XtremeDSP Slice

B
18
M REG
CE
D
36
18
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The XtremeDSP Slice

B REG
CE
D
Q
2-Deep
18
M REG
CE
D
36
A REG
CE
D
Q
2-Deep
18
500 MHz maximum frequency in the fastest speed grade

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The XtremeDSP Slice

BCOUT
B REG
0
1
18
CE
D
Q
2-Deep
Subtract
18
M REG
CE
D
36
P REG
A REG
CE
D
Q
2-Deep
CE
D
18
48
CarryIn
48
BCIN

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The XtremeDSP Slice

PCOUT
BCOUT
B REG
0
1
18
CE
D
Q
2-Deep
Subtract
18
M REG
CE
D
36
P REG
A REG
CE
D
Q
2-Deep
CE
D
18
48
CarryIn
48
48
48
PCIN
BCIN

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The XtremeDSP Slice

PCOUT
BCOUT
A:B
36
48
B REG
0
1
18
CE
D
Q
2-Deep
Subtract
18
M REG
CE
D
A REG
CE
D
Q
2-Deep
72 36 0
36
P REG
CE
D
18
0
17-bit shift
17-bit shift
48
CarryIn
48
7
OpMode
48
48
PCIN
BCIN

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Dynamically Reconfigurable
DSP OPMODEs
OpMode
Zero
Hold P
A:B Select
Multiply
C Select
Feedback Add
36-Bit Adder
P Cascade Select
P Cascade Feedback Add
P Cascade Add
P Cascade Multiply Add
P Cascade Add
P Cascade Feedback Add Add
P Cascade Add Add
Hold P
Double Feedback Add
Feedback Add
Multiply-Accumulate
Feedback Add
Double Feedback Add
Feedback Add Add
C Select
Feedback Add
36-Bit Adder
Multiply-Add
17-Bit Shift P Cascade Select
17-Bit Shift P Cascade Feedback Add
17-Bit Shift P Cascade Add
17-Bit Shift P Cascade Multiply Add
17-Bit Shift P Cascade Add
17-Bit Shift P Cascade Add Add
17-Bit Shift Feedback
17-Bit Shift Feedback Feedback Add
17-Bit Shift Feedback Add
17-Bit Shift Feedback Multiply Add
17-Bit Shift Feedback Add
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
Z
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
4
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
Y
3 2
0 0
0 0
0 0
0 1
1 1
1 1
1 1
0 0
0 0
0 0
0 1
1 1
1 1
1 1
0 0
0 0
0 0
0 1
1 1
1 1
1 1
0 0
0 0
0 0
0 1
0 0
0 0
0 0
0 1
1 1
1 1
0 0
0 0
0 0
0 1
1 1
X
1 0
0 0
1 0
1 1
0 1
0 0
1 0
1 1
0 0
1 0
1 1
0 1
0 0
1 0
1 1
0 0
1 0
1 1
0 1
0 0
1 0
1 1
0 0
1 0
1 1
0 1
0 0
1 0
1 1
0 1
0 0
1 1
0 0
1 0
1 1
0 1
0 0
Output
+/- Cin
+/- (P + Cin)
+/- (A:B + Cin)
+/- (A * B + Cin)
+/- (C + Cin)
+/- (C + P + Cin)
+/- (A:B + C + Cin)
PCIN +/- Cin
PCIN +/- (P + Cin)
PCIN +/- (A:B + Cin)
PCIN +/- (A * B + Cin)
PCIN +/- (C + Cin)
PCIN +/- (C + P + Cin)
PCIN +/- (A:B + C + Cin)
P +/- Cin
P +/- (P + Cin)
P +/- (A:B + Cin)
P +/- (A * B + Cin)
P +/- (C + Cin)
P +/- (C + P + Cin)
P +/- (A:B + C + Cin)
C +/- Cin
C +/- (P + Cin)
C +/- (A:B + Cin)
C +/- (A * B + Cin)
Shift(PCIN) +/- Cin
Shift(PCIN) +/- (P + Cin)
Shift(PCIN) +/- (A:B + Cin)
Shift(PCIN) +/- (A * B + Cin)
Shift(PCIN) +/- (C + Cin)
Shift(PCIN) +/- (A:B + C + Cin)
Shift(P) +/- Cin
Shift(P) +/- (P + Cin)
Shift(P) +/- (A:B + Cin)
Shift(P) +/- (A * B + Cin)
Shift(P) +/- (C + Cin)
Over 40 Different Modes

- Each XtremeDSP Slice
individually controllable
- Change operation in a single
clock cycle
- Enables resource sharing for
maximum utilization
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Dynamic Opmode
Complex Multiplier
(a+jb).(c+jd) = [a.c - b.d] + j[b.c + a.d]

B REG
18
B
sel1
M REG
P REG
CE
D Q
CE
D Q
CE_R
CE
D Q
REAL
CE_I
CE
D Q
IMAG
A REG
18
CE
D Q
CE
D Q
0
sel2
Opmode
CLK Cycle Function
OPMODE
Sub
Sel1
Sel2
CE_R
Sub
CE_I
Performance
400 Mhz
Size:
1 XDSP Slice
59 Slices
(5 for control)
NOTE: Control signals can be stored in a Disributed Memory

www.xilinx.com/dsp
Dynamic Opmode
Complex Multiplier

B REG
18
B
sel1
M REG
P REG
CE
D Q
CE
D Q
CE_R
CE
D Q
REAL
CE_I
CE
D Q
IMAG
A REG
18
-BxD+0
BxD
CE
D Q
CE
D Q
0
sel2
Opmode
CLK Cycle Function

1
Multiply Subtract
OPMODE
Sub
0001010
Sel1
Sel2
Sub
CE_R
CE_I
Performance
400 Mhz
Size:
1 XDSP Slice
59 Slices
(5 for control)

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Dynamic Opmode
Complex Multiplier

B REG
18
B
sel1
- BA.C
x D++(-B.D)
0
A
BxC
D
CE
D Q
M REG
P REG
CE
D Q
CE
D Q
CE_R
CE
D Q
REAL
CE_I
CE
D Q
IMAG
A REG
18
CE
D Q
0
sel2
Opmode
CLK Cycle Function
OPMODE
Sub
Sel1
Sel2
Sub
CE_R
CE_I
Multiply Subtract
0001010
Multiply Accumulate
0101010
Performance
400 Mhz
Size:
1 XDSP Slice
59 Slices
(5 for control)

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Dynamic Opmode
Complex Multiplier

B REG
18
B
sel1
- BA.C
B.C
x+D0++(-B.D)
0
AxC
B
D
CE
D Q
M REG
P REG
CE
D Q
CE
D Q
CE_R
CE
D Q
REAL
CE_I
CE
D Q
IMAG
A REG
18
CE
D Q
00
sel2
Opmode
CLK Cycle Function
OPMODE
Sub
Sel1
Sel2
Sub
CE_R
CE_I
Multiply Subtract
0001010
Multiply Accumulate
0101010
Multiply
0001010
Performance
400 Mhz
Size:
1 XDSP Slice
59 Slices
(5 for control)

www.xilinx.com/dsp
Dynamic Opmode
Complex Multiplier

B REG
18
B
sel1
A.D
- BA.C
B.C
x+D0B.C
++(-B.D)
0
A
BxD
C
CE
D Q
M REG
P REG
CE
D Q
CE
D Q
CE_R
CE
D Q
REAL
CE_I
CE
D Q
IMAG
A REG
18
CE
D Q
00
sel2
Opmode
CLK Cycle Function
OPMODE
Sub
Sel1
Sel2
Sub
CE_R
CE_I
Multiply Subtract
0001010
Multiply Accumulate
0101010
Multiply
0001010
Multiply Accumulate
0101010
Performance
400 Mhz
Size:
1 XDSP Slice
59 Slices
(5 for control)

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XtremeDSP Slice Cascade

BCOUT
XtremeDSP Slices can be

cascaded together with direct
dedicated interconnect from slice
to slice. A Columns length
determined by the number of
XtremeDSP Slices in the column
PCOUT
B
C
A
P
XtremeDSP Tile
B
C
C Input is shared between two

XtremeDSP Slices or a single
tile. Be careful to select
algorithms that do not depend
on a C input for each
XtremeDSP Slice
A
P
BCIN
PCIN
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Cascade All XtremeDSP Slices Within a Column
DSP48 Slice Power Consumption

Virtex-II
Virtex-II
~47
~47 mW/100MHz
mW/100MHz
90.0
80.0
Virtex-II
Virtex-II Pro
Pro
~39
~39 mW/100MHz
mW/100MHz
70.0
A
verageP
ow
er(m
W
)
60.0
50.0
40.0
30.0
Virtex-4
Virtex-4
3.3
3.3 mW/100MHz
mW/100MHz
20.0
10.0
0.0
0
100
200
300
400
Fre que ncy (M Hz)
500
600
Conditions: TT, 25C, nominal voltage, Fully pipelined multiply-add mode, random vectors
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DSP48 Power Test for 63 Tap FIR Filter

(Stratix II EP2S60 and Xilinx Virtex-4 XC4VLX60)
Description
Test using 63 section

asymmetrical taps with 18 bit
data stream and fixed 18 bit
coefficients. Virtex-4 uses 63
DSP48 blocks all in a single
column. Stratix II uses 4 tap
sections in a DSP block.
Reconciling summation of 4
tap chunks is handle by
Stratix II 3 input adders in
layers of 6, 2, and 1. Same
Stimulus VHDL code.
Virtex-4 Logic
Functions
64 DSP48 and 0 Slices (1 DSP

Block used as stimulus of the
filter)
Stratix II Logic
Functions
128 9 Bit DSP Elements and

187 ALMs (1/4 of 1 DSP Block
is used as a stimulus for the
filter)
1.35 W
2.35x
>> 11 Watt
-4 and
-II
Watt of
of power
power difference
difference between
between Virtex
Virtex-4
and Stratix
Stratix-II
in
in DSP
DSP Applications
Applications
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Measured 1024 Point FFT Power

(Stratix II EP2S60 and Xilinx Virtex-4 XC4VLX60)
Description
Test is on a streaming 1024

Point FFT. Test uses small
amount of DSP48 block in
Virtex-4 and equivalent
processing in Stratix II.
Design has several thousand
LUTs, registers and block
RAM.
Virtex-4 Logic
Functions
2548 Slices, 17 DSP48s, and 9

BlockRAM
1W
1.07x
Stratix II Logic
Functions
2917 ALMS, 38 M4K Blocks, 2

M512 Blocks, and 24 - 9 Bit
DSP Elements
>> 11 Watt
-4 and
-II
Watt of
of power
power difference
difference between
between Virtex
Virtex-4
and Stratix
Stratix-II
in
in DSP
DSP Applications
Applications
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Filter Techniques
For this analysis the software used was:
ISE 7.1.1i
Quartus 4.1 sp1
FIR Compiler 3.2.1
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The FIR Filter

The most common DSP function implemented in a Xilinx devices is
the Finite Impulse Response filter:
Viewed as an Equation
Coefficients
i=N-1
Y(n) =
i=0
Viewed as a Diagram
ki.X(n-i)
Accumulate
N times
Z-1
Z-1
Z-1
Z-1
k0
k1
k1
k3
kN-1
Delay
Coefficient
Multiply
X(n)
Multiply
Y(n)
Summation
How do we implement these filter in Virtex-4?
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Sequential FIR Filters

500
400
300
200
Sample Rate (Mhz)

Log Scale
100
50
10
5
1
0.5
1
10
20
50
200
100
500
Number of Coefficients (N)
Firstly consider one multiplier

based FIR Filters.
Processing of the filter
coefficients is done in a
sequential fashion
Line is where this architecture
can no longer meet
performance requirements
Line has been raised in
Virtex-4 due to higher clock
performance of Xtreme DSP
Slice
1000
Log Scale
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Virtex-4 MAC FIR Filter

Filter Specification: Sampling Frequency = 1.2288 Mhz, Coefficients = 366
input registers, output and
pipeline registers save 59
slices over Virtex-II Pro
Dual Port Memory is used

for data and coefficient
storage. Use in Read after
Write mode for required
performance
20
DSP48 Slice
opmode = 0100101
18
xn
Input Data
366 x 18
CE
Data Addr
we
Control
Coef Addr
Coefficients
366 x 18
Control logic creates the

required cyclic RAM buffer in
the data memory
Latency on load signal

matches filter latency
Clock Rate
Number of Taps
45
Load
opmode (5)
Load signal is required to

start a new output sample
computation. Inverter
required
Performance:
392 MHz (-10)
Size:
1 XDSP Slice
1 Block RAM
45 Slices
yn
23
z-4
Max Sample Rate =
Capture register still

required, although can be
reduced in size when
rounding or truncation are
used
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Stratix-II MAC FIR Filter

Load
M4K (512 x 9) x2
xn
18
Input Data
366 x 18
CE
Data Addr
we
Control
Coef Addr
Latency matching registers are built into

the DSP Block
Coefficients
366 x 18
45
yn
The second multiplier

can only be used in
multiply accumulate
M4K (512 x 9) x2
M4K are too small to store

all the coefficients in a single
block. Hence 4 are required
for data and coefficients
Performance:
217 MHz (-5)
Size:
1 DSP Block (1 Mult)
4 M4K
659 ALMs
When multiply accumulate

mode is used, two of the
multipliers are wasted
DSP Block
opmode = MULTACCUM
45%
45% Slower
Slower
Performance
Performance
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Parallel FIR Filters

500
400
300
200
Sample Rate (Mhz)

Log Scale
100
50
10
5
1
0.5
1
10
20
50
200
100
500
Now consider one multiplier

per coefficient
coefficients is done in a
parallel fashion
Line is where this architecture
is required as less than 2 clock
cycles are available
Slice
1000

Log Scale
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Virtex-4 Systolic FIR Filter

Filter Specification: Sampling Frequency = 400 Mhz, Coefficients = 23
Input time delay series is created
inside the DSP Slice for maximum
performance irrespective of the
number of coefficients
x(n)
Coefficients are
from left to right.
This causes the
latency to be as
large and grow
with the increase of
coefficients
This filter structure while referred to

as a Systolic FIR filter, it is really a
Direct Form with one extra stage of
pipelining
18
K0
K1
K2
K21
K22
DSP48 Slice
opmode = 0000101
Max Sample Rate = Clock Rate
41
DSP48 Slice
opmode = 0010101
Dedicated cascade
connections (PCOUT
and PCIN) are exploited
to achieve maximum
performance
Performance:
400 MHz (-10)
Size:
23 XDSP Slice
y(n)
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Stratix-II Parallel FIR Filter

Filter Specification: Sampling Frequency = 400 Mhz, Coefficients = 23
DSP Block
opmode = 4 MULTADD
x(n)
18
K0
K1
Full usage of the

DSP48 Blocks
relies on the
coefficients being
divisible by 4
K2
K3
K4
K5
K6
Fast 3-input adders make the large

adder trees much more resource
efficient
48%
48% Slower
Slower
Performance
Performance
K8
K7
K9
K10
The performance
bottleneck will still
always be the fabric
adder, which will greatly
limit performance
K11
Performance:
207 MHz (-5)
Size:
6 DSP Blocks
(23 Mults)
744 ALMs
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Semi-Parallel FIR Filters

500
400
300
200
Sample Rate (Mhz)

Log Scale
100
Semi-Parallel
FIR Filters
50
10
5
1
0.5
1
10
20
50
200
100
500
Now consider in between

scenario. Multiple coefficients
per multiplier (M).
coefficients is done in a semiparallel fashion
Boundary lines determined by
the other techniques
Slice
1000

Log Scale
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Virtex-4
4 Multiplier Systolic SP FIR
Filter Specification: Sampling Frequency = 74.176 MHz, Coefficients = 16

Input time delay series is created
outside the XtremeDSP Slice as
SRL16E are required to store the set
of inputs to drive each engine
x(n)
18
K0
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
20
CE
40
DSP48 Slice
opmode = 0000101
DSP48 Slice
opmode = 0010101
DSP48 Slice
opmode = 0010010
The adder chain pipeline register is compensated for in

the addressing of the memories. Hence each buffers
address is delayed by one clock cycle
Max Sample Rate =
The important thing to note about the

addressing is that each SRL16E and
coefficient memory buffer have
identical addressing
Clock Rate x Number of Multipliers

Number of Taps
An extra Xtreme DSP Slice

is require to accumulate the
results over the 4 clock
cycles required before the
slower capture register
grabs the final output
Performance:
400 MHz (-10)
Size:
5 XDSP Slice
104 Slices
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y(n)
4 Multiplier Systolic SP FIR

System Generator Implementation
Can even run hardware in

the loop on Virtex-4
today
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Stratix-II
4 Multiplier Semi-Parallel FIR
Filter Specification: Sampling Frequency = 74.176 MHz, Coefficients = 16
Accumulator will be in fabric.

This may be the critical path
in the design as fabric can not
run at the 450 MHz speed of
the DSP Block
18
x(n)
Input time delay series is

created with M512 memory
blocks. Control logic must
create a cyclic RAM buffer
4 x 18
4 x 18
4 x 18
4 x 18
40
CE
4 x 18
4 x 18
4 x 18
4 x 18
Coefficients stored in M512 as well. Rather wasteful as

Altera has no distributed memories
DSP Block
opmode = 4 MULTADD
36%
36% Slower
Slower
Performance
Performance
Performance:
256 MHz (-5)
Size:
1 DSP Block
(4 Multipliers)
188 ALMS
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y(n)
Multi-Channel Multi-Rate
FIR Filters
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Virtex-4
Multi-Channel Multi-Rate FIR
Filter Specification:
Input Frequency = 3.84 Mhz, Coefficients = 192, Interpolation Rate Change = 2,
Channels = 8, Data Width = 12-bit, Coefficient Width = 15-bits
Channel 1
96 Coefficient Phase Filter
34
12
CE

34
12
CE

Channel 8
Slicing up the Pie:

Total number of coefficients = 1536
96 x 16 is the coefficient Matrix:
Option 1:
16 Sequential MACC Engines
96 clk cycles, Clock Speed: 368 Mhz
Option 2:
1 Semi-parallel 12 Multiplier FIR
8 cycle per phase, 16 phases = 128 clk cycles
Clock Speed: 491.52 Mhz
Option 3: Increase coefficients to 196
1 Semi-parallel 14 Multiplier FIR
7 cycle per phase, 16 phases = 112 clk cycles
Clock Speed: 430.08 Mhz
www.xilinx.com/dsp
Virtex-4
x1(n)
Input Frequency = 3.84 Mhz, Coefficients = 192+4, Interpolation Rate Change = 2,
Channels = 8, Data Width = 12-bit, Coefficient Width = 15-bit
Input buffer holds 8 individual channels of 7
of values per channel
x2(n)
x3(n)
x4(n)
12
x5(n)
x6(n)
x7(n)
x8(n)
WE
WE1
Input Data
56 x 12
Input Data
56 x 12
Coefficients
112 x 15
Coefficients
112 x 15
Accumulator combines all

inner products together for
each channel in sequence
WE12
Input Data
56 x 12
136
Coefficients
112 x 15
y1(n)
y2(n)
24
y3(n)
y4(n)
34
y5(n)
y6(n)
DSP48 Slice1
opmode = 0000101
Embedded Control technique

is used to reduce slice count
Max Input Sample Rate =
DSP48 Slice
opmode = 0010101
DSP48 Slice14
opmode = 0010101
Addressing scheme is the Coefficient buffer holds 7

coefficients of each 16
same as the semi-parallel
individual phase filter
techniques we have learnt
about
Clock Rate x Number of Multipliers
Number of Taps x Number of Channels
DSP48 Slice
opmode = 0010010
Performance
447 MHz (-11)
Size:
15 XDSP Slice
14 Block RAM
233 Slices
(73 for control)
www.xilinx.com/dsp
y7(n)
y8(n)
Stratix-II
x1(n)
x2(n)
Each input time series buffer is a 40 x 12

memory that is a cyclic ram buffer. Control is
shared for every four buffers as speed
requirement is slower
12
x3(n)
40 x 12
x4(n)
x5(n)
40 x 12
x6(n)
x7(n)
x8(n)
Required Clock speed

is 295 MHz.
40 x 12
40 x 12
Input Mux is
the same size
as in Virtex-4
as there are
no F5MUXs
4 Mult / Add
DSP Block
Input time
series buffer
Input time
series buffer
Input time
series buffer
Input time
series buffer
4 Mult / Add
DSP Block
4 Mult / Add
DSP Block
4 Mult / Add
DSP Block
4 Mult / Add
DSP Block
3 input adders greatly help to

reduce the number of adders
in the adder tree
34
External Fabric adders are

always required to combine
DSP Block results
www.xilinx.com/dsp
Stratix-II
80 x 15
12
15
80 x 15
12
80 x 15
15
12
15
80 x 15 memories are required for the

coefficients. Each bank of four memories can
be addressed by the same counter as this is
a Direct Form Type I structure and speed
can still be met.
80 x 15
12
15
Performance
270 Mhz (-4)
Size:
5 DSP Blocks
(20 multipliers)
30 M4K Blocks
1271 ALMs
DSP Block
29
40%
40% Slower
Slower
Performance
Performance
www.xilinx.com/dsp
Case Study 1: DUC

DUC Specification:
Output Frequency = 450 MSPS
DDS: SFDR = 84dB, CIC: 5 Stage, Interpolation Rate = 1:16, CFIR: 32 Coefficients,
Interpolation Rate = 1:2, PFIR: 64 Coefficients, Interpolation Rate 1:2
PFIR
CFIR
CIC Filter
64 Tap, Interpolate by 2
Interpolate by 16
Input
DDS
cos (2..f1.t)
sin (2..f2.t)
PFIR
CFIR
CIC Filter
Interpolate by 16
Output
www.xilinx.com/dsp
DUC: Sysgen Model

CFIR
CIC Coarse
Gain
PFIR
CIC
Rounding
HIGHLIGHT BARREL SHIFTER

FOR COARSE GAIN MAYBE
SEPARATE FOIL
Subtraction
Mixing
DDS
www.xilinx.com/dsp
Case Study: DUC

DUC SIZE: (V-II Pro)
6 Embedded Mults
2,328 Flip-Flops
2,076 LUTs
10 Block RAM
Performance: 202 MHz
DUC SIZE: (V-4)
27 XDSP Slice
692 Flip-Flops
977 LUTs
10 Block RAM
Performance: >400 MHz
www.xilinx.com/dsp
Case Study 2: 2-D FIR

2-D FIR Specification:
Frame Rate = 60 Hz, Active Frame Size = 1440 x 1080, Single Channel
Separable FIRs : Sample Rate = 111.38 MSPS, 24 Tap Re-loadable, 10-bit Data,
Folding Factor = 4
l = + N
y (n, m ) = h0 (k ) h1 (l ).x(n k , n l )
k = N
l = N
l =+ N
k = + N
= h1 (k ) h0 (l ).x(n k , n l )
l = N
k = N
k =+ N
Vertical
Line Buffer
Vertical Filter
24 Tap
Horizontal Filter
24 Tap
www.xilinx.com/dsp
Case Study 2: Vertical FIR &

Line Buffer
Note: The Semi-Parallel Systolic

Filter forms the foundation for both of
the filters.
Vertical Line Buffers are formed out

of Single Port Block RAMs using a
cyclic RAM buffer
x(n)
10
1440 x 10
1440 x 10
1440 x 10
16 x 10
16 x 10
16 x 10
1440 x 10
5
16 x 10
13
Reloadable
Coefficients
CE
26
DSP48 Slice1
opmode = 0000101
Vertical FIR Size:

7 XDSP Slice
43 Slices + Control
30 Block RAM
DSP48 Slice2
opmode = 0010101
DSP48 Slice4
opmode = 0010101
DSP48 Slice6
opmode = 0010101
6 multipliers are required to process the

data stream
Re-loadable Coefficient memories

created out of small Dual Port
Distributed Memories
Number of Multipliers =
Input Sample rate x Number of Taps

Clock speed
DSP48 Slice
opmode = 0010010
111.38 x 24
450
= 5.94
www.xilinx.com/dsp
y(n)
Case Study: 2-D FIR
2-D FIR SIZE: (V-II Pro)

12 Embedded Mults
1,325 Flip-Flops
890 LUTs
30 Block RAM
Performance: 229.8 MHz
2-D FIR SIZE: (V-4)

15 XDSP Slice
560 Flip-Flops
414 LUTs
30 Block RAM
Performance: 446 MHz
www.xilinx.com/dsp
Conclusion - The Check List

Is the design running as fast as possible?
(500 Mhz for fastest speed grade. 50% faster that Stratix-II.
Resources can be saved by making sure the design runs at full
speed.)
Is the XtremeDSP Slice being utilized fully?

(Fabric slices can be saved by better exploiting the Xtreme DSP Slice
which leads to less power. Greater than 1 Watt less power that Stratix-II)
(The XtremeDSP Slice is designed to support adder cascades)
www.xilinx.com/dsp
9
9
Are Adder Chains being used instead of trees?
Knowledge is Power
The next best thing to knowing something is knowing where to find it
- Samuel Johnson
5 Application Notes available in the
Virtex-4 User Guide in regard to
implementation specifics
Many Reference Designs in:
VHDL
Verilog
System Generator for DSP
For Further Details visit..
www.xilinx.com/dsp
www.xilinx.com/dsp
Knowledge is Power
The desire of knowledge, like the thirst of riches, increases ever with
the acquisition of it. - Sterne
Embedded Control MACC FIR

Care must be ta ken in setting up
the m emory, especially the initial
value s so that the addressing
kick starts
Address signal is feedback

and its va lue must always
point to the next requ ired
address
Load signal is the MSB on

the coef/control memory
space and the required
latency is already in the
signal
Load
opmode (5)
Sampling Frequency = 1.2288 Mhz, Coefficients = 104, Channels = 3
Control Coefficients
117 x 10 117 x 18
WE
18
xn
Colo urs rep resents the different

chan nels going through the filte r.
Each filter is processed o ne a t a
D Q
timeyninst ead of interleaved
43
Tim e Divisio n Mu lt iplexing of

the num erous chan nels is
perform ed wit h a mux running
at C times faster than the
input
Input Data
117 x 18
Counter
CE
The o utpu t mu x wou ld most

likely ta ke the form of a ba nk
of ca pture registers tha t are
en abled as appropriate
CE
Four dimensions?
DSP48 Slice
opmode = 0100101
23
data
addr
x1(n)
4
Cont rol logic is reduced
to only a counter
Max Sample Rate =
2 DSP Courses:
Exploiting many slow data streams
Coef Addr
Clock Rate
Number of Taps
The A port is a
concatenation of the
coefficients, coefficient
address, WE, CE and
Load signals
DSP48
18Slice
opmode = 0100101
x2(n)
Filter Size:
y1(n)
1 XDSP SliceTranspose FIR
y2(n)
0
44
1 Block 50RAM
y3(n)
40 0
Systolic
FIR FIR
(symmetric
Parallel
Filters & non)
28 Slices
30 0
66
opmode (5)
20 0
he re as it has to accomm odate
Load
Increasing
10z0
Semi-Parallel
Filter Size:
1
Xi li nx C
on fide
n ti aldata stre am. The
the
TDM
No. of Multipliers
50
Dist
Mem FIR
embedd ed con tro l can also be
1 XDSP
Slice
1
10
used .
1 Block
RAM
Semi-Parallel
116 Slices
1
Clock Rate
BRAM FIR
Ma x Sample Rate =
(30 for control)
Numbe r o f Taps x Number of Channels
Embedded
x3(n)
More than 256 coefficients

Data Addr
we
18 than 9 bit
at greater
data
Control
Addr
requires more BlockCoef
RAM
and traditional control
should 30
be used
The con tro lteischnique
a little t rickier
Coefficients
104 x 18
-3
0.1
Dist Mem
MACC FIR
Sample Rate (Mhz)
P rep ared b y : Ni al l B at tson (Xi il nx ) 2 00 4
0.01 Xilinx Confidential
Control
MACC FIR
Normal Control
MACC FIR
P rep are d by : Ni al l B att so n (Xil ni x) 20 04
0.00 1
10 20 30 40
50 60 70
80 90
10 0
20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 0
10 00
Time to put everything

together!
Consider Multi-Channel
Multi-Rate FIR Filters
together
How do the Boundary lines

change as the interpolation
or decimation rate
increases?
Numbe r o f Coefficients (N)

Log Scale
P rep are d by : Ni al l B att so n (Xil ni x) 20 04
For Further Details Contact..
MySupport.xilinx.com
- DSP Implementation
Techniques (3 day)
Xilinx Confidential
Over 500
Pages
- DSP Design Flow (3 day)

To educate students on efficient
DSP design in Xilinx FPGAs
using the latest system level
design tools
www.xilinx.com/dsp

V4 Advantage5-DSP Seminar

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DSP Design Techniques

for Best Performance,

Virtex-4 DSP Advantages

DSP Design Techniques 2

Prepared by : Niall Battson (Xilinx) 2004

DSP Design Techniques 3

The Virtex-4 Family

Prepared by : Niall Battson (Xilinx) 2004

DSP Design Techniques 4

Prepared by : Niall Battson (Xilinx) 2004

DSP Design Techniques 5

128 XtremeDSP Slices

Largest device - 4VSX55

512 XtremeDSP Slices

Prepared by : Niall Battson (Xilinx) 2004

DSP Design Techniques 6

The XtremeDSP Slice

Prepared by : Niall Battson (Xilinx) 2004

DSP Design Techniques 7

The XtremeDSP Slice

Prepared by : Niall Battson (Xilinx) 2004

DSP Design Techniques 8

The XtremeDSP Slice

500 MHz maximum frequency in the fastest speed grade

DSP Design Techniques 9

The XtremeDSP Slice

500 MHz maximum frequency in the fastest speed grade

DSP Design Techniques 10

The XtremeDSP Slice

500 MHz maximum frequency in the fastest speed grade

DSP Design Techniques 11

The XtremeDSP Slice

500 MHz maximum frequency in the fastest speed grade

DSP Design Techniques 12

Over 40 Different Modes

Prepared by : Niall Battson (Xilinx) 2004

DSP Design Techniques 13

(a+jb).(c+jd) = [a.c - b.d] + j[b.c + a.d]

CLK Cycle Function

NOTE: Control signals can be stored in a Disributed Memory

DSP Design Techniques 14

(a+jb).(c+jd) = [a.c - b.d] + j[b.c + a.d]

CLK Cycle Function

NOTE: Control signals can be stored in a Disributed Memory

DSP Design Techniques 15

(a+jb).(c+jd) = [a.c - b.d] + j[b.c + a.d]

CLK Cycle Function

NOTE: Control signals can be stored in a Disributed Memory

DSP Design Techniques 16

(a+jb).(c+jd) = [a.c - b.d] + j[b.c + a.d]

CLK Cycle Function

NOTE: Control signals can be stored in a Disributed Memory

DSP Design Techniques 17

(a+jb).(c+jd) = [a.c - b.d] + j[b.c + a.d]

CLK Cycle Function

NOTE: Control signals can be stored in a Disributed Memory

DSP Design Techniques 18

XtremeDSP Slice Cascade

XtremeDSP Slices can be

C Input is shared between two

DSP Design Techniques 19

Cascade All XtremeDSP Slices Within a Column

DSP48 Slice Power Consumption

DSP Design Techniques 20