CONTENTS

1. STANDARDIZATION OF PACKAGES
1.1 EIAJ Standards
1.2 JEDEC Standards
1.3 IEC Standards

2. NAME'S OF NEC'S PACKAGES

3. PACKAGE CODES BY EIAJ
3.1 Construction of package code

4. DIMENSION SYMBOL AND EXAMPLE DIMENSIONS

4.1 Example of dimensions of packages
4.2 Dimension Symbols
4.2.1 Reference dimensions by "true geometric location"
4.2.2 Dimensional indication by geometric tolerance
4.2.3 X (Tolerance of terminal center)

5. PACKING OF PACKAGES
5.1 Packing Style and Notes
5.1.1 Packing style
5.1.2 Notes on hanging
5.2 Dimension of tapings
5.2.1 Taping for SOP/TSOP
5.2.2 Taping for SOJ
5.2.3 Taping for QFJ
5.2.4 Taping for QFP

 The information in this document is subject to change without notice. Before using this document,
please confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or of others.
Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
M7A 98. 8

INTRODUCTION
Packages for semiconductor products have been diversified and become more complicated in recent years chiefly
because these packages have a significant clue to increasing the density of the electronic systems where they and
the semiconductor products they house are employed.
Take IC products for example. The Through Hole Device (THD), whose representative package has been the Dual
In-line Package (DIP), have increasingly employed newly developed packages such as those with shrunk lead pitches,
Zig-zag In-line Packages (ZIP), Quad In-line Packages (QUIP), and Pin Grid Array packages (PGA), in order to
contribute to increasing the density on the PC board on which the device is to be mounted. In addition, in order to
satisfy the demands for compact and slim packages, Surface Mount Device (SMD) packages such as Small Outline
Packages (SOP), Quad Flat L-leaded Packages (QFP), Quad flat J-leaded Packages (QFJ), Surface Vertical Package
(SVP) and Ball Grid Array (BGA) have been developed and increasingly made their way through the market.
This manual is to describe the packages of the THDs and SMDs, including their dimensions and packing style,
in order to deepen your understanding on these diversified packages. It is recommended that you also refer to
Semiconductor Device Mounting Technology Manual (C10535E) separately available.
April, 1999

NEC Corporation

1.

STANDARDIZATION OF PACKAGES
It is necessary that the packages be standardized by the manufacturers so that they are easy to use for the users.

Therefore, NEC standardizes its packages by exchanging opinions with the users, related system manufacturers, and
parts supplier, and by actively participating in various activities for standardization.
These activities for standardization of packages, as shown in the figure below, are developed in Japan, the United
States, and European nations. The international standardization activities are promoted by the Semiconductor
Devices Sub-committee 47D (SC47D) of the Technical Committee (TC-47) of the International Electrotechnical
Commission (IEC). In Japan, these activities are organized by the Technical Standardization Committee on
Semiconductor Device Package (EE-13), the subcommittees of the subordinate organizations of the Electronic
Industry Association of Japan (EIAJ).
In the United States, an organization for semiconductor packages (JC-11) of the Joint Electronic Device Committee,
a subordinate organization of the Electronic Industry Association, is mainly responsible for the standardization
activities.
These standardization activity organizations are shown in Fig. 1-1. The activities of each organization are
periodically conducted and actively promoted.

Fig. 1-1 Standardization Activity Organizations

World
IEC; TC-47, SC47D
(Deliberation: 2 times/year)

International
Electrotechnical
Commission

Committee in Japan

Committee in U.S.A

Committee in each country

EIAJ
Technical Standardization Committee
on Semiconductor Device Package; EE-13
(Deliberation: Once/2 months)

EIA
JEDEC; JC-11
(Deliberation: 4 times/year)

Standardization organization
in each country

Sub-Comittee on Plastic Package

Sub-Committee on Ceramic Package
Sub-Committee on Discrete Semiconductor Package
Sub-Committee on Semiconductor Packing
Sub-Committee on Area Array Package
Sub-Committee on IEC/SC47D matters

EIAJ

: Electronic Industries
Association of Japan
: Electronic Industries
EIA
Association
JEDEC : Joint Electron Device
Engineering Council

1.1

EIAJ Standards

The EIAJ standards are enacted by the Technical Standardization Committee on Semiconductor Device Package
(EE-13), which consists of semiconductor manufacturers, package manufacturers, socket manufacturers, and so on.
The major standards related to packages and enacted by this committee are as follows:
Remark

The standards in the following lists are readily available from the Electronic Industry Association of
Japan(EIAJ).
Electronic Industry Association of Japan
5-13, Nishi-shinbashi 1-chome, Minato-ku, tokyo 105, Japan
Public Affaires Office
Phone: +81-3-3213-5861/FAX: +81-3-3213-5863

EIAJ Standard (1/4)

(1) General Rule of Semiconductor Device Package
Number

EIAJ Standard

Registration

ED-7300

Recommended practice on standard for the preparation of outline drawing of

semiconductor packages

1997.08

ED-7301

Manual for the standard of integrated circuits package

1996.12

ED-7302

Manual for integrated circuits package design guideline

1997.04

ED-7304

Measuring Method for Package Dimensions of Ball Grid Array(BGA)

1997.05

ED-7304-1

Measuring Method for Package Dimensions of Small Outline Package(SOP)

1997.03

ED-7305

Unit Design Guide for the Preparation of

Package Outline Drawing of Integrated Circuits(Gullwing-lead)

1997.04

ED-7400

Standard for the dimensions of semiconductor devices (Integrated Circuits)

1990.09

ED-7400-1

Standard for the dimensions of semiconductor devices (Integrated Circuits)

1990.09

ED-7400-2

Standard for the dimensions of semiconductor devices (Integrated Circuits)

1991.06

ED-7401-2

Package name and code for semiconductor device package(Integrated Circuits)

1994.06

ED-7401-4

Method of measuring semiconductor device package dimensions(Integrated Circuits)

1995.05

ED-7441B

Standard for the packages of universal Memory-devices

1998.03

ED-7500A

Standard for the deimensions of semiconductor devices (Discrete semiconductor devices)

1996.07

EIAJ Standard (2/4)

(2) Standard of integrated circuits package
Number

EIAJ Standard

Registration

ED-7311

Standard of integrated circuits package(QFP)

1997.05

ED-7311-1

Standard of integrated circuits package [TSOP(I)]

1997.08

ED-7311-2

Standard of integrated circuits package [TSOP(II)]

1997.08

ED-7311-3

Standard of integrated circuits package (1.0mm pitch T-FBGA)

1997.08

ED-7311-4

Standard of integrated circuits package (1.27mm pitch T-FBGA)

1997.08

ED-7311-5

Standard of integrated circuits package (32/48-pin FBGA)

1998.04

ED-7311-6

Standard of integrated circuits package (60/90-pin FBGA)

1998.04

ED-7311-9

Standard of integrated circuits package [P-BGA(C/U type)]

1998.03

ED-7311-10

Standard of integrated circuits package [P-BGA(C/D type)]

1998.03

ED-7311-11

Standard of integrated circuits package (119/153-pin P-BGA)

1998.03

EIAJ Standard (3/4)

(3) General Rules for the Preparation of Outline Drawings of Integrated Circuits
Number

EIAJ Standard

Registration

ED-7402-1

Small Outline Package SOP

1989.02

ED-7403-1

Plastic Dual In-line Package DIP

1988.04

ED-7405

Zigzag In-line Package ZIP

1991.10

ED-7405-1

Shrink Zigzag In-line Package SZIP

1990.03

ED-7406A

Small Outline J-leaded Package SOJ

1995.05

ED-7407

Quad Flat J-leaded Package QFJ

1988.06

ED-7408A

Pin Grid Array PGA

1994.02

ED-7409

Quad Flat I-leaded Package QFI

1988.06

ED-7410

Small Outline I-leaded Package SOI

1988.06

ED-7412

Quad Flat lead-less Package QFN

1988.06

ED-7413

Single In-line Package SIP

1989.01

ED-7414

Guard ring Quad Flat Package GQFP

1989.11

ED-7415

Small Outline Package with Heat sink HSOP

1989.11

ED-7417

Bumpered Quad Flat Package BQFP

1990.02

ED-7418

Glass seal Quad Flat Package QFP-G

1990.07

ED-7419

Glass seal Dual In-line Package DIP-G

1990.07

ED-7421

Ceramic Dual In-line Package DIP-C

1991.10

ED-7422

Glass seal Quad Flat J-leaded Package QFJ-G

1992.10

ED-7423

Ceramic Quad Flat J-leaded Package QFJ-C

1993.02

ED-7424

Surface Vertical Package SVP

1993.12

ED-7431A

Quak Tape carrier Package QTP

1994.10

ED-7432

Dual Tape carrier Package (Type I)(DTP I)

1993.12

ED-7433

Dual Tape carrier Package (Type II)(DTP II)

1993.12

EIAJ Standard (4/4)

(4) Design guideline of integrated circuits
Number

EIAJ Standard

Registration

EDR-7311

Quad Flat Package(QFP)

1996.04

EDR-7312

Thin Small Outline Package (Type I)(TSOP I)

1996.04

EDR-7313

Thin Small Outline Package (Type II)(TSOP II)

1996.04

EDR-7314

Shrink Small Outline Package (SSOP)

1996.08

EDR-7315

Balll Grid Array (BGA)

1997.05

1.2

JEDEC standards

The JEDEC standards are deliberated by a semiconductor package-related activity organization (JC-11), a
subordinate organization of the EIA, and is enacted in the sequence in which the standards are registered, with a
type name given.
Example
Outlines/Registrations
DO-: Diode Outlines
TO-: Transistor Outlines
CO-: Carrier Outlines
UO-: Uncased Outlines
MO-: Microelectronic Outlines
Standards
TS-:

Transistor Standard

GS-: Gauge Standard

CS-: Carrier Standard
US-: Uncased Standard
MS-: Microelectronic Standard

1.3

IEC standards

The IEC standards are internationally standards deliberated and enacted based on the proposals extended from
the standardization activity organizations of the major countries producing semiconductor devices.
Here are examples of the IEC standards:
IEC-Publication-148

Character codes of semiconductor elements and integrated circuits

IEC-Publication-191

Package standardization of semiconductor elements and integrated circuits

IEC-Publication-747

Ratings and characteristics of semiconductors and measuring methods

IEC-Publication-286.3

Parts packing style for automatic mounting

2.

Names of NECs Packages

NEC indicates the names of its packages in the following format:
(2)

(1)

Number of pins

(Ex.)

16 pin
32 pin
160 pin
32 pin
72 pin

Material

Plastic
Plastic
Plastic
Ceramic
Ceramic

(3)

(4)

(5)

(6)

PKG style (1)

(option)

PKG style (2)

Supplement
(option)

Nominal
dimensions
(option)

S
T
W

DIP
SOP
QFP
QFN
PGA

(Straight)
(Glass sealed)

(300 mil)
(8 14)
(28 28)

(1) Number of pins

In principle, the number of pins based on the pin pitch is indicated, i.e., the number of pins includes the missing
pins.
The pin for preventing insertion in the wrong direction is not included in the number of pins of the PGA.
In case the outermost pin is not drawn out, the above principle may not be observed.

(2) Material
The sealing materials of the package are indicated.
To distinguish between the glass sealed and seal ring products and between the cerdip and seam weld
products, a code is indicated at the position of (5) Supplement.
Example 28-pin ceramic DIP (cerdip) (300 mil)
72-pin ceramic PGA (Glass sealed)

(3) Package style (1) (option)

The following codes are indicated for the package that has the features which cannot be indicated by package
style (2):
Example S (Shrink). . . . Reduced pin pitch
T

. . . . Thin

. . . . With window

(4) Package style (2)

The most appropriate of the following codes is indicated:
Example DIP, SOP, QFP

(5) Supplement (option)

Information that supplements the code of package style (1) and package style (2) is indicated.
Example (straight)
(Glass sealed)

3.

Package Codes by EIAJ

The EIAJ regulates the names and codes of the package by its Integrated Circuit Dimension Rule Package Name

and Code ED7303, as follows:

3.1 Package code configuration
Package Code is configured by 6-item below, and maximum of 30 letters shall be specified.

(1)

(2)

(3)

(4)

(5)

(6)

(1) Material code of package body

1 letter shall be specified.
C: Multi-layer ceramic package
G: Glass sealed ceramic package
M: Package consisting of metallic materials
P:

Package molded with plastic

R: Package consisting of plastic/glass composite substrate

T:

Package consisting of tape

(2) Package specific feature code

Maximum of 3 features shall be specified. (Maximum of 3 letters)
1

Outline addition
H: Heat sink
W: Window
A:

Seated height
L:

Assembled in piggyback

Low profile

T:

Thin

V:

Very thin

Terminal pitch and position

S:

Shrink

F:

Fine pitch
Example: Terminal pitch is 0.5 mm or less for QFP.
Terminal pitch is 0.8 mm or less for BGA and LGA.

I:
4

Interstitial

Lead protection
B:

Bumper

G: Guard ring
R: Retain

(3) Package name code

3 letters shall be specified.
Example DIP, SIP, ZIP, PGA, SOP, SOJ, QFP, QFJ, QFN, BGA or LGA

(4) Package terminal number code

Maximum of 5 letters shall be specified.

(5) Package nominal dimension code

Maximum of 11 letters shall be specified.
Example 39.65 x 39.65

(6) Terminal in-line interval code

4 letters shall be specified.
Example 0.65, 0.50 or 0.40

4.
4.1

Dimension Symbol and Example of Dimensions

Example of dimensions of packages

(1) DIP (Dual In-line Package)

n
+1
2

n
2

1
D

e1
b2

A2

A1

b1
e
b

Term

Symbol

Mounting height
Stand-off height
Main unit height
Maximum terminal length
Terminal width

A
A1
A2
L
b
b1, b2

Terminal width (Max.)

Terminal thickness
Direct terminal pitch
Package overhang
Package length
Direct terminal pitch
Package width
Tolerance of terminal
center
Terminal angle

c
e
Z
D
e1
E
x

Z
c
x

Meaning
Distance from mounting surface to top edge of package
Distance from mounting surface to base surface (bottom edge of package)
Height of package itself
Length of terminal from munting surface to tip of terminal
Width of terminal inserted into mounting hole on PC board
Maximum width of terminal
Thickness of terminal
Direct gap of true geometrical position of center of terminal
Distance from true position of terminal at outermost position to edge of package
Longest dimension of package
Gap of true geometrical position of center of terminal
Width of package
Difference in center of each pin from original position. Maximum measure
condition (MMC) is applied
Angle between terminal and line at right angles to mounting surface

(2) ZIP (Zigzag In-line Package)

A2

n
A1

Base surface
Terminal neck
x

2e

Z
e1

Term

Symbol

Mounting height
Stand-off height
Main unit height
Maximum terminal length
Terminal width

A
A1
A2
L
b
c
e ,
2e
Z
D
e1

Distance from mounting surface to top edge of package

Distance from mounting surface to base surface (bottom edge of package)
Height of package itself
Length of terminal from mounting surface to tip of terminal
Width of terminal inserted into mounting hole on PC board
Thickness of terminal
Direct gap of true geometrical position of center of terminal

E
x

Width of package
Difference in center of each pin from original position. Maximum measure
condition (MMC) is applied

Terminal thickness
Straight terminal pitch
Package overhang
Package length
Distance between terminal
rows
Package width
Tolerance of terminal
center

Meaning

Distance from true position of terminal at outermost position to edge of package

Longest dimension of package
Gap of true geometrical position of center of terminal

(3) PGA (Pin Grid Array)

D
D1
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

Note 1

E1
E

Heat sink

U T R P NM L K J HG F E D C B A

A2
A1

L ANote 2

Orientation pin

B
b

e
X

Note 1. Heat sink dimensions mentions E1 D1. (Case of heat sink package)
2. Seated height includes heat sink height. (Case of heat sink package)

Term
Mounting height
Stand-off height
Package body height
Stopper diameter
Terminal width
Straight line pin spacing
Package width
Package length
Terminal length
Package overhang
Heat sink width
Heat sink length
Tolerance of terminal
center

Symbol
A
A1
A2
B
b
e
E
D
L
Z
E1
D1
x

Meaning
Distance from mounting surface to top edge of package
Distance from mounting surface to base surface (bottom edge of package)
Height of package itself
Diameter of stopper
Diameter of terminal inserted into mounting hole on PC board
Direct gap of true geometrical position of center of terminal
Width of package
Maximum dimensions of package
Length from mounting surface to tip of terminal
Distance from true position of terminal at outermost position to edge of package
Width of heat sink
Length of heat sink
Difference in center of each pin from original position. Maximum measure
condition (MMC) is applied

(4) SOP (Small Outline Package)

n1

HE
D
L1

A2

L1

b
e

A1
L

y
x

Term

Symbol

Nominal size
Seating plane
Base plane

e1
S

Mounting height

A
A1
A2
b
c
D
E
e
Z
HE
L

Stand-off height
Package height
Terminal width
Terminal thickness
Package length
Package width
Terminal spacing linear
Package overhang
Overall width
Length of flat part of
terminal
Terminal length
Tolerance of terminal
center
Uniformity of bottom face
of terminal
Angle of terminal flat part

L1
x
y

Meaning
Size of package. Center-to-center distance of mount pads of SOP
Plane determined when IC is placed on horizontal surface
Plane that runs along bottom surface of package in parallel with mounting
surface
Distance from mounting surface to top of package
Distance from mounting surface to base surface
Height of package from base plane to top of package
Width of each terminal (including plating)
Thikcness of terminal (including plating)
Length of package (including resin burr)
Width of package (excluding resin burr)
Direct gap of true geometrical position of center of terminal. Also called lead pitch
Distance from true position of terminal at outermost position to edge of package
Width including terminal length
Length of part projected on terminal mounting surface contacting mounting pad
Length of terminal projected on mounting surface of package from tip of terminal
Difference in center of each pin from original position. Maximum measure
condition (MMC) is applied
Maximum value of difference of each terminal from plane at right angles to
mounting surface
The angle between the terminal flat part and mounting surface

(5) QFP (Quad Flat Package)

HD
D

E
HE

Detail of lead end

ZE

A1

ZD

L1
c

A2

y S

Term
Nominal size
Seating plane
Mounting height
Stand-off height
Package height
Terminal width
Terminal thickness
Package length
Package width
Terminal spacing linear
Package overhang
Overall length
Overall width
Length of flat part of
terminal
Terminal length
Tolerance of terminal
center
Uniformity of bottom face
of terminal
Angle of terminal flat part

Symbol
ED
S
A
A1
A2
b
c
D
E
e
Z D , ZE
HD
HE
L
L1
x
y

Meaning
Size of package
Plane determined when IC is placed on horizontal surface
Distance from mounting surface to top of package
Distance from mounting surface to base surface (bottom surface of package)
Height of package from base plane to top of package
Width of each terminal (including plating)
Thickness of terminal (including plating)
Length of package (excluding resin burr)
Width of package (excluding resin burr)
Direct gap of true geometrical position of center of terminal. Also called lead pitch
Distance from true position of terminal at outermost position to edge of package
Dimensions including terminal length of peripheral terminal existing in longitudinal
direction of package
Width including terminal length of peripheral terminal existing in latitudinal
direction of package
Length of part projected on terminal mounting surface contacting mounting pad
Length of terminal projected on mounting surface of package from tip of terminal
Difference in center of each pin from original position
Maximum measure condition (MMC) is applied
Maximum value of difference of terminal from mounting surface in direction at
right angles to mounting surface
The angle between the terminal flat part and mounting surface

(6) QFJ (Quad Flag J-leaded package)

A2

ZE

A1

ZD

b1

HE

HD
D

y S

e1 E

e1 D

Term
Nominal size
Seating plane
Seating height
Stand-off height
Package height
Terminal height
Maximum terminal width
Terminal width
Terminal thickness
Package length
Package width
Terminal spacing linear
Package overhang
Terminal spacing linear
Overall length
Overall width
Tolerance of terminal
center
Uniformity of bottom face
of terminal

Symbol

Meaning

ED

Size of package
Plant determined when IC is placed on horizontal surface
Distance from mounting surface to top of package
Distance from mounting surface to base surface (bottom surface of package)
Height of package from base plant to top of package
Distance of terminal projecting from package from top surface to mounting
surface
Maximum width of each terminal
Width of each terminal (including plating)
Thickness of terminal (including plating)
Length of package (excluding resin burr)
Width of package (excluding resin burr)
Direct gap of true geometrical position of center of terminal. Also called lead pitch
Distance from true position of terminal at outermost position to edge of package
Direct gap of center of bending of terminal
Dimensions including terminal length of peripheral terminal existing in longitudinal
direction of package
Width including terminal length of peripheral terminal existing in latitudinal
direction of package
Difference in center of each pin from original position. Maximum measure
condition (MMC) is applied
Maximum value of difference of terminal from mounting surface in direction at
right angles to mounting surface

S
A
A1
A2
L
b1
b
c
D
E
e
ZD, ZE
e 1 E, e 1 D
HD
HE
x
y

(7) BGA
D

S B

ZD

17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ZE

A
E

U T R P NM L K J HG F E DC B A
INDEX MARK

S A

A
y1

A2

b
Term
Nominal dimension

A1

x M S A B
Symbol
ED

Package length
Package width
Package center offset

D
E
w

Seating plane
Datum plane A

S
A

Datum plane B

Mounting height
1st. Standoff height

A
A1

Package height
2nd. Standoff height

A2
A4

Terminal spacing linear

Terminal diameter
Tolerance of terminal
center
Uniformity of bottom face
of terminal
Package top flatness

b
x

Overhang in body
direction D
Overhang in body
direction E

ZD

y
y1

ZE

Meaning
Combination of integral value of package width E and package length D is
regarded as nominal dimension
Length of package
Width of package
Difference in center of package from original position
Plane determined when IC is placed on horizontal surface
Shall be specified by a plane passing a center of a form of a package or a plane
of a form.
Shall be specified by a plane passing a center of a form of a package or a plane
of a form.
Distance from mounting surface to top package
1st. stand-off height is defined as the distance from the seating plane to the
lowest point of the package except the cavity.
Height of package from base plane to top package
2nd. stand-off height is defined as the distance from the seating plane to the
lowest point of the cavity.
Direct gap of true geometrical position of center of terminal. Also called lead
pitch.
Diameter of terminal.
Difference in center of each ball from original position. Maximum measure
condition (MMC) is applied.
Maximum value of difference of terminal from mounting surface in direction at
right angles to mounting surface
Package top flatness is defined as the difference between the distance from
seating plane to the highest points of the package top and the distance to the
lowest points.
Distance from position of terminal at outermost position to edge of package for
direction D.
Distance from position of terminal at outermost position to edge of package for
direction E.

4.2
4.2.1

Dimensional symbols
Reference dimensions by true geometric location e , e1

Theoretical dimension is enclosed in a square.

Examples: 1.27 , 2.54
4.2.2

Dimensional indication by geometric tolerance

x

M
Tolerance indication accoding to MMC
Tolerance
Type of geometric tolerance (positional tolerance for the example)

Maximum material condition (MMC)

Applied to allowable positional tolerance of the terminals. (refer to ISO/1101, Parts 2)
Positional tolerance of terminals (See note)
x = 0.25 mm
Note Tolerance is a deviation from the true position (the center or each terminal) but not a cumulative error.
Example

0.25

If the terminal width (b) is the maximum, the allowable deviation from the center of
the terminal (true position) is up to 0.25 mm. If the terminal width (b) is less than
the maximum, the tolerance can be increased proportionally.

4.2.3

X (Tolerance of terminal center)

(1) Through hole packages (Standard DIP)

0.25

If the terminal width (b) is the maximum, the allowable deviation from the center of the terminal (true position)
is up to 0.25 mm. If the terminal width (b) is less than the maximum, the tolerance can be increased proportionally.
Terminal center (CL1 ,CL2 ) in the figure below are not in the true position (CL ).
The maximum terminal width (b) and tolerance (x) of a standard DIP are, respectively, 0.60 mm (= b) and 0.25
mm (= x). Therefore, the allowable terminal existing range is calculated as follows:
2
=2

x
2
0.25
2

+
+

bMAX.
2
0.60
2

= 0.85 mm
CL2

CL

CL1

0.50

0.60
2

0.25
2

0.25
2

0.10

0.60
2

0.85
Printed-circuit board

2.54
Hole diameter

0.25

(2) Surface mount packages (SOP)

0.12

If the terminal width (b) is the maximum, the allowable deviation from the center of the terminal (true position)
is up to 0.12 mm. If the terminal width (b) is less than the maximum, the tolerance can be increased proportionally.
The figure below shows that the pin center is shifted from the true center ( CL ).
The SOP has a maximum pin width, bMAX, of 0.50 mm and a positional tolerance, X, of 0.12 mm, so the allowable
pin existing range is 0.62 mm as obtained by the following expression:

2
=2

2
0.12
2

bMAX.
2
0.50
2

= 0.62 mm
The recommended mounting pad width is 0.76 mm to allow a position shift of 0.07 mm unless the self-aligning
effect cannot be expected.

CL2

0.50
2

0.07

CL

0.12
2

CL1

0.12
2

0.62

0.50
2

0.07

0.76

Mounting pad

Printed-circuit board
1.27

5.

PACKING OF PACKAGES

5.1

Packing Styles and Notes

5.1.1

Packing styles

The following figures show the general packing styles of NECs products.
Example of Packing of IC Packages
TRAY

TAPE

CONTAINER

MAGAZINE

Scotch tape
(NEC original)
INNER BOX

Scotch tape (NEC original)

Label

Scotch tape (NEC original)

Label

Label

5.1.2 Notes on handling

(a) Inner boxes should be handled with care. A strong vibration or shock during transportation can cause IC pins
to be distorted and/or the main unit to be damaged. Storage in an environment of high temperature and high
humidity should be avoided.
(b) Our transparent plastic magazine case is coated with an antistatic agent. Things to remember:
1

If the magazine is washed with water, the antistatic coating could come off.

Rubbing the surface repeatedly reduces the antistatic effect. Minimize the frequency of inserting and
removing the IC into and from the magazine.

Under normal storage conditions, the surface resistivity shows not change with aging as shown in satisfying our
specification of 1.0 1012 (/ ) MAX.

Value of surface resistivity (/

Change with Aging of Surface Resistivity of Magazine Case

1 1012
Max. specification
1 10

Storage time (year)

(c) Storage
An extremely unsatisfactory storage environment could affect soldering characteristics, damage appearance
and/or lower other characteristics.
The following are recommended environmental conditions for storage:
1

Temperature

: 5 to 30 C

Humidity

: 70 % RH or less

Ambience

: There should be no toxic gases such as sulfurous acid gas. Dust should be minimal.

Others

: There should be no vibration or shock which could distort the packing container.
To avoid excess weight do not stack many packing containers on top of each other.

(d) Delamination tension of emboss taping

The delamination tension of our emboss taping is 20 to 70 gf irrespective of storage environment. To set our
emboss taping in a mounting machine, it is necessary to consider the delamination tension.
Emboss Tape Delamination Tension Test

Tension gage
Angle of tension
175 to 180

Cover tape

Carrier tape
Tensional speed 300 mm/MIN.

Tensional strength (gf)

70

<Test method>

60

60 C, 90 %

50

60 C

40

25 C, 65 %

30
20
10
0

5 10 15

30

90

Storage time (day)

(e) Heat proof of packing material

i)

Tray
There are two types of trays: a non-heat proof tray and a heat proof tray. For baking, it is necessary to use
a heat proof tray. A heat proof tray is used for products contained in an aluminum-laminated pack. This
type of tray is labelled HEAT PROOF. The allowable temperature is 135 C MAX.

ii)

Magazine, Emboss tape & Reel

A plastic magazine, emboss tape and reel are not heat proof. To bake the products, it is necessary to transfer
them to a heat proof container.
Note When baking, it is necessary to be careful not to cause the lead pins to become distorted.

5.2

Dimensions of tapings

The reel standards and tape standards for the products packed on a tape are described, which conform to JIS
C 0806-3 Taping of electronic parts (Surface-Mount Parts) and Taping of leadless parts for automatic mounting (RS481) by EIA.
NEC uses the following ordering codes for the emboss taped ICs:
5.2.1

Taping for SOP/TSOP

(1) Indication of direction for adhesive-type taping (SOP only)

T1: When the side at which is pin 1 is at the drawout side
Pin 1 indication

Tape drawout direction

T2: When the side at which is pin 1 is at the takeup side

Pin 1 indication

Product example: PD4011BG-T1 (This is a taping product for the PD4011BG with pin 1 facing the tape
drawout direction)
(2) Indication of direction for embossed-type taping
E1: When the side at which is pin 1 is at the drawout side
Pin 1 indication

Tape drawout direction

E2: When the side at which is pin 1 is at the takeup side

Pin 1 indication

5.2.2

Taping for SOJ

Indication of direction for embossed-type taping

E1: When the side at which is pin 1 is at the drawout side
Pin 1 indication

Tape drawout direction

E2: When the side at which is pin 1 is at the takeup side

Pin 1 indication

Product example: PD421000LA-10-E1 (a model of PD421000LA with access time of 100 ns and pin 1 at the
drawout side)

5.2.3 Taping for QFJ

Indication of direction for embossed-type taping
E1: When the side at which is pin 1 is at the drawout side
Pin 1 indication

Tape drawout direction

E2: When the side at which is pin 1 is at the takeup side

Pin 1 indication

E3: When the side at which is pin 1 is at the right when

Tape drawout direction

viewed from the drawout side

Pin 1 indication

E4: When the side at which is pin 1 is at the left when

Tape drawout direction

viewed from the drawout side

Pin 1 indication

Product example: PD41265L-12-E1 (a model of PD41256L with access time of 120 ns and with pin 1 at the
drawout side)

5.2.4 Taping for QFP

Indication of direction for embossed-type taping
Pin 1 indication

E1: When the side at which is pin 1 is at the drawout side

and at the opposite side of sprocket hole
Tape drawout direction

E2: When the side at which is pin 1 is at the takeup side

Pin 1 indication

and at the sprocket hole side

Tape drawout direction

Product example: PD23C32000AGX-$$$-E2 (a model of PD23C32000A with pin 1 at the takeup side and at
the sprocket hole side)