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Vin+
Vin
Input Differential
Amplifier stage
Bias circuit
Page 30
Vo
Vin+
Vin
1st stage
2nd stage
Output Buffer
Vo
31
M4
M3
M6
Iref
Vo
CC
Vin+
M1
M2
VinCL
M7
M5
M8
32
(5.3.1)
(5.3.2)
In this circuit, current mirror active load used has three main advantages. First, active
load devices crate large output resistance that provides small amount of chip area. Second
current mirror topology provides the differential to single ended conversion of input
signal. The voltage gain of the differential amplifier is given by AV1
AV1 = g m1 (ro4 ro2 )
(5.3.3)
The differential to single ended conversion is achieved by using current mirror M3 and
M4. The current from M1 is mirror by M3 and M4 and subtracted from the current from
M2. Finally the differential current from M1 and M2 multiplied by the output resistance
of the input stage that gives the single ended output voltage. This is the part of the second
stage.
Second Stage: Second stage is a common source stage. The aim of this second stage is to
provide the additional gain consisting of transistors M6 and M8. Input of the second stage
is the output of the differential amplifier stage. This stage receives the output from the
drain of M4 and amplifies it through M6 by the common source configuration. Similar to
differential amplifier, this stage employs an active device, M8 to work as the load
resistance for M6. The gain of this stage is the transconductance of M6 times the
effective load resistance comprised of the output resistance of M6 and M8.
Transconductance and output resistance of the second stage is given by G m2 and Rout
Gm2 = g m6
(5.3.4)
33
(5.3.5)
M6 is driver and M8 is acts as the load. The voltage gain of the second stage is given by
AV2
AV2 = g m6 (ro5 ro8 )
(5.3.6)
So that total gain of the two stage CMOS operational amplifier is given by
AV = AV1 AV2
(5.3.7)
(5.3.8)
(5.3.9)
Biasing Circuit: The purpose of the biasing circuit is to provide the gate to source
voltage of the entire transistor. The biasing of the operational amplifier is achieved with
only three transistors. Transistor M5 supplies a voltage between gate and source of M7
and M8. Transistors M7 and M8 sink a certain amount of current based on their gate to
source voltage which is controlled by the bias string. M5 is diode connected to ensure
they operate in the saturation region. Proper biasing of the other transistor in the circuit
(M1-M4, M6) is controlled by the node voltages present in the circuit itself. M6 is biased
by the gate to source voltage set up by the VGS of the current mirror load as are the M3
and M4 transistors.
Third stage: In fig 5.2, third stage is output buffer stage which is simply common drain
stage. This stage is often called a source follower, because the source voltage follows the
gate voltage, except for a level shift. When possible, it is desirable to tie the substrate of
the source-follower device to its source in order to eliminate gain degradations due to the
body effect. This connection also results in a smaller dc voltage drop from the gate to the
source of the source-follower device, which is a major limitation on the maximum
positive output voltage. So that in fig 5.3, we dont show output buffer stage due above
drawback.
34
Vo 2
V1 1
Vo
Vin
CC
gm1V1
CL
ro1
roL
gm2V1
-
Figure 5.4: Small signal analysis of two-stage CMOS op-amp without miller
compensation
V
in
Vo
V in
= V 1 Vo
in
(5.4.1)
SC L
v1 sc1 +
v1
+ g m1 vin + scc (v1 vo ) = 0
R1
v1 (sc1 +
v1 =
1
+ sc1 ) + g m1 vin vo scc = 0
R1
v o sc 1 R 1 g m 1 v in R 1
(5.4.2)
1+sR 1 (c c +c 1 )
sc 2
sc2 vo +
sc c
vo
+ g m2 v1 + scc (vo v1 ) = 0
R2
vo sc2 +
vo
vo 1 + sR 2 cc + c2
vo
vo v1
+ g m2 v1 +
=0
1
R2
1
+ scc v1 scc + g m2 v1 = 0
R2
1
+ (sc2 + scc ) = v1 scc g m2
R2
1 + sR1 cc + c1
35
g m1 g m2 R1 R 2 1 g c
vo
m2
= 2
vin s R1 R 2 c1 c2 + c1 cc + c2 cc + s R 2 cc + c2 + R1 cc + c1 + cc g m2 R1 R 2 + 1
(5.4.3)
Equation 5.4.3 is standard transfer function of fig. 5.3.
Two pole transfer function:
vo
v in
vo
v in
A DC 1Z
=
=
s
1+P
(5.4.4)
1+P
s
Z
1
1
1
+ +s 2 (P P )
P1 P 2
1 3
A DC (1 )
1+s
1
P1
1
P2
=s
P2
(5.4.5)
(5.4.6)
P1
=Co-efficient of s
If pole P1 and P2 is shown in graph. In this graphs pole P2 is far away from the pole P1 at
high frequency so that pole P1 is located at low frequency so that pole P2 is ignored in
equation (5.4.6).
Compare equation (5.4.3) and (5.4.5), poles P1, P2 , zeros Z and DC gain ADC is given by
Pole P1,
P1 = R
1
2
P1 g
Pole P2,
1
1
1 R 2 c 1 c 2 +c 1 c c +c 2 c c
P2 = P
1
1 R 1 R 2 c 1 c 2 +c 1 c c +c 2 c c
P2 = R
Zeros Z,
(5.4.7)
m 2R1R2cc
P1 P2 = R
P2 =
c c +c 2 +R 1 c c +c 1 +g m 2 R 1 R 2
gm 2R1R2cc
1R2
c 1 c 2 +c 1 c c +c 2 c c
gm 2cc
c 1 c 2 +c 1 c c +c 2 c c
P2
g m 2c c
P2
gm 2
cc c2
(5.4.8)
c2
(5.4.9)
36
DC voltage gain,
(5.4.10)
1
g m2 R1 R 2 CC
gm 1
(5.5.1)
CC
Zeros is far away from the 10 times located after unity gain. So therefore, we are express
zeros in bode plot diagram,
Z 10GBW
Slew-rate, SR: It is defined by the maximum rate of change of output voltage per unit
time, generally express in V/s
SR =
dv
dt
Maximum
V=C
I dt
VC =
I dt
37
Io = cc
dv
Io
dt
cc
dv
dt
I0
(5.5.2)
cc
V0
V in
= tan1
W
Z
tan1 P tan1 P
(5.5.3)
V0
GBW
GBW
GBW
= tan1
tan1
tan1
Vin
Z
P1
P2
Putting the value of the GBW, Z, P1 and P2 from the equation (5.5.1) (5.4.7), (5.4.8) and
(5.4.9)
V0
GBW
g m1 g m2 R1 R 2 CC
GBW
= tan1
tan1
tan1
Vin
10 GBW
CC
P2
V0
1
GBW
= tan1
tan1 g m1 g m2 R1 R 2 tan1
Vin
10
P2
From the equation (5.4.10), g m1 g m2 R1 R 2 is voltage gain ADC
V0
1
GBW
= tan1
tan1 ADC tan1
Vin
10
P2
1
Putting tan1 10 = 5.71 and voltage gain is always 90 phase angle in bode plot
180 + PM = 5.71 90 tan1
PM = 180 5.71 90 tan1
PM = 84.29 tan1
GBW
GBW
P2
GBW
P2
(5.5.4)
P2
Op-amp has better phase margin and improve stability at 60 phase angle. So that we will
take phase margin is 60 as according to find relation between GBW and second pole P2
in bode plot.
60 = 84.29 tan1
tan1
GBW
P2
GBW
= 24.29
P2
38
(5.5.5)
GBW
P2
GBW
P2
GBW
= 39.29
P2
GBW
= 0.8181
P2
P2 =
GBW
0.8181
(5.5.6)
From the equation (5.4.8) and (5.5.1), put the value of P 2 and GBW in equation (5.5.5)
g m2
g m1
2.2
C2
CC
C2 is output capacitance; we replace C2 by load capacitance
gm 2
CL
2.2
gm 1
CC
39
(5.5.7)
(5.5.8)
CL
CC
CC
2.2
10
CL
CC 0.22 CL
(5.5.9)
40