Cadence Design IP: DDR (Hard) Phase PHY

For TSMC 65LP, 40G, 28HP, and 28HPM processes

Cadence DDR DRAM solutions are the only fully integrated IP offerings on the market with the
features and configurability required to optimize your design and meet your performance, power,
and cost targets. With more than 400 design wins ranging from the lowest-power handheld
consumer applications to the highest-performance enterprise supercomputers, Cadence Design IP
for DDR DRAM is your lowest risk path to success.

Cadence Hard Phase PHYs for TSMC

The memory subsystem is a core component of any SoC,
and the DDR DRAM interface will have a fundamental
impact on the performance and cost of your system.
Successful designs must support both the latest and
legacy devices while delivering the highest performance
and the lowest power in all cases.
Cadence DDR Phase PHYs for TSMC are Hard PHYs
delivered as 8-bit hardened macros or with I/Os
connectedfor TSMCs 65nm Low-Power (LP), 40nm
General-Power (G), 28nm High-Performance (HP), and
28nm High-Performance Mobile (HPM) processes. They
are designed for the highest-performance DDR3 and
DDR4 devices, including low-voltage variants such as
DDR3L and DDR3UL, at speeds up to DDR-2400 in TSMC
28HP and TSMC 28HPM.
The architecture of the Cadence DDR Phase PHY is
an oversampling design that uses DSP-like techniques
to reconstruct the data on the memorys data lines,
providing a robust output at the highest speeds of DDR
DRAM, even in the presence of noise.
With a slice-based architecture, our Hard PHY macros offer
you flexibility in placement, floorplanning, packaging,
and I/O while retaining the reliability and ease of use of
Hard PHY designs. When delivered connected to I/Os, our
Hard PHYs offer all the time-to-market advantages and
proven design quality of traditional Hard PHY designs while
retaining some flexibility.
The Cadence DDR Phase PHY is a hybrid analog/digital
solution comprising a clock phase generation PLL and
digital logic to perform all data capture and analysis

based on the multiple phases of the clock. Our DDR Phase

PHY connects the DDR I/O pads to the DDR PHY Interface
(DFI) to the memory controller including alignment of
write data, read data capture, and DQS gating.
Our highest-performance DDR PHY solution, the Hard
Phase PHY targets the highest speeds of DDR3 and DDR4
in applications such as enterprise, networking, computing,
and digital TV. Cadence also offers Soft PHY designs for
the ultimate in flexibility over process, floorplanning,
library, placement, and routing.
For consumer, low-power, wireless, handheld, and
battery-operated devices, a companion DDR DLL PHY is
available (Soft or Hard). This small, power-efficient PHY
design supports the latest mobile DRAM and non-mobile
DDR standards.

Key Features
Up to 1200MHz (DDR-2400) operation in DDR4/3
mode in TSMC 28HP and TSMC 28HPM
Supports the highest speed of DDR3, up to 1066MHz
(DDR-2133) operation in TSMC 40G
Supports the highest speed of DDR2, up to 533MHz
(DDR-1066) operation in TSMC 65LP
Complete PHY available with I/Os connected
8-bit datapath macros can be repeated to build PHYs of
any width
Supports DRAM chips with 8 or 16 data bits per chip,
commonly used in soldered-down and unbuffered
DIMM (UDIMM/SoDIMM) applications

Phase_PHY
To Memory Controller (DFI)

Individual timing to each data slice supports

DDR3 and DDR4 DIMM fly-by timing and
unique board topologies
Read and write data interfaces employ
phase-based delays for correct data and DQS
alignment

phy_param

data_slice_0

data_slice_1

PLL creates PVT-compensated read and write

clocks to the appropriate data paths
Phase PHY design allows per-bit deskewing
without any extra elements in the data path
Register interface for PHY programming,
configuration, and testing modes

phy_ctrl

io_addr_cntrl
io_control

Supports DRAM chips with 4 data bits per chip,

commonly used in RDIMM applications

data_slice_2

data_slice_3

data_slice_ca

To Pads

Figure 1: Top-level block diagram of a 32-bit system

Clock gating for the lowest power operation

Support for RDIMM including SSTE32882 and UDIMM/SoDIMM

Read and write leveling using DFI PHY evaluation mode or

controller evaluation mode

Industry-standard DFI connects to Cadence DDR Controllers or

third-party controllers

Scan functionality for data slice

Internal and external datapath loopback mode for additional
functional testing
Boundary scan muxing built into core logic facilitates insertion
of boundary scan chains between core logic and I/ O pads
I/O pads with termination calibration logic and data retention

Silicon-proven and scalable

Cadence has 10+ years of Design IP experience with 400+ design
successes, from 180nm down to 22nm. As an active member
of the JEDEC standards organization, Cadence has early access
to standards under development, can provide IP for emerging
standards early in their lifecycles, and can identify and adapt to
changes in already-published standards.

Superior ease of implementation

Technology Support
Hard GDSII implementation for TSMC 65LP, TSMC 40G, TSMC
28HP, or TSMC 28HPM (different Hard PHYs available)

Deliverables
RTL Verilog files for all PHY modules including data slice
Verilog sample testbench with Cadence memory models,
encrypted memory controller, and sample tests
Compatible with Cadence DFI Monitor Verification IP to aid
integration with custom memory controllers
Register configuration files and utilities for programming the
sample simulation testbench, controller, and PHY registers
PHY user guide and implementation guide

Support for PC/server DRAM: DDR4 and DDR3

Hardened slice
Liberty timing model
Abstract in LEF format
Post-layout Verilog netlist
GDS layout or P&R db (DEF or Cadence Encounter format)
SDF for back-annotated timing verification
Static timing analysis (STA) and signal integrity (SI) reports
LEC report
Physical verification reports (DRC, LVS, ANT)

Support for low-voltage DRAM: DDR3L

Synthesis scripts for PHY core level and I/O pad integration

Support for multi-standard PHYs; mixing the standards listed

above allows your product to penetrate different markets,
extends product life, and reduces supply chain risk

STA scripts for the PHY level

Designed to be used at chip-level STA or standalone at the
PHY level
Designed to create SDC input to layout, and to validate
timing of the final design)

The DDR Phase PHY is our latest-generation architecture created

for ease of implementation and to be highly compatible with EDA
tools from multiple vendors. Its slice-based architecture gives
you more flexibility than traditional Hard PHY designs, while still
retaining the robustness and ease of use of a Hard PHY.

Supported Interfaces

Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
2012 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design
Systems, Inc. All others are the properties of their respective holders.
22723 05/12 MK/DM/PDF