Lab1: Design a MIPS 32 by 32 Register File

Group 11

1. Member and contribution:

Tran Ngoc Hai
Nguyen Tien Hieu
Dang Hoai Nam

Module register32x32 and regfile

Module multiplexer
Module decoder

2. Lab Objectives:
For this lab1 you are to construct a 32 by 32 register file using Verilog HDL. The register file is
introduced in chapter 4 of the class textbook. Within the 32 by 32 register file is an array of 32 different
32-bit registers. These registers must be constructed from D flip-flops (positive edge-triggered). Note
that for MIPS, register zero ($zero) is hardwired to always output the value zero, regardless of what may
or may not be written to it. The figure below shows a block diagram of a register file (this is a modified
reproduction of figure 4.7 on page 310 of the textbook: Computer Organization and Design 4th edition by
Patterson and Hennessy).
5
32
5
5

32

Read Register 1 and Read Register 2 select the registers whose values are output on
the Read Data 1 bus and Read Data 2 bus respectively. The Write Register input bus selects the
target of the write; when RegWrite is true, the information on the Write Data bus register is
written into that register.
Computer resources and software tools:
PCs with Software Quartus II, ModelSim, IVerilog installed, testbench file: regstim.v
Implementation:
A simple implementation of the 32 by 32 MIPS register file can be made using

Registers composed of D flip-flops, a 5:32 enabled decoder, and two large to 32 multiplexors

32

Register 1

32

Register 2

32
32

RegWri
te

Register 31

Write Register 5

Read
Data 1

32

5
1

Read Register

3
2
32
Write Data

32
32
32

Read
Data 2

32

5
2
Each 32-bit register is simply an array of 32 D flip-flops:

Read Register

Data In

Register

Register

Enable

32

Data Out

3. Design:
a. Decoder:
We use decoder 3to8 and 2to4 to make decoder 5to32

b. Multiplexer:
First, we make the multiplexer 2to1.

Then make the multiplexer 4to1

Then make the multiplexer 16to1

Then make the multiplexer 4to1

c. Regfile:
First we make a 1 bit register by using D flipflop

Enable
D

clock

Register Cell

clear

+ Logical 0 cell holds its state because of AND gate

+ Logical 1 cell D input enabled data goes to cell
Value on D stored on clock, and wait for enable control-logical 1

Then connect 32 1 bit registers in series to make a 32bit register.

Finally, we have 32x32bit register.

4. Code :
a. Decoder :
Decoder 2 to 4 :
module decoder2to4(in1, in2, y0, y1, y2, y3, RegWrite);
input RegWrite;
input in1, in2;
output y0, y1, y2, y3;

not not241(in1n, in1);

not not242(in2n, in2);

and and3(y3, RegWrite, in1, in2);

and and2(y2, RegWrite, in1n, in2);
and and1(y1, RegWrite, in1, in2n);
and and0(y0, RegWrite, in1n, in2n);
endmodule

Decoder 3 to 8 :

module decoder3to8(w0, w1, w2, En, y1, y2, y3, y4, y5, y6, y7, y8);
input w0, w1, w2, En;
output y1, y2, y3, y4, y5, y6, y7, y8;
not not100(w2n, w2);
and and381(En1, w2n, En);
and and382(En2, w2, En);

decoder2to4 mydecoder2to4a(w0, w1, y1, y2, y3, y4, En1);

decoder2to4 mydecoder2to4b(w0, w1, y5, y6, y7, y8, En2);
endmodul

Decoder 5 to 32 :

module decoder(enable, WriteRegister, RegWrite);

input RegWrite;
input [4:0] WriteRegister;
output wire [31:0] enable;
wire e1, e2, e3, e4;

decoder2to4 mydecoder2to4(WriteRegister[3], WriteRegister[4], e1, e2, e3, e4, RegWrite);

decoder3to8 mydecoder3to8a(WriteRegister[0], WriteRegister[1], WriteRegister[2], e1, enable[0],

enable[1],enable[2],enable[3],enable[4],enable[5],enable[6],enable[7]);
decoder3to8 mydecoder3to8b(WriteRegister[0], WriteRegister[1], WriteRegister[2], e2, enable[8],
enable[9],enable[10],enable[11],enable[12],enable[13],enable[14],enable[15]);
decoder3to8 mydecoder3to8c(WriteRegister[0], WriteRegister[1], WriteRegister[2], e3,
enable[16],enable[17],enable[18],enable[19],enable[20],enable[21],enable[22],enable[23]);
decoder3to8 mydecoder3to8d(WriteRegister[0], WriteRegister[1], WriteRegister[2], e4,
enable[24],enable[25],enable[26],enable[27],enable[28],enable[29],enable[30],enable[31]);

endmodule

b. Multiplexer :
Multiplexer 2 to 1
module mux2to1(data, w, y0, y1);
output data;
input w, y0, y1;
not n1(nw,w);
and a1(a,nw,y0);
and a2(b,w,y1);
or o1(data,a,b);
endmodule

Multiplexer 4 to 1

module mux4to1(data, w1, w0, y0, y1, y2, y3);

output data;
input w1, w0, y0, y1, y2, y3;

mux2to1 m0(data0,w0,y0,y1);
mux2to1 m1(data1,w0,y2,y3);
mux2to1 m2(data,w1,data1,data2)

endmodule

Multiplexer 16 to 1

module mux16to1(data, w3, w2, w1, w0, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12,
y13, y14, y15);
output data;
input w3, w2, w1, w0, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14,
y15;

mux4to1 m0(data0, w1, w0, y0, y1, y2, y3);

mux4to1 m1(data1, w1, w0, y4, y5, y6, y7);
mux4to1 m2(data2, w1, w0, y8, y9, y10, y11);
mux4to1 m3(data3, w1, w0, y12, y13, y14, y15);
mux4to1 m4(data, w3, w2, data0, data1, data2, data3);

endmodule

Multiplexer 32 to 1

module mux32to1(data, w4, w3, w2, w1, w0, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11,
y12, y13, y14, y15, y16, y17, y18, y19, y20, y21, y22, y23, y24, y25, y26, y27, y28, y29, y30,
y31);
output data;
input w4, w3, w2, w1, w0, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13,
y14, y15,y16, y17, y18, y19, y20, y21, y22, y23, y24, y25, y26, y27, y28, y29, y30, y31;
mux16to1 m0(data0, w3, w2, w1, w0, y0, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12,
y13, y14, y15);

mux16to1 m1(data1, w3, w2, w1, w0, y16, y17, y18, y19, y20, y21, y22, y23, y24, y25, y26,
y27, y28, y29, y30, y31);
mux2to1 m3(data, w4, data0,data1);
endmodule

Multiplexer 32 to 32

module multiplexer(
input [4:0] ReadReg,
input [31:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11,
reg12, reg13, reg14, reg15, reg16, reg17,reg18, reg19, reg20, reg21, reg22, reg23, reg24,
reg25, reg26, reg27, reg28, reg29, reg30, reg31,
output [31:0] RegReadData
);
genvar i;
generate
for(i=0;i<32;i=i+1)
begin: muxblock
mux32to1 mux32to1(RegReadData[i], ReadReg[4], ReadReg[3], ReadReg[2],
ReadReg[1], ReadReg[0], reg0[i], reg1[i], reg2[i], reg3[i], reg4[i],reg5[i], reg6[i], reg7[i],
reg8[i], reg9[i], reg10[i], reg11[i], reg12[i], reg13[i], reg14[i], reg15[i],reg16[i], reg17[i],
reg18[i], reg19[i],reg20[i], reg21[i], reg22[i], reg23[i], reg24[i], reg25[i], reg26[i], reg27[i],
reg28[i], reg29[i], reg30[i], reg31[i]);
end
endgenerate
endmodule
c. Register
D flip flop
module DFlipFlop(q, qBar, D, clk, rst);
input D, clk, rst;
output q, qBar;

reg q;
not n1 (qBar, q);
always@ (negedge rst or posedge clk)
begin
if(rst)
q = 0;
else
q = D;
end
endmodule

1 bit register

module OnebitRegister(clk,rst,enable, data,out);

input clk, rst, enable, data;
output out;

wire not1, Q, notQ, and1, and2, or1;

not (not1,enable);
and (and1, data, enable);
and (and2, not1, Q);
or (or1, and1, and2);
DFlipFlop DFlipFlop(Q,or1,clk,rst);
assign out=Q;

endmodule

32 bit register

module register( clk, rst, enable, in, out);

input clk,rst,enable;
input [31:0]in;
output [31:0]out;

genvar i;
generate
for(i=0;i<32;i=i+1)
begin: block32bit
OnebitRegister onebit(clk,rst,enable,in[i],out[i]);
end
endgenerate

endmodule

32 x 32 bit register

module register32x32(
input clk, rst,
input [31:0] enable,
input [31:0] WriteData,
output [31:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg12,
reg13, reg14,reg15, reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23, reg24, reg25,
reg26, reg27, reg28, reg29, reg30, reg31);

register register0(clk, rst, enable[0], WriteData, reg0);

register register1(clk, rst, enable[1], WriteData, reg1);
register register2(clk, rst, enable[2], WriteData, reg2);
register register3(clk, rst, enable[3], WriteData, reg3);

register register4(clk, rst, enable[4], WriteData, reg4);

register register5(clk, rst, enable[5], WriteData, reg5);
register register6(clk, rst, enable[6], WriteData, reg6);
register register7(clk, rst, enable[7], WriteData, reg7);
register register8(clk, rst, enable[8], WriteData, reg8);
register register9(clk, rst, enable[9], WriteData, reg9);
register register10(clk, rst, enable[10], WriteData, reg10);
register register11(clk, rst, enable[11], WriteData, reg11);
register register12(clk, rst, enable[12], WriteData, reg12);
register register13(clk, rst, enable[13], WriteData, reg13);
register register14(clk, rst, enable[14], WriteData, reg14);
register register15(clk, rst, enable[15], WriteData, reg15);
register register16(clk, rst, enable[16], WriteData, reg16);
register register17(clk, rst, enable[17], WriteData, reg17);
register register18(clk, rst, enable[18], WriteData, reg18);
register register19(clk, rst, enable[19], WriteData, reg19);
register register20(clk, rst, enable[20], WriteData, reg20);
register register21(clk, rst, enable[21], WriteData, reg21);
register register22(clk, rst, enable[22], WriteData, reg22);
register register23(clk, rst, enable[23], WriteData, reg23);
register register24(clk, rst, enable[24], WriteData, reg24);
register register25(clk, rst, enable[25], WriteData, reg25);
register register26(clk, rst, enable[26], WriteData, reg26);
register register27(clk, rst, enable[27], WriteData, reg27);
register register28(clk, rst, enable[28], WriteData, reg28);
register register29(clk, rst, enable[29], WriteData, reg29);

register register30(clk, rst, enable[30], WriteData, reg30);

register register31(clk, rst, enable[31], WriteData, reg31);

endmodule
d. Regfile
Module regfile(readData1,readData2,WriteData,ReadReg1,
ReadReg2,WriteReg,RegWrite,clk);
input clk, RegWrite;
input [4:0] ReadReg1, ReadReg2, WriteReg;
input [31:0] WriteData;
output [31:0] readData1, readData2;

wire [31:0] reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg12,
reg13, reg14, reg15, reg16, reg17,reg18, reg19, reg20, reg21, reg22, reg23, reg24, reg25,
reg26, reg27, reg28, reg29, reg30, reg31;
wire [31:0] enable;
reg rst=0;

decoder decoder(enable, WriteReg, RegWrite);

register32x32 register(clk,rst,enable, WriteData, reg0, reg1, reg2, reg3, reg4, reg5, reg6,
reg7, reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg16, reg17,reg18, reg19,
reg20, reg21, reg22, reg23, reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31);

multiplexer multiplexer1(ReadReg1, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8,
reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg16, reg17,reg18, reg19, reg20, reg21,
reg22, reg23, reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31, readData1);

multiplexer multiplexer2(ReadReg2, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8,
reg9, reg10, reg11, reg12, reg13, reg14, reg15, reg16, reg17,reg18, reg19, reg20, reg21,
reg22, reg23, reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31, readData2);

endmodule

5. Simulation
a. Decoder:
In this case we make a test bench to check the work of module decoder
The decoder work with enable is active

The decoder with enable is deactie

We can see that the decoder is work exactly.

b. Multiplexer:
In this case, we check the work of the module multiplexer. The waveform
simulation is very long so we capture some parts of simulation.
When multiplexer choose reg6 and reg7

When multiplexer choose reg8 and reg9

We can see that the decoder is work exactly.

c. Register32x32:
In this case, we simulate the case that we write data from 0-31 to 32 register with
clock and reset is not active.

We conclude that the module work perpectly

d. Simulation of regfile :
In this part, we simulate the main module regfile by the file regstim.v in this lab.
The wave form also is very long so we can capture some parts of simulation.

From the simulation, we see that the module work perfectly.