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EE - 304 ENT
(j) Topology:
i. Deals with properties of networks which are unaffected when the network is
stretched, twisted, or otherwise distorted the size and the shape,
ii. Not concerned with the particular types of elements appearing in the circuit, but
only with the way in which branches and nodes are arranged.
(k) Graph:
i. A graph corresponding to a given network is obtained by replacing all circuit elements with lines.
) Connected graph: A graph in which at least one path exists between
any two nodes of the graph. If the network has a transformer as one of the
element, then the resulted graph is unconnected
) Directed or Oriented graph: A graph that has all the nodes and branches
numbered and also directions are given to the branches.
) Subgraph: The subset of a graph. If the number of nodes and branches of a
subgraph is less than that of the graph, the subgraph is said to be proper.
Note: Circuits [closed paths] of a graph have the following properties
- The maximum number of branches possible, in any circuit/loop, will be equal to
the number of nodes or vertices.
- There are exactly two paths between any pair of vertices in a circuit.
- There are at least two branches in a circuit.
If the two terminal nodes of a path are made to coincide, the result will be a circuit or
loop.
(l) Example - 01
IL
IR1
R1
Is
R2
2 IR2
I R3
IC
Vs
R3
(a) A circuit.
2
2
3
1
4
4
4
1
Handout: # 01
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(m) Example - 02
L
IL
R1
I1
Is
I3
IC
R2
2 I2
R3
Vs
g
4
4, 5
(a)
(b)
(c)
Fig. 1.3: (a) A circuit, (b) its directed graph and (c) simplified directed graph of (b).
(n) Example - 03
IL
I1
R1
2 I2
R2
IC
R
Ivs
Is
Vs
e
4
(a)
(b)
(c)
Note:
- The active elements are excluded[replaced by their internal resistances] from the graph
to simplify analysis and computation.
(o) Example - 04
1 IR1
R1
2 I R2
IR3
5A
IR4
IC
C
R3
R2
R4
(a) A circuit.
Note:
- If each of the line/branch in a given graph has a reference direction [as indicated by an
arrow mark], then the resulted graph is called an/a oriented/directed graph.
(p) Example - 05
1A
1V
1
1
(a)
(b)
(c)
Fig. 1.6: (a) A circuit, and its- (b) simplified graph and (c) directed graph.
Note:
- Where direction of flow of currents are not shown in the given circuit diagram, arbitrary
directions may be assigned in each branch before drawing the directed graph.
- When voltage source is not in series with any passive element in the given network, it is
kept in the graph as a branch.
(q) Example - 06
C1
C1
4
R2
R2
RS
R2
R2
C2
R1
C2
RL
RS
RL
v1
R1
C1
Ref.node
C1
(a)
(b)
Fig. 1.7: (a) A circuit, and its- (b) simplified graph and (c) directed graph.
4
5
(a)
(b)
IL
2
Is
I1
R2
R3
3 I2
R4
I3
IC
R1
Is
1
Vs
5
1, 5
(a)
(b)
1
R1
3 IC
2 3
I1
R3
Vs
6
(a)
6 5
(b)
Example - 01:
L
IL
a
R1
I1
R2
2 I2
R3
Is
I3
IC
Vs
4
(a) A Circuit
a
b
a
c
(o) Tree 13
a
c
(p) Tree 14
(m) Tree 11
(n) Tree 12
(j) Tree 8
(l) Tree 10
(f ) Tree 4
(i) Tree 7
(k) Tree 9
b
(h) Tree 6
a
b
(g) Tree 5
(e) Tree 3
a
2
(d) Tree 2
(c) Tree 1
a
c
(q) Tree 15
(r) Tree 16
1
+
vx
15
vx
14
100 V
+
vx
1S
2A
2 S
1V
3
Ref. node
1 S
1
Ref. node
2v x
Ref. node
2S
vy
4vy
+
4
Summary:
- A linear graph is defined as a collection of nodes and branches where nodes are
joined together by branches.
- A subgraph is a subset of branches and nodes of a given graph.
- Point of intersection of two or more branches is called node.
- A circuit elements is represented by lines in a graph and these lines are called
branches of the graph.
- Voltage and current sources may be represented by their internal impedances while
drawing a graph in which a voltage source would be assumed to be an ideal voltage
source and thus would be replaced by short circuit while current source [an ideal
current source] would be replaced by an open circuit to simplify the graph.
References
[1] M. E. Van Valkenburg, Network Analysis, 3/e, PHI, 2005.
[2] W. H. Hayt, J. E. Kemmerly, S. M. Durbin, Engineering Circuit Analysis, 8/e, MH, 2012.
[3] M. Nahvi, J. A. Edminister, Schuams Outline Electric Circuits, 4/e, TMH, SIE, 2007.
[4] D. Roy Choudhury, Networks and Systems, New Age Publishers, 1998.
[5] A. Sudhakar, S. S. Palli, Circuits and Networks: Analysis and Synthesis, 2/e, TMH, 2002.