LABORATORY EXPERIMENTS REPORT FILE

COMPUTER SCIENCE & ENGINEERING

NOV/DEC 2013 SESSION PERFORMED AT

RAYAT COLLEGE OF ENGINEERING

AND TECHNOLOGY, ROPAR

Submitted By

Submitted To

Ravi Kumar Rachuri

Mr Harish Kundra

ST-332396-5

Head Of Department
CSE & IT

INDEX
SL
No
1
2

7
8

10

Laboratory Experiment
Pulse & Digital Circuits
To design a 4-bit synchronous
counter & study its function.
To design a 4-bit asynchronous
counter & study its function.
Data Structures
To obtain the given tree type
structure using a suitable
structure. (Binary Search Tree)
To define a node with the given
structure and to implement
insert, delete & search. (Singly
Linked List)
Programming
To develop a function on C
that splits a list into two other
lists so that the entries that
were
in
odd-numbered
positions are now in one list (in
the same relative order as
before) and those from evennumbered position are in
another new list.
To write a C program to print
the day for an input of date,
month and year.
Computer Architecture
To design on paper a full 18 X
16 barrel shifter.
To design a 4-bit, 8 function
arithmetic unit that will meet the
given specifications.
System Analysis
To draw the systems flow-chart
showing the given steps in
processing customers sales
order.
To describe in detail a pay roll
data processing application
giving inputs, outputs and files
required. Draw the system flowchart and show the structure of
input documents and output
reports.

Date

Page
Number
01-02
03-04

05-06

07-11

12-12

13-13

14-15
16-19

20-21

22-23

Teachers
Remarks
Initials

1
Experiment No: 1 (Pulse & Digital Circuits)
Objective:

To design a 4-bit synchronous counter and study its function.

Requirements:
4 JK flip-flops, Square clock generator, 7-segment LED to display
the decimal number.
Preparation:
In the Asynchronous binary counter, the output of one counter stage is connected
directly to the input of the next counter stage and so on along the chain, and as a result
the asynchronous counter suffers from what is known as "Propagation Delay". However,
with Synchronous Counters, the external clock signal is connected to the clock input of
EVERY individual flip-flop within the counter so that all of the flip-flops are clocked
together simultaneously (in parallel) at the same time giving a fixed time relationship.
Feed the output Q0, Q1, Q2 and Q4 to 7-segment LED.

Counter State & Required Inputs:

Q3

Q2

Q1

Q0

JA

KA

JB

KB

JC

KC

JD

KD

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X

X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1

0
1
X
X
0
1
X
X
0
1
X
X
0
1
X
X

X
X
0
1
X
X
0
1
X
X
0
1
X
X
0
1

0
0
0
1
X
X
X
X
0
0
0
1
X
X
X
X

X
X
X
X
0
0
0
1
X
X
X
X
0
0
0
1

0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1

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2
A 4-bit Synchronous counter made by using JK flip-flops is shown below.

Observation:
It can be seen that the external clock pulses (pulses to be counted) are fed directly to
each JK flip-flop in the counter chain and that both the J and K inputs are all tied
together, but only in the first flip-flop, flip-flop A (LSB) are they connected HIGH, logic 1
allowing the flip-flop to toggle on every clock pulse.
The J and K inputs of flip-flop B are connected to the Q of flip-flop A, but the J and K
inputs of flip-flops C and D are driven from AND gates which are also supplied with
signals from the input and output of the previous stage, If we enable each J-K flip-flop to
toggle based on whether or not all preceding flip-flop outputs (Q) are HIGH we can
obtain the same counting sequence as with the asynchronous circuit but without the
ripple effect, since each flip-flop in this circuit will be clocked at exactly the same time.
Result:
4-bit synchronous waveform diagram is shown below.

The counter counts sequentially on every clock pulse the resulting outputs count
upwards from 0000 to 1111.
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3
Experiment No: 2 (Pulse & Digital Circuits)
Objective:

To design a 4-bit asynchronous counter and study its function.

Requirements:
4 T flip-flops, Square clock generator, 7-segment LED to display the decimal number.
Preparation:
Connect the T flip-flop, input clock as per the below given figure. Connect the four
outputs QA, QB, QC and QD to the input of 7-segment LED. The T-type flip-flop is an
edge-triggered device based on the standard RS flip-flop. They can be triggered to
switch on either the leading or trailing edge of the input clock signal.
A 4-bit Asynchronous counter made by using JK flip-flops is shown below.

Observation:
This type of counter is commonly known as an Asynchronous 4-bit binary counter as the
output on QA to QD, which is 4-bit wide, is a binary count from 0 to 15 for each clock
pulse, with the output of one flip-flop stage providing the clocking signal for the next flipflop stage. This arrangement is commonly known as Asynchronous, Output QA will be
the LSB and QD will be the MSB, as the clocks arrives the corresponding number will get
display in LED increments by one.
Result:
4-bit asynchronous waveform diagram is shown below.

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The counter counts sequentially on every clock pulse the resulting outputs count
upwards from 0000 to 1111.

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5
Experiment No: 3 (Data Structures)
Objective: Determination of Passes, Comparisons and Exchanges for Bubble Sort.
Objective To find expected number of passes, comparisons and exchanges for bubble
sort when n=12 and compare them with actual number of these operations when the
given sequence is as follows:8, 6, 4, 3, 7, 9, 5, 12, 1, 11, 10, 2
Minimum Requirements:
Desktop/Laptop with Windows XP or higher with C compiler.
Bubble sort Implementation:
#include<iostream.h>
#include<conio.h>
int main()
{
int a[10],i,j,n,temp;
cout<<endl<<"ENTER THE NUMBER OF ELEMENTS : ";
cin>>n;
cout<<endl<<"ENTER THE ELEMENTS :";
for(i=0;i<n;i++)
cin>>a[i];
cout<<"\nNUMBER OF PASSES ARE :"<<n-1;
int e=0;
int q=0;
for(i=0;i<n-1;i++)
{
for(j=0;j<n-i-1;j++)
{
if(a[j]>a[j+1])
{
temp=a[j];
a[j]=a[j+1];
a[j+1]=temp;
e++;
}
}q=q+j-1; }
cout<<endl<<"NUMBER OF COMPARISONS ARE : "<<q;
cout<<endl<<"NUMBER OF EXCHANGES ARE : "<<e;
cout<<endl<<"LIST AFTER BUBBLE SORTING IS GIVEN BELOW: ";
for(i=0;i<n;i++)
cout<<endl<<a[i];
getch();
}
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6
Bubble sort Implementation Output Screenshot :-

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7
Experiment No: 4 (Data Structures)

Objective:

To obtain the following tree-type using a suitable structure:

Minimum Requirements:
Desktop/Laptop with Windows XP or higher with C compiler.
Analysis of given structure:
After analysis of this tree structure it is clear that it is a binary search tree. In binary
search tree all the elements in right sub-tree of any node are greater than or equal to the
elements in left sub tree.
Determine the list for obtaining the objected tree structure: For obtaining the given
tree structure using Binary Search Tree the elements order can be as given below:
15, 11, 19, 14, 9, 33, 17, 7, 18, 10, 16
Binary Search Tree Implementation in C:
#include <stdlib.h>
#include<conio.h>
typedef struct tnode {
int data;
struct tnode *right, *left;
} TNODE;
TNODE *CreateBST(TNODE *, int);
void Inorder(TNODE *);
void Preorder(TNODE *);
void Postorder(TNODE *);
main() {
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8
TNODE *root = NULL; /* Main Program */
int opn, elem, n, i;
do {
printf("\n ### Binary Search Tree Operations ### \n\n");
printf("\n Press 1-Creation of BST");
printf("\n
2-Traverse in Inorder");
printf("\n
3-Traverse in Preorder");
printf("\n
4-Traverse in Postorder");
printf("\n
5-Exit\n");
printf("\n
Your option ? ");
scanf("%d", &opn);
switch (opn) {
case 1:
root = NULL;
printf("\n\nBST for How Many Nodes ?");
scanf("%d", &n);
for (i = 1; i <= n; i++) {
printf("\nRead the Data for Node %d ?", i);
scanf("%d", &elem);
root = CreateBST(root, elem);
}
printf("\nBST with %d nodes is ready to Use!!\n", n);
break;
case 2:
printf("\n BST Traversal in INORDER \n");
Inorder(root);
break;
case 3:
printf("\n BST Traversal in PREORDER \n");
Preorder(root);
break;
case 4:
printf("\n BST Traversal in POSTORDER \n");
Postorder(root);
break;
case 5:
printf("\n\n Terminating \n\n");
break;
default:
printf("\n\nInvalid Option !!! Try Again !! \n\n");
break;
}
printf("\n\n\n\n Press a Key to Continue . . . ");
getch();
} while (opn != 5);
}
TNODE *CreateBST(TNODE *root, int elem) {
if (root == NULL) {
root = (TNODE *) malloc(sizeof(TNODE));
root->left = root->right = NULL;
root->data = elem;
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9
return root;
} else {
if (elem < root->data)
root->left = CreateBST(root->left, elem);
else if (elem > root->data)
root->right = CreateBST(root->right, elem);
else
printf(" Duplicate Element !! Not Allowed !!!");
return (root);
}
}
void Inorder(TNODE *root) {
if (root != NULL) {
Inorder(root->left);
printf(" %d ", root->data);
Inorder(root->right);
}
}
void Preorder(TNODE *root) {
if (root != NULL) {
printf(" %d ", root->data);
Preorder(root->left);
Preorder(root->right);
}
}
void Postorder(TNODE *root) {
if (root != NULL) {
Postorder(root->left);
Postorder(root->right);
printf(" %d ", root->data);
}
}

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10
Binary Search Tree Output Screenshot:- Showing Output of Selection 1, 2 and 3

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11
Binary Search Tree Output Screenshot:- Showing Output of Selection 4 and 5.

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12
Experiment No: 5 (Programming Languages)
Objective: To develop a function on C that splits a list into two other lists so that the
entries that were in odd-numbered positions are now in one list (in the same relative
order as before) and those from even-numbered position are in another new list.
Minimum Requirements: Desktop/Laptop with Windows XP or higher with C compiler.
Implementation of the objective:
#include<stdio.h>
#include<conio.h>
int main()
{
int a[20],b[20],c[20];
int i,j,k=0,l=0;
printf ("Please Enter Number of Elements: ");
scanf("%d",&j);
printf("\nEnter the elements in any order!\n");
for(i=0;i<j;i++)
scanf("%d",&a[i]);
for(i=0;i<j;i++)
{
if(a[i]%2==0){
c[k]=a[i];
k++; }
else {
b[l]=a[i];
l++;}
}
printf("The Single list is split into two lists\n");
printf("First List of Even values is given below\n");
for(i=0;i<k;i++)
printf("%d\n",c[i]);
printf("Second List of Odd values is given below\n");
for(i=0;i<l;i++)
printf("%d\n",b[i]);
getch();
}
Output Screenshot:

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13

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14
Experiment No: 6 (Programming Languages)
Objective:

To write a C program to print the day for an input of date, month and year.

Minimum Requirements:
Desktop/Laptop with Windows XP or higher with C compiler.
Implementation of the objective:
//PROGRAMME TO FIND THE DAY FOR ANY GIVE DATE IN DD/MM/YYYY FORMAT
//26 JAN 2014
# include <stdio.h>
# include <conio.h>
# include <string.h>
int main()
{
int month[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31};
char week[7][10] ;
int date, mon, year, i, r, s = 0 ;
strcpy(week[0], "Sunday") ;
strcpy(week[1], "Monday") ;
strcpy(week[2], "Tuesday") ;
strcpy(week[3], "Wednesday") ;
strcpy(week[4], "Thursday") ;
strcpy(week[5], "Friday") ;
strcpy(week[6], "Saturday") ;
printf("\n ENTER A DATE TO FIND THE DAY (dd/mm/yyyy) : ") ;
scanf("%d / %d / %d", &date, &mon, &year) ;
if( (year % 400 == 0) || ((year % 4 == 0) && (year % 100 != 0)) )
month[1] = 29 ;
for(i = 0 ; i < mon - 1 ; i++)
s = s + month[i];
s = s + (date + year + (year / 4) - 2);
s = s % 7 ;
printf("\n THE DAY FOR THE GIVEN DATE IS : %s", week[s]) ;
getch() ;
}
Output:

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15
Experiment No: 7 (Computer Architecture)
Objective:

To design on paper a full 16 bit barrel shifter.

Definition and Design of 16-bit Barrel Shifter:

A barrel shifter is a combinational logic circuit with n data inputs, n data outputs, and a
set of control inputs that specify how to shift the data between put. A barrel shifter that is
part of a microprocessor CPU can typically specify the direction of shift (left or right), the
type of shift (circular, arithmetic, or logical), and the amount of shift (typically 0 to n-1 bits,
but sometimes 1 to n bits).
In this subsection, well look at the design of a simple 16-bit barrel shifter control input
S[3:0] to specify the amount of shift. For example, if the input word is
ABCDEFGHGIHKLMNOP (where each letter represents one bit), and the control input is
0101 (5), then the output word is FGHGIHKLMNOPABCDE. From one point of view, this
problem is deceptively simple. Each output bit rolled by the shift-control s, which each
multiplexer data input connected to the appropriate On the other hand, when you look at
the details of the design, youll see that there are trades-offs in the speed and size of the
circuit.

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16
Let us first consider a design that uses off-the-shelf MSI multiplexers. A 16-input, one bit
multiplexer can be built using two 74x151s, by applying S3 and its complement to the
EN_L inputs and combining the Y_L data outputs with a NAND gate, as we showed in
Figure for a 32-input multiplexer. The low-order shift-control inputs, S2-S0 connect to the
like-named select inputs 151s.
We complete the design by replicating this 16-input multiplexer 16 times and hooking up
the data inputs appropriately, as shown in Figure. The top 151 of each pair is enabled by
S3_L, and the bottom one by S3; the remaining select bits are connected to all 32 151s.
Data inputs D0-D7 of each 151 are connected to the DIN inputs in the listed order from
left to right.

Result:

Input Word
1011110001110011
1111100001110011

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Control Input
S [3:0]
0101
1001

Output Word
1000111001110111
1110011111110000

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17
Experiment No: 8 (Computer Architecture)
Objective: To Design a 4-bit, 8 function arithmetic unit that will meet the following
specifications.
S1
0
0
0
0
1
1
1
1

S2
0
0
1
1
0
0
1
1

S3
0
1
0
1
0
1
0
1

Function
A+B
A+B+1
A+B
A+B+1
A
A+1
A-1
A

Overview:
An arithmetic unit is a combinational circuit that performs arithmetic micro operations on
a pair of n-bit operands (ex. A[3:0] and B[3:0]). The operations performed by an AU are
controlled by a set of function-select inputs. Block diagram of 4-bit AU is given below:

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18
The diagram has four full adder circuits that constitute the 4-bit adder and four
multiplexers for choosing different operations. There are two 4-bit inouts A and B and a 4
bit output D. the four inputs from A go directly to the X inputs of the binary adder. Each of
the four inputs from B is connected to the data inputs of the multiplexers. The
multiplexers data inputs also receive the compliment of B. The other two data imputs are
connected to logic-0 and logic-1, Logic-0 is a fixed voltage value(0 bolts for TTl
integrated circuits) and the logic-1 signal can be generated through an inverter whose
input is 0. The four multiplexers are controlled by two selection inputs, S1 and S0. The
input carry Cin goes to the carry input of the FA in the least significant position. The other
carries are connected from one stage to the next.
The output of the binary adder is calculated from the following arithmetic sum:
D=A+Y+Cin
Where A is the 4-bit binary number at the X inouts and Y is the 4-bit binary number at the
Y inputs of the binary adder. Cin is the input carry, which can be equal to 0 or 1, it is
possible to generate the eight arithmetic micro operations.
1. When S1S0=00, the value of B is applied to the Y inputs of the adder. If Cin=0, the
output D=A+B. If Cin=1, output D=A+B+1. Both cases perform the add micro
operation with or without adding the input carry.
2. When S1S0=01, the complement of B is applied to the Y inputs of the adder. If
Cin=1, then D=A+B+1. This produces A plus the 2s complement of B, which is
equivalent to a subtraction of A-B. When Cin=0, then D=A+B. This is equivalent to
a subtraction with borrow, that is A-B+1.
3. When S1S0=10, the inputs from B are neglected, and instead, all 0s are inserted
into Y Inputs. The output becomes D=A+0+Cin. This gives D=A when Cin=0 and
D=A+1 when Cin =1. In the first case we have a direct transfer from input A to
output D. In second case the value of A is incremented by 1.
4. When S1S0=11, all 1s are inserted into the Y inputs of the adder to produce the
decrement operation D=A-1 when Cin=0. This is because a number with all 1s is
equal to the 2s complement of 1 (the 2s complement of binary 0000 is 1111).
Adding a number A to the 2s complement of 1 produces F=A+ 2s complement of
1=A-1. When Cin=1, then D=A-1+1=A, which causes a direct transfer from input A
to putput D. Note that the micro operation D=A is generated twice so there are
only seven distinct micro operations in the arithmetic circuit.
Design Strategies:
When designing the AU we will follow the principle Divide and Conquer in order to use
a modular design that consists of smaller, more manageable blocks, some of which can
be re-used. Instead of designing the 4-bit AU as one circuit we will first design a one-bit
AU, also called a bit-slice. These bit-slices can then be put toghether to make a 4-bit AU.

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19
Design:
1. Build a macro for logics A and B. This macro should have four inputs(S1, S0, Ai
2.
3.
4.
5.

and Bi) and two outputs (Xi and Yi). Call it bit-slice.
You need two 4-bit registers to store the value A and B.
You need four instances of the macro you built in step 1.
You need four full adders. You can build your own or fined one in the Xillinx library.
Connect four switched to the inouts of the two 4-bit registers (D3, D2, D1 and D0)

6.
7.
8.
9.

respectively.
Use switch to enable one of the registers and disable the other.
Use a button switch as a clock for the two registers.
Connect the outputs of the registers to the proper inputs of the bit-slice macro.
Connect the outputs of the bit-slice macros to the full adder as in below given
figure

10. Use the switches for the control signals S1, S0 and Cin respectively.
11. Import the multiplexed seven-segment display macro you built earlier and connect
the outputs of the register A to the most left display and the output of register B to
the second left display. Connect the outputs of the adder to the right most display
as in Figure.
12. Use three LEDs for over-flow, carryout and signals.

Output:
S1
0

S2
0

S3
0

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Function
A+B

Micro-operations
Add

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20
0
0
0
1
1
1
1

0
1
1
0
0
1
1

1
0
1
0
1
0
1

RAVI KUMAR RACHURI

A+B+1
A+B
A+B+1
A
A+1
A-1
A

Add with Carry

Subtract with Borrow
Subtract
Transfer A
Increment A
Decrement A
Transfer A

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21
Experiment No: 9 (Systems Analysis And Design)
Objective: To draw the system flow chart showing the following steps in processing
sales order:
a) Open the mail.
b) Make an entry in an Order log recording the receipt of each order.
c) Edit the order for missing or erroneous information; if no errors go to (e), else go
to (d).
d) Add any needed information.
e) Check the customers credit rating.
f) Forward orders from customers with bad credit ratings to the credit manager. If
he rejects it, the party is to be intimated: otherwise go to (g).
g) Forward orders from customers to the key punch department.
h) Place the sales order in a file.
i) Sort the sales order cards using computer into item number sequence.
j) Process the sales order cards against the inventory master file producing an
updated master file and a printed listing of each transaction.

Flow - Chart:

CHECK THE EMAIL

MAKE AN ENTRY IN
ORDER LOG FOR
THE RECEIPT OF
EACH ORDER

CHECKIN
G
ERRORS
IN
ORDERS
NO

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YES

REMOVE THE
ERROR OR INPUT
CORRECT
INFORMATION

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22

YES

SEND THESE
ORDERS TO
CREDIT MANAGER

IS CUSTOMER
CREDIT
RATING IS BAD

NO
YES
FORWARD ORDER TO KEY PUNCH
DEPARTMENT

ORDER
APPROVED
BY
MANAGER

NO

PLACE THE SALES ORDER IN A

FILE

SORT THE SALES ORDER

CARDS USING COMPUTER
INTO ITEM NUMBER
SEQUENCE.

INFORM
CUSTOMER ABOUT
ORDER REJECTION

STOP
PROCESS THE SALES ORDER
CARDS AGAINST THE
INVENTORY MASTER FILE
PRODUCING AN UPDATED
MASTER FILE

INVENTORY
MASTER FILE

PRODUCING UPDATED MASTER FILE

PRINT EACH TRANSACTION ON

PRINTER

STOP
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23
Experiment No: 10 (Systems Analysis and Design)
Objective: To describe in detail a pay roll data processing application giving inputs,
outputs and files required. Draw a system flow chart and show the structure of input
documents and output reports.
Definition of Payroll Application:
In a company, payroll is the sum of all financial records of salaries, wages, bonuses and
deductions. Any system which is going to enable the company maintains and manages
paychecks / pay slips, salaries, wages etc., and different levels of employees etc., is
called a Payroll System.
A payroll system is adopted by the employer to process payment of salaries of the
employees. These are various kinds of payroll system; one is an automated
disbursement facility that enables fund transfers from the employers bank account to
various individual accounts of the employees. Under this system, the employer need to
maintain an account which should be sufficiently funded to cover payroll amount of the
employees, including the payroll processing fee, upon transmission of the payroll data for
faster and more convenient crediting of employee accounts.
Inputs for Payroll Application:
The Inputs required are given below:
1. Files having all details of every employee like Name, Address, date of Birth,
Employee ID, Basic Salary, DA, HRA, Joining Date, Category of Employee
(Temporary or Permanent), Department, Designation, Location and PAN No. etc.,
2.
3.
4.
5.
6.

with the basic format acceptable to the payroll system.

Timesheet data for every employee like attendance report.
Leaves record data for each employee like paid and Unpaid leaves.
Employee Bank and PF account details.
File having the details of other finance related information like Loans etc.
Claims related information like food claims, tour claims etc.

Outputs for Payroll Application:

The Outputs are mentioned below:
1.
2.
3.
4.
5.
6.
7.

Payroll Data file from the system should then be sent to the bank.
Pay Slip of employee.
Income tax related files like Form-16.
EPF statement.
Loan statement if any.
Full and Final settlement statement.
Payroll Register.

RAVI KUMAR RACHURI

COMPUTER SCIENCE & ENGINEERING

332396-5

ST-

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8. Claim status report.
9. Employee appraisal report.
Payroll System Provides:
1.
2.
3.
4.
5.
6.
7.

Complete Payroll and Tax Filling Services.

Direct Deposit and Automatic Tax Deposits.
Quarterly and Year End Reporting.
Sick and Vacation Time Tracking.
Processing for Multiple Locations and Divisions.
Time and Attendance Interfaces.
Web Based Employee Self Service System.

Why Payroll System is used?

1. Guaranteed Accuracy
2. Same Day Turnaround
3. Cost Effective Pricing

RAVI KUMAR RACHURI

COMPUTER SCIENCE & ENGINEERING

332396-5

ST-