Path Specific Constraints

Path-Specific
Timing Constraints
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Outline
Inter-Clock Domain Constraints

Multi-cycle Paths
False Paths
Miscellaneous Constraints
Summary
Constraining Between Rising

and Falling Clock Edges
The PERIOD constraint automatically accounts for two-phase clocks
Includes adjustments for non-50-percent duty-cycle clocks
Example: A PERIOD constraint of 10 ns on CLK will apply a 5-ns constraint

between these two flip-flops
No path-specific constraints are required for this case
OUT
CLK
Constraining Between
Related Clock Domains
Create a PERIOD constraint for one clock
Define all related clocks in terms of this PERIOD constraint
The implementation tools will use the relationships to determine how to

cross between clock domains
DCM with multiple outputs:
Define a PERIOD constraint on the input to the DCM

The implementation tools will push the constraint onto each output
All constraints will be defined relative to the original PERIOD constraint
Unrelated Clock Domains
In this example, the delay path between the two clock domains is NOT
covered by either of the PERIOD constraints
You must add a constraint to cover paths when crossing between related
clock domains
This is the default behavior
Example: Same frequency, but CLK_B is phase shifted
You must add a synchronization circuit when crossing between unrelated

clock domains
PERIOD CLK_A
DQ
D Q
PERIOD CLK_B
D Q
D Q
OUT1
CLK_A
CLK_B
To constrain the paths between the two clock domains (highlighted in

gray)
Define groups of registers CLK_A and CLK_B with the Group by Nets option
Automatically done if you have specified a PERIOD constraint for both clock
domains
Place a Slow/Fast Path Exception between the two groups of registers
PERIOD CLK_A
D
5 ns
PERIOD CLK_B
D
OUT1
CLK_A
CLK_B
Step 1: Create the groups

by using the Group by Nets
option
Group by clock net

Skip this step if PERIOD
constraints are defined
Step 2: Create the

constraint by clicking the
Slow/Fast Path Exceptions
button
Enter a name for this constraint
Must begin with TS
Select the groups that define the

constraint
Specify the value of the constraint
Outline

Multi-cycle Paths
False Paths
Summary
Multi-cycle Path Constraints
Multi-cycle paths occur when

registers are not updated on
consecutive clock cycles
Always at least one clock cycle

between updates
Typically, the registers are
controlled by a clock enable
A prescaled counter is one

example
Registers in COUT14 are

updated every 4 clock cycles
Paths between these registers
are multi-cycle paths
200 MHz
CLK
PRE2
Q0 Q1
TC
CE
50 MHz
COUT14
Q2 Q3 Q4
Q14Q15
Creating Multi-cycle Path

Constraints
Step 1: Create a global

PERIOD constraint (not
shown)
Step 2: Create groups by
using the Group by Nets
option
Group by enable net
Step 3: Click the Multicycle Paths button
Creating Multi-cycle Path

Constraints
Enter a TIMESPEC name

Select the groups that were
previously defined
Define the constraint relative to
the PERIOD constraint
Outline

Multi-cycle Paths
False Paths
Summary
False Paths
The False Paths options

will prevent constraints
from being applied to
specific paths
Define False Paths to

reduce the number of
constrained paths in
your design
Defining False Paths
Use the False Paths

(FROM:TO:TIG) button to define
false paths between groups of path
endpoints
TIG = Timing IGnore

Prevents any constraints from being
applied to the paths
Paths through specific nets or 3state buffers can be defined with the
THRU points option
What is wrong with this example?
Defining False Paths by Nets
The False Paths by Nets option

allows you to ignore timing
constraints on a specific net
Any delay path containing the

RESET net will not be
constrained
The Ignored TIMESPECs

option allows specific
constraints to be ignored
TS_P2P constraint will be

ignored on paths containing
the RESET net
Outline

Multi-cycle Paths
False Paths
Summary
Miscellaneous Tab
Assign individual registers to

IOBs
Mark asynchronous registers
Select nets to be routed on the

Low Skew Resources
Prevents X propagation during

simulation
Use for high-fanout control

signals
Assign timing group elements to

area groups for floorplanning
FEEDBACK constraint for DCMs
Define initial values for storage
elements
Prorating Constraints
Prorating allows the tools to use the most accurate information
The implementation tools use the worst-case operating temperature and

voltage for your chosen device package (85 for Commercial, 100 for
Industrial)
Specify your own worst-case conditions
This will prorate the device delay characteristics to accurately reflect your
worst-case system conditions
Timing Constraint Priority
False Paths
Must be allowed to override any

timing constraint
FROM THRU TO
FROM TO
Pin-Specific OFFSETs
Group OFFSETs
Highest
Groups of pads or registers
Global PERIOD and OFFSETs
Lowest priority constraints
Lowest
Timing Constraint
Interaction
Whenever a path is covered by more than one constraint, the tools must
choose which constraint to use for timing analysis
If the constraints are of different types, the highest priority constraint is
applied
If the constraints are of the same type (Example: FROM TO), the
decision is more complex
Can be dictated with the PRIORITY keyword in the UCF file
To see where your constraints overlap, generate a Timing Specification

Interaction (TSI) file
Under Properties for Post-Place & Route Static Timing Report, type in a
filename
In the Timing Analyzer, select Analyze Constraints Interaction
Outline

Multi-cycle Paths
False Paths
Summary
Skills Check
Review Question
Background Information
Prescaled 16-bit counter is created in two blocks
Q0 and Q1 in block PRE2 toggle at 200 MHz

Q[15:2] toggle every fourth clock edge (50 MHz)
The design is fully synchronous because all registers share the same clock
However, COUT14 registers are disabled 3/4 of the time so they do not have to
meet a 200-MHz PERIOD constraint
200 MHz
CLK
PRE2
TC
Q0 Q1
CE
50 MHz
COUT14
Q2 Q3 Q4
Q14Q15
Review Questions
What constraints need to be placed on this design to assure it will meet the
performance objectives?
How would you enter these constraints through the Constraints Editor?
How do multi-cycle path constraints improve your designs performance?
200 MHz
CLK
PRE2
TC
Q0 Q1
CE
50 MHz
COUT14
Q2 Q3 Q4
Q14 Q15
Answers
What type of constraints need to be placed on this design to assure it will

meet the performance objectives?
Global PERIOD constraint of 5 ns (or 200 MHz)

Multi-cycle path constraint of 5 x 4 = 20 ns (or 200 / 4 = 50 MHz)
How would you enter these constraints through the Constraints Editor?
PERIOD constraint: Use the Global tab

Multi-cycle path constraint:
Group the flip-flops in COUT14 by clock enable net (group name: MSB)
Constrain from MSB to MSB
How do multi-cycle path constraints improve your designs performance?
They allow the implementation tools to place some logic farther apart and use
slower routing resources
Review Questions
If a PERIOD constraint were placed on this design, what delay paths would
be constrained?
If the goal is to optimize the input and output times without constraining the
paths between registers, what constraints are needed?
Assume that a global PERIOD constraint is already defined
Status
Register
Control
Register
Control_Enable
BIDIR_PAD(7:0)
BIDIR_BUS(7:0)
Status_Enable
Answers
If a PERIOD constraint were placed on this design, what delay paths

would be constrained?
Paths between the control registers and the status registers would be
constrained
Status
Registers
Control
Registers
Control_Enable
BIDIR_PAD(7:0)
BIDIR_BUS(7:0)
Status_Enable
Answers
If the goal is to optimize the input and output times without constraining the
paths between registers, what constraints are needed?
Enter OFFSET constraints on the Global tab

Define False Paths By Nets
Select the BIDIR_BUS[7:0] nets

Select the global PERIOD constraint to be ignored
Status
Registers
Control
Registers
Control_Enable
BIDIR_PAD(7:0)
BIDIR_BUS(7:0)
Status_Enable
Summary
Use a Slow/Fast Path Exception to constrain paths that cross between

clock domains
Identifying multi-cycle and false paths allows the implementation tools to
make appropriate tradeoffs
These paths will use slower routing resources, which frees up fast routing
for critical signals
Prorating your operating conditions gives the tools the most accurate
picture of your design environment
In general, more-specific constraints have a higher priority than lessspecific constraints
Where Can I Learn More?
Timing Presentation on the Web: http://support.xilinx.com Tech Tips

Timing & Constraints
Constraints Guide: http://support.xilinx.com Software Documentation
Documentation may also be installed on your local machine

Path Specific Constraints

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Path-Specific

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Inter-Clock Domain Constraints

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Constraining Between Rising

The PERIOD constraint automatically accounts for two-phase clocks

Includes adjustments for non-50-percent duty-cycle clocks

Example: A PERIOD constraint of 10 ns on CLK will apply a 5-ns constraint

PDF created with pdfFactory Pro trial version www.pdffactory.com

Create a PERIOD constraint for one clock

Define all related clocks in terms of this PERIOD constraint

The implementation tools will use the relationships to determine how to

Define a PERIOD constraint on the input to the DCM

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This is the default behavior

Example: Same frequency, but CLK_B is phase shifted

You must add a synchronization circuit when crossing between unrelated

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To constrain the paths between the two clock domains (highlighted in

Place a Slow/Fast Path Exception between the two groups of registers

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Step 1: Create the groups

Group by clock net

Step 2: Create the

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Enter a name for this constraint

Must begin with TS

Select the groups that define the

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Inter-Clock Domain Constraints

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Multi-cycle Path Constraints

Multi-cycle paths occur when

Always at least one clock cycle

A prescaled counter is one

Registers in COUT14 are

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Creating Multi-cycle Path

Step 1: Create a global

Group by enable net

Step 3: Click the Multicycle Paths button

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Creating Multi-cycle Path

Enter a TIMESPEC name

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Inter-Clock Domain Constraints

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The False Paths options

Define False Paths to

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Defining False Paths

Use the False Paths

TIG = Timing IGnore

What is wrong with this example?

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Defining False Paths by Nets

The False Paths by Nets option

Any delay path containing the

The Ignored TIMESPECs

TS_P2P constraint will be

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Inter-Clock Domain Constraints

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Assign individual registers to