Photonische Netze 02. 03.05.

2011 in Leipzig

Paper 9

Clock Recovery in Coherent Optical Receivers

Nebojsa Stojanovic, Fabian. N. Hauske, Changsong Xie, Ming Chen
Huawei Technologies Duesseldorf GmbH, European Research Center, Riesstrasse 25, 80992 Munich, Germany
Nebojsa.stojanovic@huawei.com

Abstract
Standard clock recovery schemes with timing phase estimation before or after the 2x2 MIMO FIR filter in digital coherent receivers are analyzed. In particular, the influence of first-order PMD combined with certain SOPs to the timing
estimation is investigated. No scheme has been identified to prove robust timing estimation for all channel conditions.

Introduction

In digital communication systems, the heart of each receiver is a clock recovery circuit that extracts frequency
and phase from incoming data and forces a local clock
source to control the sampling rate and the sampling
phase of the analog-to-digital converter (ADC). The second feature is not too important in over-sampled systems,
as data processing blocks are less sensitive to the sampling phase. However, the sampling phase has to be very
stable over time (see jitter tolerance requirements in ITUT G.8251; not yet updated for 100G systems but frequency scaling is trivial).
Higher level modulation formats are required to fulfill
demands for improved spectral efficiency. Using both polarizations, increasing the number of signal constellation
points, and introducing digital equalization blocks, practically enables systems with 112 Gbit/s dual polarization
(DP) quaternary phase shift keying (QPSK) transmission.
After coherent detection and an optical to electrical conversion, four data signals are processed as shown in Fig.1.
Four ADCs are sampled by a voltage controlled oscillator
(VCO) that is supported by a timing estimation block
consisting of a phase detector and a proportional integral
(PI) filter. Chromatic dispersion (CD) is most efficiently
compensated by frequency-domain filters. Dynamic filters
(finite impulse response FIR; 2x2 multiple-input multiple-output MIMO) compensate for residual CD and polarization-mode dispersion (PMD), and decouple the polarizations. The digital equalizer module applies slow operations/calculations in a software-based digital signal
processing (DSP) part (e.g. frequency estimation, CD estimation, etc.). Fast operations are performed in the
ASIC/FPGA part of the device.
Besides reducing complexity, power dissipation and size,
most critical problems are related to the clock extraction
[1]. Timing information can be extracted after the CD
compensation block. Due to the inherent processing delay, a feed-forward timing recovery employing an interpolator is needed to cope with fast sampling phase variations
(see G.8251). However, the data after the CD compensator still suffer from polarization effects. One of most critical cases is first order PMD with half-symbol differential
group delay (DGD) and maximum polarization mixing

ISBN 978-3-8007-3346-0

Fig. 1 Electrical part of coherent receiver.

(power coupling factor 0.5; rotation angle of 45). As
shown below, all known phase detectors suffer in this
case.
In this paper we investigate various methods for extraction of timing information. We demonstrate the influence
of polarization effects to various timing estimation algorithms employing timing recovery before the dynamic
FIR filter and show the draw-backs of timing estimation
based on the filtered signal after the FIR filter (Fig. 1).

Timing Estimation before FIR

Filter

Several phase detectors have been proposed for digital

systems. Some of them are frequently used in practical
systems. We investigate phase detectors that can be used
in time domain operating within a maximum of two samples per symbol (maximum two-fold over-sampling). In
the following, we refer to samples A and B as the first and
second sample within a symbol duration. Higher oversampling or interpolation significantly increases device
complexity. Our phase detector candidates are:
Mueller and Mller (M&M-PD) [2],
Alexander (Alex-PD) [3], and
Gardner (Gard-PD) [4].
The M&M-PD works on A samples only with a timing
error detector characteristics (TEDC) derived as [5]:

TEDC ( ) = E [a k 1 x(kT + ) a k x(kT T + )]

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(1)

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Paper 9

ples at a half-baud rate (2 samples per symbol):

Tab. 1: Alex-PD

x(kT + T / 2 + )

TEDC ( ) = E x(kT + )
x(kT T / 2 + )

A1
-1
1
-1
1

A2
A3
output
-1
1
-1
1
-1
-1
1
1
1
-1
-1
1
otherwise
0
A1= sign( x ( kT T / 2 + )) ), A2= sign( x ( kT + )) , and
A3= sign( x ( kT + T / 2 + ))
where T refers to the symbol interval, x to the input signal, a to the decision, and to the sampling instant (between 0 and T ). Decisions may be replaced by the sign of
the input signal:

sign( x(kT T + ))x(kT + )

TEDC ( ) = E

sign(x(kT + ))x(kT T + )

(2)

TEDCs of the Gard-PD and the M&M-PD depend on the

input signal swing. The TED maximum (TEDCMAX) of
Alex-PD is equal to 0.5 for a scrambled noise-free signal.
So, we have to compare the TEDC curves carefully.
For the comparison of the phase detector performance, we
simulated a 112 Gbit/s RZ DP-QPSK transmission system
with first-order PMD. Since we assume digital timing recovery after full CD compensation, CD is not considered
in the channel simulation. In the optical path, we used a
45 GHz, 5th order Gaussian filter and the received electrical signal was filtered by a 4th-order, low-pass Bessel filters. All four data paths are used for timing extraction.
The TEDC simulation results are presented in Fig. 2 for
the B2B case. The five curves are related to OSNR values
between 12 and 20 dB (OSNR step of 2 dB). Positive zero
crossings (equilibrium point) correspond to the VCO
sampling phase. The absolute timing phase of each
scheme can be easily adjusted by constant phase shifts to
provide the optimum sampling instant to the timing recovery. The Gard-PD is least sensitive to OSNR variations. In contrast to the other two schemes, its linear characteristic around the equilibrium point allows sampling
phase adjustment by interpolation of samples.
In Fig. 3, we present the TEDMAX parameter (jitter indi-

TEDC

TEDC

TEDC

In this paper we also use Eq. (2) do derive the TEDC (often called s-curve).
The second phase detector (Alex-PD) is most widely used
in digital optical transmission systems. The Alex-PD uses
three samples and generates 0, +1 or 1 at its output.
These outputs are averaged to obtain the TEDC. The
Alex-PD output generation is described in Table 1 (earlylate phase detector; also known as bang-bang phase detector). The Gardner phase detector also uses three sam-

0
-1

-1
-2
0

0.2

0.4

0.6

0.8

0
-1

-2
0

(3)

0.2

0.4

0.6

0.8

-2
0

0.2

0.4

b)

a)

0.6

0.8

c)

Fig. 2: TEDC: a) M&M-PD, b) Alex-PD, and c) Gard-PD

2

1.4
0
15
30
45

TEDCMAX

TEDCMAX

1.2

0
15
30
45

1.5

0.8
0.6

0.5

0.5

0.4

0
15
30
45

1.5
TEDCMAX

1.6

0.2
0
0

10

15
20
DGD [ps]

a)

25

30

0
0

10

15
20
DGD [ps]

25

30

0
0

10

15
20
DGD [ps]

b)

Fig. 3: TEDCMAX at OSNR of 20 dB: a) M&M-PD, b) Alex-PD, and c) Gard-PD

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c)

25

30

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Paper 9

tor of 0.5 (PA=45). As a result from Fig. 2 and Fig. 3, the

Gard-PD proves the best solution among the three PDs.
Therefore, we continue only with the Gard-PD and analyze its performance after the FIR block. It can be shown
that the other two PDs perform very badly after the FIR
filter.

TEDC

1
0
-1
-2
0

3
0.5

a)
2

TEDC

1
0
-1
-2
0

0.5

b)

TEDC

0.5
0
-0.5
-1
0

0.5

c)

TEDC

0.5
0
-0.5
-1
0

0.5

d)
Fig. 4: TEDC at OSNR of 20 dB: a) B2B open loop
b) B2B closed loop c) DGD=18ps PA=45 open
loop d) DGD=18ps PA=45 closed loop.
cator) in channels suffering from 1st-order PMD (OSNR
of 20 dB). Polarization was rotated in steps of 15 from 0
to 45 (polarization angle, PA) and DGD was varied from
0 to 30 ps in step of 6 ps (18 ps is close to T/2). All PDs
fail at a DGD of T/2 combined with a power coupling fac-

ISBN 978-3-8007-3346-0

Gard-PD Performance after FIR

Filter

The 2x2 FIR butterfly filter is applied for polarization decoupling and PMD compensation. We apply the constant
modulus algorithm (CMA) for channel acquisition adjusting the FIR taps. Both samples (A and B) are filtered and
provided to the Gard-PD. For filter update, only the A
sample is employed in the CMA, forcing A samples onto
a unit circle; B samples can adapt to arbitrary values after
filtering.
As the FIR butterfly filter couples the signals and the timing information from both polarizations, timing estimation based on the filtered signal may be corrupted depending on the channel condition (the filter condition respectively). Furthermore, it acts as a timing phase interpolator
maximizing the A sample at the output. Therefore, we assume two extreme situations: First, rapid update of the
FIR filter ideally tracking timing phase changes. Second,
static FIR filter. In the first case, we obtain the TDEC by
iteratively applying a constant sampling phase, adapting
the FIR filter, filtering the signal and applying the GardPD. In the second case, the FIR coefficients are adapted to
a certain sampling phase and kept constant while the timing phase is varied and with the Gard-PD estimating the
timing phase. As expected from the previous results, clear
differences between the B2B case and the most critical
channel are observed. Due to the timing phase interpolation, the rapid FIR update shows one equilibrium point
(Fig. 4, a) while the critical channel experiences two equilibriums (Fig. 4, c), which causes erroneous timing recovery. Also discontinuous jumps from maxima to minima
are observed (compare Fig. 2, right).
In the second case, one TEDC for every sampling phase is
obtained with frozen FIR coefficients adapted to a specific sampling phase. The TEDCs, evaluated at 32 sampling phases within one symbol duration, are presented in
Fig. 4, b) and Fig. 4, d) respectively for the aforementioned two channels. Now we have 32 different TEDCs.
Applying a closed loop simulation, the finite
TEDC/TEDCs are obtained and denoted in Fig. 4 with red
cycles. Closed loop simulation means: stay at current
sampling phase, learn the FIR filter, generate timing information and step one phase increment to the left or to
the right. The same procedure is repeated until we are at
the stable equilibrium phase. We observe that the equilibrium phase/phases of these curves are identical to the
equilibrium phase/phases in the open loop simulation. It
seems that our clock recovery problem is solved if we apply the clock recovery after the FIR block. However, this
is a false conclusion.

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Paper 9

0.5

0
0

0 best
0 worst
15 best
15 worst
30 best
30 worst
45 best
45 worst
10
20
DGD [ps]

0.5

TEDC

TEDCMAX

1.5

0
-0.5

30

-1
0

a)
0 best
0 worst
15 best
15 worst
30 best
30 worst
45 best
45 worst

TEDCMAX

0.6
0.4
0.2

10

20

30

DGD [ps]

b)
Fig. 5: TEDCMAX at OSNR of 20 dB for worst TEDC
case and best TEDC employing both polarizations (top)
and X-polarization only (bottom).

channel imperfections. Some enhancements are visible

but they will be the subject of further investigations.

References

[1] D. Zibar, et al., Proc. ECOC 09, P. 7.3.4 (2009).

[2] K. H. Mueller and M. Muller, Transaction on Comm.
24, 516 (1976).
[3] J. D. H. Alexander, Electron. Lett. 111, 541 (1975).
[4] F. Gardner, Transaction on Comm. 34, 1111 (1986).
[5] H. Meyr , et al., Digital Communication Receivers,
John Wiley & Sons (1998).

Conclusion

Simulation results show that timing information extracted

from the output signal of FIR filters still suffer from

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Fig. 6: TEDC for OSNR=20dB, DGD=24ps, and

PA=15

We now solved the problem for the most critical case

(DGD=18ps, RA = 45) but new problems are caused for
other channels. In Fig. 5 we present TEDMAX values
(like in Fig. 3) for the combination of both polarizations
X+Y and for X polarization only. The worst TEDCMAX
is related to the closed loop simulation. If there are more
equilibrium points, the worst TEDC is selected. The best
TEDCMAX is not related to the equilibrium phase. We
just selected the best TEDC among all sampling phases
(see Fig. 4b or 4d). The best TEDCMAX opens new
doors for further investigations. In Fig. 6, the TEDCs of
the worst case in Fig. 5a are presented. Two TEDCs denoted by cycles are obtained in the closed loop simulation. The worst one is selected and presented in Fig. 5a.
The TEDC with square symbols is the best TEDC also
shown in Fig. 5a and this curve corresponds to sampling
point 1 . However, this curve cannot be acquired in
closed loop simulation. Two solutions are visible for timing information enhancement. First, if there are two
TEDCs select the best one with higher TEDCMAX. Second, find sampling phase 1 , interpolate signal at phase
1 + and use interpolated samples in the clock recovery
block to get the best timing information. There are open
questions how to do it.

0.5

0.8

0
0

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