Professional Documents
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Design
this material is multiple courses
Cortical Neurons
1000s of inputs,
1000s of channel populations,
one output
Equivalent computation ~
400MMAC / neuron
(no learning / growth)
4004 Intel
1980
1970
First VLSI
courses
Synthesis tools
2000
MOSIS
MIPS
First CAD
(Fairchild, 1967)
Handcrafted Design
Every Gate Optimized
Cost only feasible for
government contracts
TI C54
(fixed
point)
1990
Magic (CAD ventures)
1960
Pentium (Intel)
(0.8um)
TMS 32010(NMOS)
VLSI taught
In CMOS
First
Synthesis
classes
FPGAs
In classes
XC2064
Mead &
Conway
100% S/W
(Programmable)
Cost
Cost
100% H/W
(Fixed Function)
Design at
gate level
Design at
Multipliers and Adders Design at Basic Algorithms
(1837)
Fixed function Analog
Vector-Matrix Multiplication
Frequency Decomposition
Adaptive Filters
Classifiers (NN, GMM, HMM)
Programmable Circuits
(FG transistors)
Eliminate mismatch
Programmability
~ x1000 improvement
in power efficiency
Configurable Signal
Processing
Wide accessibility
I = f r
EKV Model
If,r = 2 Ith
ln2
(1+e
((VgVT)Vs,dVd,s)/2UT
DIBL / VA
I = 2 Ith ( e
If = 2 Ith
- e
((VgVT)VsVd)/UT
Above-threshold
((VgVT)VdVs)/UT
(Saturation, Vds > 4UT)
( ((V V )V V ) )2
g
V1
V2
GND
Tunneling
Vtun Junction
GND
StandardCMOS
Datareten.on:
<5V(0.5m)(10year,300K)
Apps:Filters,Dataconverters,
Regulators,etc.
Accuracy~0.1%between
100pA1A~10e
Writedegrada.on(100C):
Vtunincreaselessthan25%
Vinjnegligablechange
(100Cis>109completeFGrewrite)
Impact Ionization
Themeanrateofanimpactioniza.on
collisionishighlyenergydependant
ImpactCurrentispropor.onal
tosourcecurrent
source
n+
p+
gate
drain
p+
Vinj=430mV
n-well
p-substrate
gate
(3)
Channel
(1)
(2)
Drain-to-Channel
Depletion Region
p+
drain
Theinjectedelectronsaregenerated
byholeimpactioniza.ons.
Injec.oncurrentispropor.onalto
sourcecurrent,andisan
exponen.alfunc.onofdc.
E c,oxide
Ev
dr ain
2
el
chann
source
Iout
Gate1
Gate2
Iout
NIPS 1994
Gate1
Gate2
GND
GND
Vdd
Vdd
4C
a2
2C
Vout
a1
a0
8C
a3
4C
a2
2C
a1
C
a0
Vout
GND
GND
tun V
dd
g
V
Industrial Respect
Floating-gate transistors
V tun
V dd
Vg
V tun
M3 Vg
M4
VA
S1
M9
D1
V dd
VB
S2
D2
M 10
M1
In +
M2
Bias
Circuitry
M7
In Itail
M5
V out
M8
M6
Input Offset
Voltage
Reduced to
25V
V. Srinivasan, G. Serrano,
J. Gray, and P. Hasler,
CICC 2005, pp. 739-742.
(Best paper CICC 2005)
Process/ Vdd
0.5um CMOS / 5V
Linearity
10bit (INL/DNL)
Epot Accuracy
Sample Rate
~10MSPS(instrumented)
>100MSPS (on-chip)
Input caps
140fF
Constant Q Filterbanks
Vector-Matrix Multiplication
I1+
I1-
Im+
Vtun Vdd
Im-
outn
I+out
1.5mm
VMM
V3
Vn
Analog Digital
Output(s) Output(s)
V2
Winner-Take-All
V1
ou t
Adaptive Filters
x1
x2
w1
w2
xN
wN
0.3
Steady-state weights
w2 = sin
0.2
0.1
w1 = cos
0
-0.1
-0.2
-0.3
-0.4
0
Rotation parameter(degrees)
A/D
Converter
DSP
Processor
Computer
(digital)
DSP
Processor
Computer
(digital)
Specialized A/D
Real
world
(analog)
ASP
IC
A/D
MMAC/W
Ratio to digital
LowPowerDSPs
0.02 to 0.002
Analog VMM
1 to 30
1000
Analog Filterbanks
30 to 1000
10000
Analog VQ
1 to 10
300
Analog HMM
>1000
> 100000
Digital Signal
Processing
HMM
VQ
Cepstrum
Microphone
ADC
(16bit)
digital
Remaining
DSP
FFT
12
10
8
analog
Lower
digital
cost
~10bit SNR
Lower
analog
cost
Remaining
DSP
2
0
0
10 12
14 16
Analog filter
bank (~FFT)
10bit
[Kucic, et. al. 2001]
Jan 2008
Concept
Simulation
VLSI
Fabrication
Testing
(3 months)
x3
Concept
Simulation/
Synthesis
Testing
VLSI
Fabrication
RASP 2.x:
RASP 2.5, 2.7: 2004-2007
- >50,000 Prog. Analog Devices
- Used by > 100 Eng
x 20
Large-Scale Field
Programmable Analog
Arrays (FPAA)
RASP Programming/Configuration
Program
Vin
Vg
Run (Program)
GND
GND
Vdd
GND
GND
GND
GND
GND
Vd
GND
GND
Vdd
GND
Vout
Vin
CAB Type
row offset
column offset
A
VMM
0
252
VMM
0
216
VMM
0
180
VMM
0
144
VMM
0
108
VMM
0
72
VMM
0
36
VMM
0
0
GP
56
252
GP
56
216
GP
56
180
GP
56
144
GP
56
108
GP
56
72
GP
56
36
GP
56
0
GP
98
252
GP
98
216
GP
98
180
GP
98
144
GP
98
108
GP
98
72
GP
98
36
GP
98
0
GP
140
252
GP
140
216
GP
140
180
GP
140
144
GP
140
108
GP
140
72
GP
140
36
GP
140
0
GP
182
252
GP
182
216
GP
182
180
GP
182
144
GP
182
108
GP
182
72
GP
182
36
GP
182
0
GP
224
252
GP
224
216
GP
224
180
GP
224
144
GP
224
108
GP
224
72
GP
224
36
GP
224
0
VMM
266
252
VMM
266
216
VMM
266
180
VMM
266
144
VMM
266
108
VMM
266
72
VMM
266
36
VMM
266
0
Vout
GND
GND
GND
3mm
3mm
2.8a: General FPAA
2.8b: BioChannel FPAA
2.8c: Sensor FPAA
2.8d: MITE FPAA
a low-power FPGA
On-chip Programming
120 dB DR TIA
9 bit ramp ADC
7 bit DAC
0.35um CMOS
Usedby>100Eng.
Size ~ 3mm x 3mm
I/O pins ~ 56 (100 pin package)
nFET Transistors
Looking Closer at
CAB Components
Node (nm)
Prog #s (M)
TMACs
350
4.0
90
64.0
64
45
256.0
512
Tools?
Are these available anywhere?
Compiled circuits include:
n-th order filters / filterbanks, Capacitive summation / differencing,
Ramp ADC, Algorithmic and Sigma-Delta ADCs, MP3 encoder, WTA,
Analog Distributed Arithmatic, HMM classifiers, Van-der-pol Oscillator
Starting design
at high level
Extensive Library
(working circuits)
Parameter
Translation
Developed
visual tool for
routing (RAT)
Programmable Circuits
(FG transistors)
Eliminate mismatch
Programmability
~ x1000 improvement
in power efficiency
Configurable Signal
Processing
Wide accessibility