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Course : VT-SV :: System Verilog + VIP Development + 1 Complex Project

Course Features :

7 Weeks Course (System Verilog Training in Bangalore, Next Batch Starting Date : 13Dec-2014)
Weekend Course :
o 4 Hours on Saturday & 4 Hours on Sunday(2:00PM - 6:00PM on both days)
o Includes 2 full day practical sessions, one during middle of course, other towards
end of course.
Focused on student developing complete testbench environment, testcases
& debugging
Tools Used : Questasim (Mentor Graphics)
Demo Class : Attend 1st Session of System Verilog Training course as a demo class

Course Fee :INR 10,000/SystemVerilog Training Course Structure:


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SystemVerilog for Advanced Verification


ASIC Verification Concepts
Verification IP Development
Module(IP) Level Verification Project
o Project#1 : SystemVerilog Based Complex Project (USB, MemCtrl, Bridge, etc)
5. SystemVerilog for System on Chip(SoC) Testbench setup
6. Mock Interviews & Groups Discussions
7. Student assignments for weekday practice

Detailed Course Structure :


1. SystemVerilog for Advanced Verification (Session# 1 - 4)
o Classes : Object Oriented Programming
o Arrays, Data Types, Literals, Operators
o Scheduling Semantics, Inter process Synchronization
o Processes, Threads, Tasks and Functions
o Randomization, Constraints
o Interface, Clocking blocks, Program Block
o Functional Coverage
o Assertion Based Verification
o System Tasks & Functions
o Compiler Directives
o DPI
2. ASIC Verification Concepts (Session# 5)
o SoC Verification
o Module Level Verification

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Constrained Random Verification


Coverage Driven Verification
Directed Verification
Assertion Based Verification
Verification IP Development (Session# 6 - 7)
o AXI Protocol Concepts : Features, Signals, Timing Diagrams
o AXI VIP Architecture Development
o VIP Component Coding
o AXI Slave model testcase development
o Testcase debugging
Module(IP) Level Verification Project
o Project#1 : SystemVerilog Based Project (Session# 8 - 12)
Specification analysis
Verification Plan creation
Feature & Scenario Listing down
TB architecture creation
Building Top level verification environment
TB component coding and integration
Sanity test case and environment bring up
Complete test case coding
Building regression test suite
Functional coverage and code coverage analysis
SystemVerilog for System on Chip(SoC) Testbench Setup (Session# 13)
o Project Category : Medium complex SoC
o TB Architecture creation
o Building top level verification environment
o TB component coding and integration
o Sanity test case and environment bring up
o Complete test case coding
Functional, Timing, Power &Performance Tests
Reset Value, Register access, Interrupt, Power Related, Functional Tests
o Building regression test suite
Mock Interviews & Groups Discussions (Session# 14)
o System verilog Interview questions covering all aspects of SV, AXI, AXI-VIP &
Memory controller projects
o System verilog Training group discussion on Projects worked on as part of course
Assignments provided to student during course
o VIP Developmet for one of OCP/Wishbone/APB/Ethernet Protocols
o Verification of PCIEx Physical Layer LTSSM FSM from scrach
o Functional Verifcation of UART/AXI-DMA/OCP2AXI Bridge from scratch

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