CMOS INVERTER

Why CMOS Inverter?

CMOS because it is the dominating technology
of the era.
High Packing Density
Relatively Easy Process

Inverter because it is the nucleus of all digital

designs.
Behavior of more intricate structures (logic gates,
adders, etc.) can be almost completely derived by
extrapolating the results obtained from the
inverters.
CMOS Inverter

CMOS Inverter: A First Glance

V DD
Driven by Output
Of another gate
=> Fanin

PMOS

V in

V out
CL
NMOS

Collective Capacitances
Of Wires and Gates
=> Fanout

CMOS Inverter: Physical View

N Well

VDD

VDD
PMOS

2l

PMOS
In

Contacts

Out
In

NMOS

Out
Metal 1

Polysilicon

NMOS
GND

CMOS Inverter Static Behavior

V DD

V DD
Rp

Vout

Vout
Rn

Vin = VDD

Vin = 0

CMOS Inverter Dynamic Behavior

VDD

Rp

VDD

Charge

Discharge
Vout

CL

Low to High

Vin = 0

Vout
CL

Rn

High to Low

Vin = V DD

Gate response time is determined by the time to charge CL through Rp

(discharge CL through Rn)

CMOS Properties
Full rail-to-rail swing
High noise margins
Logic levels not dependent upon the relative
device sizes => Ratioless
Transistors can be minimum size
Regenerative Property

Low output impedance

Large Fan-out (albeit with degraded performance)
Typical output resistance in k range.
CMOS Inverter

CMOS Properties (2)

Extremely high input resistance (MOS
transistor is near perfect insulator)
nearly zero steady-state input current

No direct path between power and ground

under steady-state (but there always exists a
path with finite resistance between the output
and either VDD or GND)
no static power dissipation

Propagation delay a function of load

capacitance and resistance of transistors
CMOS Inverter

NMOS Short Channel I-V Plot Recap

2.5

X 10-4

VGS = 2.5 V

2
VGS = 2.0 V

1.5
VGS = 1.5 V

VGS = 1.0 V

0.5
0
0

0.5

1.5

2.5

VDS (V)
NMOS transistor, 0.25 m, Ld = 0.25 m, W/L = 1.5, VDD = 2.5 V, VT = 0.4 V
CMOS Inverter

PMOS Short Channel I-V Plot Recap

All polarities of all voltages and currents are reversed

-2

VDS (V)

-1

0
0

VGS = -1.0 V

-0.2
VGS = -1.5 V

-0.4
VGS = -2.0 V

-0.6
-0.8

VGS = -2.5 V

-1
X

10-4

PMOS transistor, 0.25 m, Ld = 0.25 m, W/L = 1.5, VDD = 2.5 V, VT = -0.4 V

CMOS Inverter

10

Transforming PMOS I-V Plot

NMOS and PMOS VTC must be put into a common coordinate

set of Vin, Vout, and IDn
IDn

IDSp = -IDSn
VGSn = Vin ; VGSp = Vin - VDD
VDSn = Vout ; VDSp = Vout - VDD

VGSp = -1
VGSp = -2.5

Vout

Vin = 0

Vin = 0

Vin = 1.5

Vin = 1.5

Mirror around x-axis

Vin = VDD + VGSp
IDn = -IDp
CMOS Inverter

Horiz. shift over VDD

Vout = VDD + VDSp
11

CMOS Inverter Load-Line Plot

PMOS

NMOS

X 10-4

2.5

Vin = 0 V

Vin = 2.5 V
2

Vin = 0.5 V

Vin = 2.0 V

1.5

Vin = 1.0 V
1

Vin = 1.5 V

Vin = 1.5 V

Vin = 1 V

Vin = 2 V

Vin = 0.5 V

0.5

Vin = 1.5 V

Vin = 1.0 V

Vin = 2.0 V

Vin = 0.5 V

Vin = 2.5 V

0.5

1.5

Vout (V)

2.5

Vin = 0 V

CMOS 0.25 m, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5 V, VTn = 0.4 V, VTp = -0.4 V
CMOS Inverter

12

CMOS Inverter VTC

Vout (V)

* VTC = Voltage-Transfer Characteristics

NMOS off
PMOS res

2.5

NMOS sat
PMOS res

2
1.5
NMOS sat
PMOS sat

Vin

Vout

nmos

pmos

2.5

Vgsn<vtn
Cutoff

0>-2.1
linear

0.5

2.4

2.4>0.1
sat

-0.1>-1.6
linear

2.3

2.3>0.6
sat

-0.2>-1.5
linear

1.25

1.25>0.85
sat

-1.25<-0.85
sat

1.5

0.4

0.4<1.1
linear

-2.1<-0.6
sat

2.0

0.2

0.2<1.6
linear

13
-2.3<-0.1
sat

2.5

0<2.1

Vgsp>=vtp

NMOS res
PMOS sat NMOS res 1.0
PMOS off
1.25

0.5
0
0

0.5

1.5
Vin (V)

CMOS Inverter

2.5

Load Line Analysis

Vin = 0 0.2V

DD

|
Idsn
dsn, |Idsp
dsp

0.4VDD 0.6V
DD

0.8VDD

VDD

Vin0

Vin5
in5

Vin1

Vin4

Vin2

Vin3

Vin3
Vin4

Vin2
Vin1
in0
Vout
out

VDD
DD

20

Region 3/Region C