UNIT-III SEQUENTIAL LOGIC CICUITS

PART A
1. Differentiate Flip-Flop from Latches.
[May 2010]
2. Draw the excitation table and state diagram for JK and SR Flip-Flop. [May 2010]
3. Write down the differences between sequential and combinational circuit? [Nov 2009]
4. What is race around condition?
[Nov 2009]
5. How many flip-flops are required for designing synchronous MOD 5 counter?
[May 2009]
[May 2009]

6. What is shift register? List the types.

7. Convert a T-FF into an sr-FF. Draw the circuit.
[Dec 2008]
8. Draw the state diagram of a MOD-10 counter.
[Dec 2008]
9. What are the differences between sequential and combinational logic? [May
10. Draw the logic diagram for D-Type Latch.
[May 2008]
11. How can a D flip flop be converted in to a T flip-flop?
[May 2007, Nov 2005]
12. How many states are there in a 3-bit ring counter? What are they?
[May 2007]
13. What is meant by the term edge triggered?
[Dec 2007]
14. How does a J-K flip flop differ from an S-R flip-flop in its basic operation.
[Nov 2006]

15. Define Synchronous counter.

[Nov 2006]
16. What are the memory elements used in a clocked sequential circuit?
[May2006]
17. What is meant by state diagram?
[Nov 2005]
18. List out at least four applications of FFs
[Nov 2005]
19. What are the states of a 4-bit ring counter
[Nov 2005]
20. What are the principal between synchronous and asynchronous counters?
[Apr 2005]

21. Distinguish between combinational logic circuits and sequential logic circuits?
[Apr 2005]

22. What are the advantages of shift registers?

[May 2005/Nov 2003]
23. Derive the characteristic equation of T flip flop
[May 2004]
24. What is the minimum of Flip flops required to build a counter of modulus 8
[May 2004]

25. Define propagation Delay.

[May 2004]
26. Define rise time and fall time?
[May 2004]
27. What is edge-triggered flip-flop?
[May 2004]
28. How will you convert a JK flip-flop into a D-flip flop?
[Nov 2003]
29. What is a shift register?
[Nov 2003]
30. What are the various types of triggering of FFS
[Nov 2003]
31. The t pd for each flip-flop is 50 ns. Determine the maximum operating frequency
for MOD - 32-ripple counter
[Nov 2003]
32. Why is a parallel counter faster than ripple counter?
[Nov 2003]

PART B
1. Design a synchronous sequential circuit using JK flip-flop to generate the following
sequence and repeat. 0, 1, 2, 4, 5, 6
[May 2010]
[May 2010]

2. Design and implement a Mod-5 synchronous counter using JK flip-flop.

Draw the timing diagram also.
[Nov 2009]

2008]

3. (i)Explain the working of master slave JK flip-flop.

(ii)Draw the diagram for a 3 bit ripple counter.

[Nov 2009]

(iii) Draw the logic diagram of a D-FF using NAND gates and explain.
[Dec 2008]
4. With a neat circuit explain a universal shift register.
[Dec 2008]
5. Design a T-FF giving the flow table, state table, state assignment, excitation table
and excitation map.
[Dec 2008]
6. Design a 3 bit binary Up Down counter
[May 2008]
7. Explain the operation of 4-bit binary ripple counter.
[Dec 2007]
8. Explain the operation of BCD counter.
[Dec 2007]
9. Explain the operation of D-Type Edge triggered flip-flop. [May 2007]
10. What are the general capabilities of universal shift register?
11. Draw the Four bit Johnson counter and explain its operation.
[Nov 2006]
12. a)Design an Asynchronous BCD down counter using J-K flip=flop and verify
its operation.
[May 2006]
b) What are Edge triggered flip-flops.Discuss.
13. Design a synchronous mod-8 down counter and implement it
[Nov 2005]
14.Design a sequence detector circuit with a single input line and a single output
line.Whenever the input consists of the sequence 101,the output should be 1.For example, if
the input is 00110101then the output is 00000101. In other words, overlapping
sequences are allowed. Use any type of flip flop.
[Nov 2005]

15. Design a modulus 5 counter using JK flip flop and implement it. Construct its
Timing
diagram
[Nov 2005]
16. What is race around condition? How is it avoided?
[Nov 2005]
17. Draw the schematic diagram of Master slave JK FF and input and output
waveforms. Discuss how does it prevent race around condition. [Nov 2005/May 2005/
Nov 2006]

18. Design and explain the working of a synchronous mod-3 counter

[May 2005]
19. Design and explain the working of a up-down ripple counter.
[May 2005]
20. Using JK flip-flops design a parallel counter, which counts in the sequence
101,110,001,010,000,111,101
[Nov 2004]
21.Using SR flip-flops design a parallel counter, which counts in the sequence
000,111,101,110,001,010,000.
[May 2004]
22.Draw the state diagram and characteristic equation of TFF, DFF, and JKFF
[Nov 2003]