AbstractRecently multilevel inverters (MLIs) got wide popularity as it gives much similarity in the output voltage

waveform of that of ideal inverter. Many topologies are existed for MLIs. A new topology that gives better performance
in reduction of switch count is also there in the field of MLIs. This new topology uses Sinusoidal Pulse Width Modulation
(SPWM) as the control strategy. Even though it gives better results over the other existing topologies, but suffers some
problems especially in the case of THD (Total Harmonic Distortion). For the nine level inverter, new topology gives
harmonics content that is much larger than tolerance limit, which is specified by IEEE standards, for industrial
application. This paper presents the performance characteristics of new topology with SVM (Space Vector Modulation)
using MATLAB Simulink platform. Simulation results show that THD can be reduced to the level that is admissible for
both domestic and industrial applications.
Keywords-Multilevel Inverter, THD, SPWM, Space Vector Modulation

1. INTRODUCTION

The necessity for the inverters has been increased with the popularity of the renewable energy sources. This is
mainly because majority of such sources are producing energy in terms of DC and large number of the loads are of
AC type. Inverters behave as a connection link in between DC source and AC load. Ideal inverter output is perfect
sinusoidal waveform and that of practical inverter is either square wave or quasi square wave. A MLI (Multi Level
Inverter) will give better performance as it gives stepped output voltage waveform which resembles sinusoidal
waveform [1-2]
First multilevel inverter was introduced by Nabae, Takashi and Akagi in 1981[3] that was a Diode clamped
multilevel inverter having three level at the output voltage waveform. In this topology, DC bus voltage is split into
number of levels by bulk capacitors, connected in series. Since then so many topologies were introduced. Flying
capacitor multilevel inverter was proposed by Meynard [4]. The presence of capacitor, in this topology will make
the advantage of prevention of filter demand. But the overall system will be costly and bulky. Further more accurate
charging and discharging of the capacitors should be ensured. In Cascaded H-Bridge multilevel inverter topology,
single phase inverters are connected in series with separate DC sources [5]. This
topology got wide popularity since it can be effectively utilized for the system having more than one DC source and
is suitable in the interface with different renewable energy sources.
Besides the successful combination of two or more existing topologies also was introduced as new topologies. They
are collectively called as Hybrid topologies [6-8].
MLI control strategies can be divided into two, according to the switching frequency as shown in Fig 1

Recently another topology is presented by Krishna Kumar Gupta, Shailendra Jain in the paper A multilevel
Voltage Source Inverter (VSI) to maximize the number of levels in output waveform [9]. This method has many
advantages such as reduction in switching losses, size and cost of the inverter. This is due to the reduction of heat
sinks and other protective components in the circuit. The control strategy adopted for their work was SPWM
(Sinusoidal Pulse Width Modulation) for generating switching pulses.
Even though this topology gives superior performance, compared to other topologies, it still suffers all the
disadvantages of the conventional SPWM technique.
Here in this paper, an alternative is made to improve the performance of the model described in [9] by incorporating
SVM (Space Vector Modulation) instead of SPWM. The simulink results are also presented in this paper.

2. ABOUT THE NEW TOPOLOGY

For the nine level output voltage waveform, the new topology utilizes two DC sources and eight power electronic
switches as shown in Fig 2.
These eight switches are represented by T 1 to T4 and the two DC sources are by E1 and E2 . V0 is the output voltage
across the AC load. Switches T 1 and T1 , T2 and T2 , T3 and T3, and T4 and T4 are complementary switches. For
generating any level 3 of the 8 switches needed to be ON. To avoid the redundancy condition in the output voltage
level, the authors suggest Trinary selection Rule

The modulation strategy used here will give a THD of 11.40%. According to IEEE standards the acceptable level of
THD for domestic application is 20% and that for industrial applications is only 5%. So the new method only can be
used for domestic applications only and is the main drawback of this system.

3. IMPLEMENTATION OF SVM IN NEW TOPOLOGY

The basic idea of SVM is that, the realization of `Vref ' in terms of known vectors and predetermining ta and tb. To
realize `Vref ' in terms of known vectors a simple way is selected, in which only basic laws associated with triangles
are included. The method adopted for the realization of `Vref ' can be described briefly as follows. Sampling time,
Ts must be as minimum as possible. 0.0002 sec. is selected as Ts here. That is, after each 0.0002 second, the
reference signal gets sampled and fresh values of `ta' and `tb' will be given out after each sampling. By this way the
entire 2-D plane can be included in the sampling process. This is the case of an inverter having single DC source. 12
V and 36(=3*12)V are used as two DC sources, according to trinary selection rule [9]. Possible nine level
combination that can be generated with these two DC sources are 48(=36+12)V, 36 V, 24(=36-12)V, 12 V, 0 V, -12
V, -24(=- 36+12)V, -36 V, -48(=-36+-12) V. Consider the positive values of combination of voltages, 48 V, 36 V,
24 V and 12 V. We can draw the circles, having radius equal to the level at the output. So constructed the circles
having radii of 12, 24, 36, 48 units to represent 12, 24, 36, 48volts respectively. Possible combinations of voltage
levels at the first sector can be represented as shown in TABLE I .The principle used to determine the combination is
that sum of instantaneous voltages in three phase system is zero. Corresponding V and V values are also
represented in TABLE I.
Circles that present DC voltages and the 15 vertices, namely V0 to V14, can be incorporated simultaneously as
shown in Fig 3.
By giving 30 degree advancement to the Fig 3. We can easily proceed it as normal method of SVM.
The magnitude of V1 is
V1 = [(V)^2 + (V)^2]^(1/2) ---(1)
Similarly magnitude of each vertex from origin, V0 can be calculated. The diagram for first sector after 30 degree
advancement can be shown in Fig 4.
The method of realization of Vref can be explained with the sector diagram given in Fig 4. The realization procedure
can be proceeded, only when the magnitude of Vref is known.
24 V, the tip of vector will be between the arcs `ab' and `cd'

These conditions can be divided into two cases.

Case-1
Let Vref 12 V, then the vector Vref can be realized by the vertices V1 and V2 and Va and Vb are the components
of Vref along V1 and V2 axes respectively. This is shown in Fig 5.
. So corresponding time periods for V1 and V2 can be calculated as
Va*Ts = V1* ta ---(2)
therefore,
ta = Va*Ts/V1 ---(3)
Here Va, Ts and V1 are known values. So ta can be calculated from the equation 3, easily. Similarly
tb = Vb *Ts/V2 ---(4)
Once ta and tb are calculated, we can calculate zero voltage time period, t0 as
t0 = Ts - (ta + tb) ---(5)

Here the tip of the reference vector is within the arc `ab'. That is if the tip of Vref is within `V0' and `ab', we can use
this method. By this way we can calculate both active and zero time periods of areas within V2' and `cd', which
represents in Fig 6. Then Vref can be realized either with the vertices V0, V3, V5 or V2, V4, V5. Here second group
of vertices is taken for the sake of simplicity.
The same method can be used for the reference vector having tip is within V1' and `cd'
Case-2
If the tip of Vref is between the arcs `ab' and `cd' and not in previous considerations. For the easy analysis we can
split the area into two by drawing a line combining the vertices V0 and V4. This will divide the shaded portion into
upper half and lower half. This is shown in Fig 7. As both the method of analysis for both the halves are same, here
only considers upper half. From the laws of triangles, we canresolve Vref in terms of known parameters. As both the
method of analysis for both the halves are same, here only considers upper half. From the laws of triangles, we can
resolve Vref in terms of known parameters and the results are given in the diagram give Fig 8.
The corresponding time periods can be find out then.
From the above mentioned two cases, we can resolve all the possible Vref values for nine level inverter, not only for
the first sector but also for the entire 2-D plane

4. SIMULATION RESULTS

The results are validated with the MATLAB-R2013a/Simulink software tool. Various results are analysed such as
output voltage, output current, THD, voltage stress across the particular switch and power dissipation across the
switch. System frequency is set as 50 Hz. E1 is arbitrarily selected as 12 V. So E2 will be 36, according to Trinary
selection rule. 0.0002 sec is selected as Ts here. Simulation resuls such as output voltage, THD spectrum were
represented in Fig 9. and Fig 11 respectively.
Here the THD spectrum shows that by providing SVM in new topology, the harmonic content level will be
admissible for both domestic and industrial applications(ie, below 5%).
5. RESULT ANALYSIS
Various electrical parameters such as fundamental voltage (Vfund), THD, maximum voltage stress across any
particular switch (Vstress), maximum current through that swich (Isw) are analysed in Table II

6. CONCLUSION

The new topology requires less number of switches than existing topologies. Hence the novel topology will reduce
the switching losses, size and overall cost of the system. SPWM was used as control strategy for the novel topology
THD observed was greater than 5%, so cannot be used for industrial applications, according to IEEE standards. This
paper analysed the implementation of SVM in new topology. Simulation results show that THD got improved in
SVM as compared to that of conventional SPWM and is admissible for both domestic and industrial applications.