SEMESTER III

EC201

DIGITAL ELECTRONICS
(Common to CSE, ECE, EEE, EIE, IT, Mechatronics)

LTPC
3 10 4

COURSE OBJECTIVES

To introduce the basic postulates of Boolean algebra and the methods for simplifying
Boolean expressions.
To outline the formal procedures for the analysis and design of combinational and
sequential circuits.
To expose the Verilog HDL

UNIT I
MINIMIZATION TECHNIQUES AND DIGITAL LOGIC FAMILIES
9+3
Review of Number Systems, Boolean algebra, Postulates and Laws, Demorgans theorem,
Principle of Duality. Minimization Techniques: Boolean Expressions, SOP, POS, K-Map,
Tabulation Method, Dont Care Conditions .Digital Logic Families: Logic Gates, NAND,
NOR Implementation, Comparison of RTL, DTL, TTL.
UNIT-II
COMBINATIONAL LOGIC CIRCUITS
9+3
Combinational Logic Circuit Design: Adders, Subtractors, Multiplexer, Demultiplexer, Encoder , Decoder , Parity Checker and Generator , Code Converters : Binary to
Gray, Gray to Binary , Excess3 to BCD , BCD to Excess 3 , 2 bit Magnitude Comparator.
UNIT-III
SYNCHRONOUS SEQUENTIAL CIRCUITS
9+3
Latches: SR, Clocked SR, Flip Flops: SR, JK, D, T - Characteristic Table and Equation Edge and Level Triggering. Analysis & Design of Synchronous Sequential Circuit :
Analysis and Design Procedures, Synchronous Counters , Modulon Counters , 3 Bit
Up/Down Counter , Shift Registers : SISO, SIPO, PISO, PIPO, Moore and Mealy Models ,
State Diagram , State Table , State Reduction , State Assignment.
UNIT-IV
ASYNCHRONOUS SEQUENTIAL CIRCUITS
9+3
Analysis and design procedures of asynchronous sequential circuits -Asynchronous Counters:
Ripple counter, Decade counter, Transition Table, Flow Table, Race Conditions, Hazards.
UNIT-V
MEMORY DEVICES AND HDL PROGRAMMING
9+3
Memory Devices: RAM, Static RAM, Dynamic RAM, ROM, PROM, EPROM, PLD, PAL,
and PLA.

HDL Programming for Combinational and Sequential Circuits: Introduction to Verilog

HDL , Verilog HDL for Combinational Circuits :Adder , Subtractor, Encoder, Decoder,
Multiplexer, Demultiplexer , Verilog HDL for Sequential Circuits : Flip Flops - D, Modulo-n
Counter, Shift Registers.
L: 45, T: 15, TOTAL: 60

TEXT BOOK
1. M. Morris Mano, Digital Design, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 / Pearson
Education (Singapore) Pvt. Ltd., New Delhi, 2003. [UNIT I-V]
REFERENCES
1. S.Salivahanan and S. Arivazhagan, Digital Circuits and Design, 3rd Edition., Vikas
Publishing
House Pvt. Ltd, New Delhi, 2006.
2. John.M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2006.
3. Charles H.Roth. Fundamentals of Logic Design, 6th edition, Thomson Learning, 2013.
4. Tephen Brown, Fundamentals of Digital Logic with Verilog Design, 2nd Edition, Tata
Mc Graw
Hill.
COURSE OUTCOMES
At the end of the course, the students will be able to

Understand basic minimization techniques and logic gates.

Design and implement combinational and sequential circuits.
Analyze combinational and sequential circuits using Verilog HDL.

EC 204

DIGITAL ELECTRONICS LABORATORY

(Common to CSE, ECE, EEE, EIE, IT, Mechatronics)

LT PC
0 0 3 2

COURSE OBJECTIVES
To design and Implement Digital circuits using logic gates
To expose to sequential and combinational circuits.
To Simulate Digital circuits using Verilog Hardware Description Language.
LIST OF EXPERIMENTS
1. Verification of Boolean Theorems using digital logic gates.
2. Design and implementation of Adder and Subtractor using logic gates.
3. Design and implementation of code converters using logic gates
4. Design and implementation of odd/even parity generator / checker.
5. Design and implementation of 2 bit magnitude comparator.
6. Design and implementation of encoder and decoder.
7. Design and implementation of application using multiplexers/ demultiplexers.
8. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops.
9. Design and implementation of 3 bit synchronous and asynchronous counters.
10. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple
Counters
11. Simulation of combinational circuits using Verilog Hardware Description Language.
12. Simulation of Sequential circuits using Verilog HDL.
L: 0, T: 0, P: 45 TOTAL: 45

COURSE OUTCOMES
At the end of the course, the students will be able to

Understand the concepts and methods of digital system design techniques.

Design combinational and sequential circuits using logic gates
Design and implement combinational and sequential circuits using HDL