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10.1109/JESTPE.2014.2313185, IEEE Journal of Emerging and Selected Topics in Power Electronics
*
abc
C1
d
d-q
f
fs
Hac
Hdc
Iin
IL1
IL2
Io
L1, L2
Ts
Vc1
Vc2
Vin
Vo
Z
NOMENCLATURE
Reference value of a variable
Three-phase stationary frame
Cuk converter capacitor
Cuk converter instantaneous duty ratio
Direct and quadrature synchronous frame
Output voltage fundamental frequency
Sampling frequency
ac voltage ratio
dc voltage ratio
Total input current
Cuk converter input current
Cuk converter output current
Peak value of load three-phase current
Cuk converter input and output inductors
Sampling time
Cuk capacitor voltage
Cuk output voltage
Cuk input voltage
Output load three-phase voltage
Load impedance
Phase angle of load three-phase current
Steady state Cuk converter duty ratio
Phase angle of Cuk three-phase voltage
I. INTRODUCTION
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(1a)
dv c1
1
=
i L1
dt
C1
(1b)
x 1 = A1 x 1 + B1 V in
(1c)
v o1 Y 1 x 1
(1d)
1
A1
C 1
Y 1 0
0
ii)
-1
L1
0
0
1
0
L
0 , B1 0
-Z
0
L2
Z , x 1 i L1
v c1
(1e)
i L2
(2a)
dv c1
1
=i L2
dt
C1
(2b)
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x 2 = A 2 x 2 + B 2 V in
(2c)
v o2 Y 2 x 2
(2d)
A 2 0
Y 2 0
0
L
0
1
1
, B2 0
C1
-Z
0
L2
0
0
1
L2
Z , x 2 i L1
v c1
ratios between output and input are Hdc and Hac respectively,
(4) explains the relation between the input and output voltage:
V c 2a H a V in
(4a)
H a H dc H ac sin(t )
V c 2b H b V in
(2e)
H b H dc H ac sin(t
V c 2c H c V in
2
)
3
(4b)
2
)
3
(4c)
H c H dc H ac sin(t
i L2
Averaging the state space equations over the period [0 < t <
Ts] assuming the duty ratio d=
Ha ,
Hb
and H c
b
c
H a 1
H b 1
H c 1
(4d)
A A1 (1 d ) A 2d
B B1 (1 d ) B 2d
(3a)
Y Y 1 (1 d ) Y 2d
x Ax BV in
(3b)
v o Y x
(1 d )
0
L1
(1 d )
A
0
C1
0
L
2
Y 0
0
Z , x i L1
1
0
L
d
,B 0
C1
-Z
0
L 2
V c1
(3c)
I L 2b
1-
(3e)
G i,ss
1-
1
Gv,ss
c 2a
1
V
3Z
1
V
3Z
1
V
3Z
c 2b
2
V
3Z
c 2b
1
V
3Z
1
V
3Z
c 2c
c 2a
(5a)
c 2c
(5b)
2
)
3
1
2
V c 2b
V
3Z
3Z
2
I o sin(t
)
3
c 2c
(5c)
L 1 I L1
t
V in
L1
I L1 f s
I L 2
V o L2
t
Vo
L2
I L2 f s
(3f)
c 2a
I o sin(t
I L 2c
( Z 2Zd + d 2 Z )
Gv,ss
2
V
3Z
I o sin(t )
i L2
Zd(1 - d)
Gv
3
C1 L1 L 2 s C 1 L1 Zs 2 s(L 2 2dL 2 d 2 L 2 )
I L 2a
in
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(6a)
(6b)
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10.1109/JESTPE.2014.2313185, IEEE Journal of Emerging and Selected Topics in Power Electronics
Value
50 Vdc
50 A
50 Vac
33.33 A
1.5
0 and 0.667
50 kHz
0.667 A
0.667 A
20 V
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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DC/AC Cuk
Buck-boost
Inverter
Vin
Vc2_abc
1,2 .. 6
Vdqo*
Vc2_abc
Vdqo
dqo
dqo
dqo
PI
Controller
abc
Gate Driver
abc
V*
abc
Kp s + Ki
s
D1 = 0.1
D2 = 0.3
D3 = 0.5
D4 = 0.75
D5 = 0.85
0.5
Imaginary Axis
Pole-Zero Map
x 10
-0.5
-1
-1000
-800
-600
-400
-200
Real Axis
4
Amplitude
x x X
vo v o V o
d d D
X, Vo and D are the steady state values of x, vo and d
D1 = 0.1
D2 = 0.3
D3 = 0.5
D4 = 0.75
D5 = 0.85
x ax bd
vo yx
2
1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (sec)
100
80
(1 D )
a
C1
y 0
60
40
20
0
0.02
(7a)
0.03
0.04
0.05
time (s)
0.06
0.07
0.08
(1 D )
L1
0
D
L2
Z , x iL1
V c1
0
L
1
( I I )
D
L1
L2
,B
C1
C1
-Z
V c1 Z
I
L2
L
L 2
L
2
2
vc1
iL2
(7b)
where; Vc1, IL1 and IL2 are the steady state values of
vc1, iL1 and iL2 respectively
In order to ease the control design process, a point at the
middle of the trajectory in Fig. 5a, where d = 0.5, is chosen to
be an intermediate operating point. The poles loci of the
closed loop system of (7b) are plotted in two different ways.
In Fig. 7a, Ki is held constant at 0.7 and Kp is varied in the
range [0.1:0.8]. Similarly, Fig. 7b shows Kp held constant and
Ki varied from [0.1:0.8]. From Fig. 7a, increasing the
proportional value drives the poles toward the right hand side.
From Fig. 7b, the imaginary poles are locked in their loci
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while the real poles move away from the origin to the left
hand side. The gain values are selected by compromising
between both cases. From Fig. 7a and 7b, selecting Kp = 0.3
and Ki = 0.4 provides preliminary proper dynamic
performance and stability margin from the imaginary axis.
1000
Imaginary Axis
Imaginary Axis
2000
-1000
-2000
-3000
-100
0
Kp
Kp
Kp
Kp
Kp
Kp
Kp
Kp
-1000
-2000
-90
-80
-70
-3000
-60
-50
-100 -40
-90
Real Axis
=
=
=
=
=
=
=
=
-30
-80
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Kp
Kp
Kp
Kp
Kp
Kp
Kp
Kp
-20
-70
-10
-60
-50
0
-40
Real Axis
-30
=
=
=
=
=
=
=
=
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
-20
-10
140
3000
Vc2a
Vc2b
Vc2c
120
100
80
60
40
20
0
0.08
0.09
0.1
0.11
0.12
0.13
time (s)
0.14
0.15
0.16
60
50
Vd and Vq (V)
3000
1000
Ki = 0.1
Ki = 0.2
Ki = 0.3
Ki = 0.4
Ki = 0.5
Ki = 0.6
Ki = 0.7
Ki = 0.8
-1000
-2000
-3000
-100
Vd*
Vd
Vq*
Vq
30
20
10
0
-10
0
0.02
0.04
0.06
0.08
time (s)
0.1
0.12
0.14
0.16
-90
-80
-70
-60
-50
-40
Real Axis
-30
-20
-10
40
Vo (V)
Imaginary Axis
2000
40
20
10
0
-10
0
0.05
0.1
0.15
time (s)
three-phase output Current (A)
60
40
20
0
-20
-40
0.08
0.1
0.12
time (s)
0.14
0.16
30
IL2a
IL2b
IL2c
6
4
2
0
-2
-4
0.08
0.1
0.12
time (s)
0.14
nd
0.16
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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48
Ts
2Ts
3Ts
time(s)
4Ts
Magnitude (dB)
150
5Ts
100
50
0
-50
PI control
PI +PR control
-100
-150
0
Phase (deg)
-45
The new Ha, b and cratios shown in Fig. 11e are responsible for
eliminating the 2nd order harmonic current in Fig. 11d. In order
to suppress the input current ripple, the PWM carrier signals
are displaced by 120 as shown in Fig. 12a. In this way, the
converters input currents, shown in Fig.12b, charge and
discharge in different time periods, instead of all being
charged and discharged simultaneously and hence, the high
frequency ripple in total input current Iin is reduced to 0.6%
pp, compared with the symmetric PWM signals shown in Fig.
8e (6% pp). This reduction may alleviate the need for PV
output capacitive filtering. Fig. 13 shows the same operation
when the proposed system is connected to a voltage source of
250V via a 1:5 step-up transformer under unity power factor
operation where Io = 33.33A and =0.
Vq
-270
-2
100
80
60
40
20
0
0.08
(8b)
20
10
-10
0
0.1
0.15
50
Vo (V)
40
b
+
PI
0.05
time (s)
a
+
30
20
10
abc
Vq
0
-10
0
0.05
0.1
0.15
time (s)
PI
Vo
Fig. 9. Control structure with eliminating the 3rd harmonic in the dq frame (2nd
in the stationary)
Vo*
Vd*
Vd
Vq*
Vq
30
(a) Output voltages at Vc2a, Vc2b and Vc2c and corresponding dq components
dqo
0.16
60
Vd
Vq
0.14
40
abc
0.12
dq
0.1
60
50
PR
PI
Vd
10
Vc2a
Vc2b
Vc2b
120
(8a)
PR
10
140
0V
10
Frequency (Hz)
0V
-
10
time (s)
1
s2 a s 1
(2fb )2
-225
as
K rr s
, o 2f
G pr K pr 2
s o2
Vd
-180
Vd and Vq (V)
Gbp
-90
-135
IL2a
IL2b
IL2c
60
40
20
0
-20
-40
0.08
0.1
0.12
time (s)
0.14
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0.16
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/JESTPE.2014.2313185, IEEE Journal of Emerging and Selected Topics in Power Electronics
IL2a
IL2b
IL2c
6
4
2
0
-2
-4
0.08
0.1
0.12
time (s)
0.14
0.16
nd
Ha
Hb
Hc
2.5
Ha,b&c
2
1.5
1
0.5
0
0.08
0.1
0.12
time (s)
0.14
0.16
Carrier
IL1b
IL1c
t
(a) Displaced
signals
PWM
carrier
50.2
Iin (A)
50.1
50
49.9
49.8
0
Ts
2Ts
time (s)
3Ts
4Ts
10V/div 10ms/div
20V/div 5ms/div
(a) Output voltages at Vc2a, Vc2b and Vc2c and corresponding dq components
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10.1109/JESTPE.2014.2313185, IEEE Journal of Emerging and Selected Topics in Power Electronics
20A/div 5ms/div
(b) three-phase output current
20A/div 5ms/div
(b) three-phase output current
20A/div 5ms/div
(c) Cuk input currents IL1a,IL1b and IL1c
1 A/div 5ms/div
(c) 2nd order harmonic components of three-phase
1 A/div 5ms/div
(d) 2nd order harmonic components of three-phase output current
20V/div 5ms/div
Displaced carrier
signals as in Fig.
12a
10V/div 10ms/div
(a) Output voltages at Vc2a, Vc2b and Vc2c and corresponding dq components
10A/div 5ms/div
(e) Total input dc current (Iin)
Fig.16 Proposed system, under PI+PR control in Fig. 9
2168-6777 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/JESTPE.2014.2313185, IEEE Journal of Emerging and Selected Topics in Power Electronics
ACKNOWLEDGEMENT
Voa
This publication was made possible by NPRP grant (NPRP 4250-2-080) from the Qatar National Research Fund (a member
of Qatar Foundation). The statements made herein are solely
the responsibility of the authors.
REFERENCES
IL2a
20V/div 20A/div 5ms/div
[1]
[2]
Voa
[3]
[4]
[5]
IL2a
[6]
[7]
V. CONCLUSION
Due to its inherent current sourcing nature, the Cuk converter
is an attractive choice for dc-ac converters in PV applications.
The proposed single-stage three-phase Cuk-based inverter
introduces several merits when employed for PV applications.
Continuous input current enables direct MPPT techniques and
the ability of paralleling dc-ac converters at the same PCC
promote the proposed converter as viable topology for PV
applications. Importantly, because of low input current ripple,
no capacitor is required across the PV array (and if used to
bypass high frequency switching components, plastic
capacitors can be used instead of low reliability electrolytic
types). Generally, high order converters like Cuk converters
have been avoided in inverter applications because of their
control complexity. Moreover, the Cuk converters inherent
nonlinearity is a reason for output current and voltage
distortion. The effect of this nonlinearity can be relieved by
increasing the Cuk converter inductances and capacitance.
However, this adversely affects the total cost, size and control
complexity. In this paper, a three-phase dc-ac Cuk converter
based current source inverter has been proposed and assessed.
The state space averaging method was used to design the
control structure. An additional control loop reduced distortion
with low passive element values. Satisfactory results in terms
of reduced 2nd order harmonic components in the output
currents and voltages were obtained and verified by
MATLAB/SIMULINK. An inverter system was used to
produce experimental results that confirmed system
performance. Detailed overall control analysis, including
MPPT operation, as well as the effect of grid side imbalance,
common mode voltage, and low order harmonics are to be
considered in future publications.
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
2168-6777 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/JESTPE.2014.2313185, IEEE Journal of Emerging and Selected Topics in Power Electronics
[19]
[20]
[21]
[22]
2168-6777 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.