BCD Adder/Subtracter

Second Revision
EE365
10-19-2004

Chris Ouellette
Joshua Smith

Index
I. Introduction................................................................................................................3
II.
Basic Components..................................................................................................3
A. 1-bit Full Adder / Subtracter (FAS).....................................................................3
B. 4-Bit FAS.................................................................................................................5
C. Add six Technique Design.................................................................................7
D. Look-up table Technique Design....................................................................13
II.
One Digit BCD adder/subtracter.......................................................................14
III.
Two Digit BCD adder/subtracter.......................................................................15
V. Future Improvements to Design.............................................................................19
VI.
Conclusions...........................................................................................................19

Figures
Figure 1 - FAS......................................................................................................................4
Figure 2 - FAS Timing Diagram..........................................................................................4
Figure 3 - 4-bit FAS.............................................................................................................5
Figure 4 - 4-bit FAS Timing Diagram.................................................................................6
Figure 5 - Add six (addition)...............................................................................................9
Figure 6 - Add Six (Add/Subtract).....................................................................................10
Figure 7 - Add/Subtract 6 Timing Diagram.......................................................................11
Figure 8 - Look up table BCD correction..........................................................................13
Figure 9 - 1-digit BCD Adder/Subtracter..........................................................................14
Figure 10 - 1-digit BCD Adder/Subtracter Timing............................................................15
Figure 11 - Two digit BCD adder/subtracter.....................................................................16
Figure 12 - Two digit BCD Timing Diagram....................................................................17
Figure 13 - BCD to 7 Segment Display Decoder..............................................................18
Figure 14 - BCD to 7 Segment Display Timing Diagram.................................................19

Tables
Table 1 - FAS Truth Table....................................................................................................4
Table 2 - Add six carry Truth Table...................................................................................11

All VHDL Code and Testbenches in Attached

I. Introduction
The goal of this project is to design and implement a 2-digit binary coded decimal
(BCD) adder/subtracter using VHDL. The device will consist of two 4-bit
adder/subtracter units, two BCD correction units, two subtraction correction units, and
two BCD to 7 segment display converters. The inputs are expected to be BCDs, with
outputs capable of driving a seven segment display. The unit will be able to correctly add
and subtract any number from 99 to -99, correctly displaying the output (complete with
negative where necessary). Two different methods of correcting for BCD errors will be
developed, one known as add-six and the other a case-select. The components for the
device will be written in different modeling languages and utilize higher level functions
such as for-generate loops as well as different architectures such as a look-up table-based
architecture. Individual components will be introduced below, defined in terms of their
function, summarized in their design, and then tested using a ModelSim testbench. After
the basic components are shown, the higher level entities which these create will also be
tested until the final product is done.

II. Basic Components

A. 1-bit Full Adder / Subtracter (FAS)
The Full Adder / Subtracter unit in this project has 3 input bits, and 2 output bits.
A logic diagram is shown below of the FAS entity and its corresponding truth table
(Figure 1 and Table 1).

sub
Case:
1
2
3
4
5
6
7
8

(c_in)
0
0
0
0
1
1
1
1

a
0
0
1
1
0
0
1
1

b
0
1
0
1
0
1
0
1

c_out
0
0
0
1
1
0
1
1

s
0
1
1
0
0
1
1
0

Table 1 - FAS Truth Table

Figure 1 - FAS

A and B are in input bits to be added or subtracted, SUB is asserted when

subtraction is to be performed, and is not asserted when addition is to be performed.
C_IN is the carry in, used when ripple addition is being performed. The outputs
C_OUT and s represent the carry bit and sum, respectively. As seen in , the SUB and
C_IN have been tied together outside the entity (this is reflected in the truth table). This
was done within the testbench and not in the entity to keep the FAS generic so a multi-bit
FAS could be implemented from a single bit FAS. In the multi-bit case, the C_OUT
becomes the C_IN for the next bit, with the exception of the LSB whose C_IN is tied to
SUB, allowing for the ones complement to be performed.
The timing diagram from a ModelSim testbench is shown below.

Figure 2 - FAS Timing Diagram

This timing diagram has a 1-to-1 correspondence to the truth table for the
intended design in Figure 2. This leads us to believe that the logic function for the 1-bit

FAS is correct and can be instantiated for use in higher level designs. Specifically, the 1bit FAS will be used to create a 4-bit FAS next.
B. 4-Bit FAS
The 4-bit FAS will be needed to add BCD numbers together since a 1 digit BCD
number requires 4 bits, 0000 through 1001 representing 0 through 9 (1010 through 1111
are invalid BCDs, which will be addressed later). A 4-bit adder was constructed using a
for-generate loop in VHDL, instantiating the 1-bit FAS four times and tying C_OUT to
C_IN of the next most significant bit in a ripple carry. The LSB FASs C_IN was, as
noted before, tied to SUB, and the MSB FASs C_OUT was left as an output to the 4-bit
FAS entity. This carry can represent cases of overflow in addition or inappropriate
subtraction (that is in a-b when b>a). This will be addressed later when the add-six
function is discussed.
The 4-bit FAS entity is shown below in Figure 3:

Figure 3 - 4-bit FAS

The C_IN was tied to sub outside the entity again (in the testbench) because
flexibility is needed in the design of this circuit. Ultimately, the 4-bit FAS needs to be
able to accept a carry-out from another 4-bit FAS in the case where two are used in series
to create a 2 digit BCD adder/subtracter. However, for the testing of the 4-bit FAS

design, SUB being tied to c_in (in order to produce 2s complement when SUB=1) is the
appropriate test.
The following cases were tested with expected results:
Case:
1. 0 + 0 = s: 0000, c_out: 0
2. 9 + 1 = s: 1010, c_out: 0
3. 5 + 2 = s: 0111, c_out: 0
4. 0 0 = s: 0000, c_out: 1
5. 9 9 = s: 0000, c_out: 1
6. 4 2 = s: 0010, c_out: 1
7. 2 4 = s: 0010, c_out: 0
Below is a figure of the ModelSim testbench timing diagram for the cases given
above.

Figure 4 - 4-bit FAS Timing Diagram

Note cases 2 and 7. In case 2, the inputs are BCD numbers, but the output is not a
valid BCD number as it issome modification will need to be made to the sum in order
for it to be valid. In case 7, the output is a valid BCD number, but this sum is not
mathematically correct (also note in this case SUB=1 is different than C_OUT=0). This
fact can be used later to force a carry to the next decimal place. That is, if SUB and
C_OUT are different and subtraction is being performed, a carry should be performed.
This will be addressed later.
With the sum and carry outputs expected for addition and subtraction in a few
representative cases matched up, the VHDL representation of the 4-bit FAS is believed to
be accurate. Since the 4-bit FAS is generic, it can be used with standard 4-bit binary

inputs, or special 4-bit inputs such as BCDs. However, as noted, special corrections
will need to be made for addition or subtraction of BCDs that yield invalid BCDs, or an
invalid result. This will be addressed in two different ways: utilizing the add/subtractsix technique, and by a case-lookup technique. These techniques will be outlined in the
following two sections. Further corrections might also be necessary to account for
borrowing when subtraction is being performed.
C. Add six Technique Design
The add six technique is one way that accounts for outputs from the 4-bit FAS
which are not valid BCD numbers or are valid BCD numbers, but not arithmetically
correct. Addition will be considered first, and then subtraction will be considered.
Addition:
The output from the 4-bit FAS will be an invalid BCD number when the sum of
the decimal equivalents of the 4-bit BCD numbers being added is greater than 9 (1001),
and do not result in a carry (in the cases where the sum is greater than 15). For example,
in case 2 in the previous section, the addition of 9 + 1 was performed in the 4-bit FAS.
The FAS has no problem performing this calculation, and returns the correct binary value
1010 (decimal 10). However, since we have constrained ourselves to using BCD
numbers, 1010 is not valid. BCD numbers are 4-bit numbers ranging from 0000 to 1001
allowing for direct coding of a decimal number. 4-bit words above 1001 have no
meaning as a BCD number, as there are only 10 decimal digits (0 though 9). Thus, the
correct BCD equivalent of the given place value must be generated, and a carry
performed.
To do this, we must consider how to detect when an improper BCD output occurs,
how to correct it to a valid BCD, and know when to carry a 1 to the next BCD digit.
By definition, an incorrect BCD output is when the 4-bit output from the FAS has
a decimal equivalent greater than 9. Those digits are: 1010, 1011, 1100, 1101, 1110, 1111.
Noting the pattern of these digits, all have the pattern 1X1X or 11XX, where X can be a 0
or a 1. Also note that no 4-bit BCD less than 9 has this pattern so this can be used as an
invalid BCD detection method (note that this by itself does not account for a sum of two
BCDs that resulted in a carry out of the 4-bit FAS).

The method proposed by other sources has been the add-six method to correct
for an invalid BCD. Essentially, by taking the improper BCD number and adding six, it
will skip the number past the six invalid BCD numbers, and place it in the correct
relative place in the valid BCD range. For example, 1100 is an invalid BCD number,
which should represent 12. This can be represented with two 4-bit BCD numbers as
0001-0010, each 4-bit BCD directly translating to the 10s place decimal number and the
1s place decimal. If 6 is added to 1100 (ignoring the carry for now): 1100 + 0110 = 0010.
As noted though, there is one more case when the six needs to be added. If the
sum of the original 4-bit numbers results in a carry itself, this means a valid BCD number
will result, but it will be mathematically incorrect for example 9 + 9 = 18 = 0001 + 1000
(in BCD), but 1001 + 1001 = 0001 + 0010 (210). The result is a valid BCD number, but
six still needs to be added: 0010 + 0110 = 1000.
With a method of correcting BCDs, we now need to consider when a carry should
be conducted. In the case where it was detected that 6 needs to be added, a carry will
result since the sum will always exceed 1111 (1510). If a two digit BCD adder is in
consideration, this carry will need to be input to the 4-bit FAS of the 10s place. So if the
sum output of the FAS is 1X1X, or 11XX, or the carry out of the 4-bit FAS is 1 a carry
of 1 needs to go to the next highest place (ones to tens place for example). That is:
Consider the logic diagram below representing the add-six correction for
addition of BCD numbers:

Figure 5 - Add six (addition)

The inputs are the 4-bit sum from the FAS, the C_OUT from the FAS (which is
C_IN), and SUB=0 (not shown). The outputs are the corrected 4-bit BCD sum, and the
carry, C_OUT. Notable in this design is the fact that only two 1-bit FAs are needed to add
six to the input sum. Since the LSB of the sum is never changed by adding 6 (0110), it
can be passed through. For the second digit s1, when six needs to be added, Wcondition is
high, passing a 1 to the full adder. s1in is then added to Wcondition (1), with a
C_IN=0, and the result is passed to the next FAS. This result is added with s2in and
Wcondition(1). The carry out of this is then passed to an xor gate. If the carry of the
second FAS is 1, then the XOR acts as an inverter. For example, if s3in is 1, and the
carry from the FAS is 1, then the output bit needs to be 0 (1+1= s: 0, carry: 1 -Note in this case, the carry from s3out has already been taken care of). The opposite is true
if the carry is 0 -- s3in is passed through. Note that is Wcondition is NOT 1 (input is a
valid and correct BCD number) then the FASs are simply adding zero to the input bits,
and the sum passes through. With the design principles for addition worked out,
subtraction will now be considered.

Subtraction:
With an idea for a design that works for addition, adding subtraction requires
reanalyzing the same questions that addition had: how can one tell that the BCD is
inappropriate and must be corrected, and when should the carry from the add six
function be asserted? Instead of describing these questions before presenting the design,
consider the final design proposed below, noting the changes between Figure 5 and it.

Figure 6 - Add Six (Add/Subtract)

The major differences in the design presented in Figure 6 and Figure 5 are
the logic gates used to determine the Wcondition wire, addition of a variable SUB, and
changes in the way that the carryout (cout) is generated. The first difference arises from the
difference between when the carry is asserted in the 4-bit FAS in addition and
subtraction. When the 4-bit FAS is adding (SUB=0), a carryout (cin) of 1 signifies an
overflow which means 1) the carry (out of the add six) must be 1, and 2) the add six
correction must be performed (Wcondition must be asserted). When the 4-bit FAS is
subtracting (SUB=1), a carryout (cin) of 0 signifies that a negative number resulted
which means 1) carry (out of the add six) should be 0, and 2) the subtract six correction
must be performed. The FASs are passed a 1 in the case of subtraction (SUB=1) by the
introduction of an xor gate with cin. If an invalid subtraction was performed, cin = 0,
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making the XOR a buffer. SUB is then passed through to the OR gate and the FASs get
an input value of 1.
Consider the truth table as a summary of the discussion so far:
SUB
0
0
0
0
1
1
1
1

WCONDITION
0
0
1
1
0
0
1
1

C_IN
0
1
0
1
0
1
0
1

C_OUT
0
1
1
X
0
1
0
X

Table 2 - Add six carry Truth Table

th

th

Note the in the 4 and 8 cases c_out is dont care because these cases are impossible. Also note
that in cases 5 and 7 c_out is zero because a borrow has occurred in these cases and not carrying
a 1 is equivalent to borrowing from the next digit.

This truth table can be reduced to a logic function:

C_OUT = C_IN + SUB WCONDITION
This circuit works as a subtract six by adding 2s complement of 6, that is 1010.
In essence, this means inverting s3 to 0 since s3 will always be 1 if the add six
condition is met. However, if a valid subtraction was done, the signal will just be passed
through.
The timing diagram for the circuit is shown below in Figure 7:

Figure 7 - Add/Subtract 6 Timing Diagram

Looking at Case 1 in the timing diagram, we see that this case is a subtraction
case, due to SUB=1, where the sum input to the add six function is 0101. The output sum
remains unchanged in this case for two reasons: first, it is a valid BCD number; secondly,

11

we also know that looking at c_in, which is the c_out of the 4-bit FAS, is equal to SUB
when the subtraction has been correct. Thus, if we know that the add six doesnt need to
do anything to the sum. This case needs to have a C_OUT = 1 because C_IN and SUB
are both 1 and Wcondition 0 (add six did not need to be performed). This matches
with the truth table presented.
The next case shows an invalid BCD number input into the add six. Note that
C_IN does not equal SUB, an indicator for the add six needing to be used. Subtracting six
is like adding the 2s compliment of the binary code for six, 0110, to the input sum. The
2s compliment of 0110 is 1010. Thus, using the first full adder/subtracter to add 1 to the
s1 bit and a set of xor gates to add the second 1 to s4 bit, we have subtracted 6 from the
input sum. This can be seen in detail in Figure 6. Note that the carry out is equal to zero.
This arises from the fact that because an invalid BCD number was input to the add six for
subtraction, we need to borrow from the next most significant bit. This borrowing is
manifested in a carry of zero, instead of 1. We know we need to borrow because it is
impossible to get an invalid BCD number for a-b when a>b. The implications of the
borrow are handled outside of the add six entity.
The third case is much like the first case.
The fourth case shows an addition case where an invalid BCD is presented. Since
the valid BCD being sought is 0001 0010, add six needs to be performed. The C_OUT
is obviously 1 because 12 needs to have a tens digit representation and it matches
the pattern 11XX. In case 5, a valid BCD number is presented, but C_IN is different than
SUB meaning that a carry has already been performed (ie 9+8) so six needs to be added
to the sum, with a carry of one. The last case is similar to the fourth case: an invalid BCD
number, where no carry has been needed yet.
From these cases we can conclude that the add/subtract six logic design is
accurate and appropriate for correcting incorrect BCD outputs from a 4-bit FAS. Note
that this design has an assumption: that there is always a more significant bit from which
it can borrow. This assumption will be assessed an corrected later in the paper.

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D. Look-up table Technique Design

In the last section we designed a correction for invalid BCD numbers after they
had been added/subtracted in a 4-bit FAS. This design was done using dataflow/structural
techniques in ModelSim. In this section we propose a second, equivalent way of
designing a BCD correction using dataflow language in ModelSim.
With this technique, all possible inputs to the correction entity are taken as cases,
and appropriate outputs based on each case is assigned. For example:
when "001010" => s_out <= "0000"; c_out <= '1';
when "001101" => s_out <= "0011"; c_out <= '1';
when "011010" => s_out <= "0000"; c_out <= '1';
when "101111" => s_out <= "1001"; c_out <= '1';
when others => s_out <= "1111"; c_out <= '1';
Each of these lines represents a different set of inputs. For example, the first line
represents a SUB=0, cin = 0, s= 1010. In the last example, SUB=1, cin=0, s= 1111.
Corresponding to each of these inputs are the outputs, s_out and c_out. These are
determined simply by what the output should be in a behavioral sense. For example, in
the first case, the input sum was 10, which should be BCD 0001 0000, so s_out became
0000, and a 1 was carried for the tens place. The timing diagram for the look-up table,
doing the same test as the add-six shown in Figure 7 is below:

Figure 8 - Look up table BCD correction

Since Figure 8 is identical to Figure 7 we are led to believe that the lookup table
architecture and add six are equivalent in the BCD adder/subtracter. This means that the
entity definitions are identical, with the same output for all inputs, and the architectures

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can be use interchangeably. Obviously one would want to use that architecture that had
the best cost/performance ratio.
II. One Digit BCD adder/subtracter
The one digit BCD adder/subtracter will use the previously mentioned components of
The 4-bit FAS and the addsix component (or look-up table component). With these two
components the one digit BCD adder/subtracter will be able to have 2 inputted BCD
numbers (A and B) and add or subtract them computing the sum (S) and allowing for a
carry out bit (c_out). This is shown below in a block diagram:

Figure 9 - 1-digit BCD Adder/Subtracter

Since the 4-bit FAS and add-six entities are already made, the 1-digit BCD
Adder/Subtracter only required a structural instantiation of the two lower-level entities,
and then tying the appropriate ports together.
The expected output of this will be a fully functional 1 digit adder/subtracter. That
is when any two single digits can be added or subtracted giving the appropriate positive
or negative number. A positive or negative requires interpretation, but this will be
addressed when a seven segment display is implemented allowing for the display of a

14

new digit for overflow, or a negative sign. A timing diagram showing a sampling of
outputs is shown below:

Figure 10 - 1-digit BCD Adder/Subtracter Timing

Figure 10 shows in 1-digit input BCDs, as well as the operation, carries, and
output BCD. Note in Case 1, the subtraction of a b, where a > b yields a c_out = 1.
This can be interpreted as a positive number because SUB = C_OUT. In Cases 2 and 3,
the c_out = 0 because a < b, this sum is invalid (obviously 5-9 != 6) but this will be
addressed later in higher level. In addition cases, Cases 4 and 5 result in a carry to the
next decimal place (tens place), while Case 6, does not require a carry so c_out = 0.
This analysis leads us to believe that the 1-digit can correctly add and subtract
BCDs except for the case when a < b. We will now use the 1 digit BCD twice in a
ripple to create a 2 digit BCD adder/subtracter. The impact of the negative numbers
will be addressed in a higher level structural way in the next section.
III. Two Digit BCD adder/subtracter
The two digit BCD adder/subtracter will use the previously mentioned one digit BCD
adder/subtracter to then compute two digit BCD additions and subtractions. The carry
out, c_out, from the adder/subtracter that deals with the ones digit is connected to the
carry in, c_in, of the adder/subtracter that deals with the tens digit. The SUB is tied to
c_in of the ones digit, but SUB and c_in are independent in the tens digit. The output of
the circuit is two 4-bit BCD numbers representing the tens place and ones place, and a
carry out from the tens place BCD adder/subtracter. The block diagram showing this is
below:

15

Figure 11 - Two digit BCD adder/subtracter

Notice the addition of two more 4-bit FASs to the design. These are used to
correct for when negative numbers are incurred in subtraction. In the one digits place the
twos compliment of the ones sum is added to 10 when the right condition is met, which
can be seen from the diagram. When the inverse of the tens carry bit and sub is equal to 1.
Also when that condition is met the 2s compliment of the tens sum from the BCD adder
is taken and added to 9. This is basically hard wiring a borrow from the addition of -100
to the incorrect BCD number from the adder. Once the full adder does the addition the
sums for both tens and ones will be the correct values. There is also a component which
signals whether or not the value is negative, positive or overflow. This is described later
on.

16

The timing diagram for the two digit BCD adder subtracter is shown below for
various inputs:

Figure 12 - Two digit BCD Timing Diagram

The output timing diagram shows accurate addition and subtraction of two digit
BCD numbers. To determine whether the output should be interpreted as negative,
overflow, or neither we need to observe SUB and NORMAL. When NORMAL=1 this
means that, regardless of SUB the output should be interpreted as positive (with no
overflow). If NORMAL=0, the sign of SUB determines negative or overflow. When
SUB=1 this is interpreted as a negative number, and when SUB=0, this is an overflow.
For all of the cases, considering the interpretations of SUB and NORMAL the output is
as mathematically expected. There are a variety of situations presented: case 1 requires a
borrow for the 1s place where a > b; case 2 requires a borrow in the 10s place
(resulting in a negative number), and case 3 shows a regular subtraction requiring no
borrowing. The last case shows the case when there is an overflow (a carry of a 1 to the
hundreds place).
This leads us to believe that the design for the two digit BCD adder/subtracter is
correct and can be used to drive a 7 segment display. The next section briefly details the
construction of a BCD to 7 segment display decoder.
IV. BCD to 7-Segment Display Decoder
Seven segment displays are popular methods for displaying digits 0-9 as an
electronic readout. We have designed a BCD to 7-segment display converter for this
17

purpose. This converter enables the correct segments for a given BCD input. This was
done by doing a 4 variable (for each of the BCD bits, WXYZ) K-map for each of the 7segments of the display. The result of the K-map reduction and associated 7 segment
display is shown in the figure below:

Figure 13 - BCD to 7 Segment Display Decoder

The application of this decoder is when the BCD input for say, a 7 are put on the
decoder (0111), this will be translated into a 7 on the display by A=1, B=1, C=1, F=1.
Note that there is also an extra segment display which allows for the display of a
negative symbol (D=1) and a 1 (C=1 and F=1). The negative symbol is controlled by
the logic function D = NORMAL SUB. The C and F segments are controlled by

18

NORMAL nor SUB. The timing diagram showing the BCD sum/difference inputs, and
the resulting 7-segment display outputs is below:

Figure 14 - BCD to 7 Segment Display Timing Diagram

There are a few things to note in this Figure. Note Case 2 where we perform the
operation 64-72. The sum translates to be negative (note the extra_segment) eight (-08).
Case 4 shows a similar case (33-77) which would be displayed as -44. Lastly, note Case 8
where a 1 is displayed in the extra_segment. The sum 99+87 = 186. From these
observations we can conclude that the BCD adder/subtracter that we set out to develop
works correctly for addition and subtraction of numbers between -99 and 99. The largest
number we can represent is +198 (99+99) and the smallest number -99 (0-99).
V. Future Improvements to Design
This design seems to be fully functional as is. However, efficiency
considerations were not taken into account while working on this final product. For
example, two 4-bit FASs were used to correct for negative numbers, but a much more
efficient way might be possible. While the accuracy of this design is felt to generally be
right, more testing for extraneous results could always be done.
VI. Conclusions
In this project we have developed and tested a two digit BCD adder / subtracter
which can output to a seven segment display. We used various methods of modeling
languages in VHDL including structural and dataflow. A for-generate loop was also used
to create a 4-bit adder / subtracter. Two interchangeable methods were developed for

19

correcting for invalid BCD numbers. By coupling together two one digit BCD adder
subtracters with a correction factor for negative numbers, a fully functional BCD
adder/subtracter was created.

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