A 2.

4GHz CMOS Low Noise Amplifier

using an Inter-sta.ge Matching Inductor
Hong-Sun Kim, Xiaopeng Li, and Mohammed Ismail, Fellow IEEE
Department of Electrical Engineering
The Ohio State University
Columbus, OH 43210 USA
{kimho , lixp, ismail}@ee.eng.Ohio-st at e.edu

Abstract-A 2.4GHz CMOS Low Noise Amplifier(LNA) design is presented in this paper. A conventional cascode LNA structure is used with an interstage matching inductor. The two transistors of the
cascode structure are considered as two individual
stages. The off-chip inter-stage matching inductor is
inserted between two stages. Using this method, overall gain can be increased and the noise figure of the
LNA can be decreased.
Win

I. INTRODUCTION
Fast growth of personal communication market highly
demands t o produce low cost and low power transceivers
for wireless applications [l]. A Low Noise Amplifier(LNA)
is the most critical block to determine sensitivity of a communication system [2]. Conventionally GaAs and Bipolar
technologies are used to implement the LNAs [3][4][5].
Thanks to development of CMOS technology, it is possible to implement GHz RF and microwave circuits with
sub-micron CMOS technologies. The CMOS technology
has a merit to be combined with digital circuitries. Thus,
CMOS LNAs have been extensively investigated in several
papers PI [71PI.
The cascode structure has been widely used for LNA
designs because it is easy to satisfy both noise and power
gain requirements [8]. However, the matching between
the common-source stage and the common gate stage is
often less emphasized in the analysis of the cascode topology. In order to achieve good isolation, the output of the
common-source stage should be considered carefully. This
paper shows the importance of the mathing between two
stages. By inserting an inter-stage matching inductor, the
performance will be improved significantly.
The design procedure of the cascode LNA using an
inter-stage matching inductor will be presented in the first
section. A 2.4GHz LNA is exampled using the presented
procedure in the section 1. Finally the last section summerizes the performance of the LNA and concludes the
paper.

0-7803-5491-5/99/$10.00 0 1999 IEEE

Figure 1. A Simplified LNA structure with an

inter-stage inductor
A simplified LNA structure with an inter-stage inductor is shown in Figure 1. An inter-stage inductor(l,)
is added between the common-source stage and the
common-gate stage. The inter-stage inductor, the output
inductor(l,,t), and the output capacitance(COut)are the
e.xternal components. The input and output impedance
are both %::wed to be 50R.
---

Cout

Win

0-

i
I

zin 1

I--

Zin2
Figure 2. Two-Stage Design Strategy

-4pplying small signal analysis of the common-gate

stage, the LNA can be divided into two stages(Figure
2). Because of high isolation of the common-gate stage
between input and output, the output matching network
can be designed separately. Let us consider the input
matching network of transistor 11.1, first. By neglecting

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Miller effect of gate-drain capacitance(C,dl) of MI the

input impedance of Ml can be given by [a]

where gml and Cgsl

are the transconductance and the
gate- source capacitance of MI respectively. L, and L , are
the gate input inductor and source degeneration inductor.
In order to match the input impedance(R,), the real part
of the equation (1) should be matched to R,, and the
imaginary part of the equation (1) should be cancelled
out. These matching criteria gives

and

the noise performance of the LNA. Since both the input impedance of the common-gate stage and the output impedance of the common-source stage are capacitive, a series off-chip inductor La is included to improve
the matching. Since the gain is improved by adding the
additional inductor, the Miller capacitance effect will be
more significant in the first stage. Again, accurate simulation should be required to adjust the input matching
network of the LNA. Because of good power transfer in
the common gate stage, the overall noise figure will be
decreased.
The final procedure of the LNA design is to determine
the output matching network. The stability and the linearity should be considered carefully at this stage. If the
performance is not satisfactory, we may go back to the
first stage to optimize the LNA performance.

111. A 2.4GHz LNA DESIGN

where WO is the operating frequency.
MOS transistor Noise Figure equation can written by

PI
CbiasL

where y is in the long channel theory. It is known that

the y value is higher than in the sub-micron technology [9]. Under the condition that the drain current is
constant, we can write the transconductance of the transistor Ml(gml) to be J ~ I D , L L C ~ ~ W ~
The
/ L Cssl
~ . can
be also written by $ W1LICoz. When we differentiate the
equation (4) in terms of W 1 , we can find out the optimum size of the transistor MI to generate minimum noise
figure, which is given by

']

La

&
1
W1,min = 2 WoRsLiCoz'

The obtained value from the above equation does not

match the designed size of the transistor because the parasitic gate resistance R, and the parasitic overlap capacitances are neglected. However, the obtained value from
the equation ( 5 ) can be used as an initial value for the
size of the MI transistor. Accurate simulation is required
to obtain good noise figure, isolation, and stability factor
simultaneously.
The second step is to design the common-gate stage.
The common-gate input impedance can be given by
Zin2

1
gm2

+ jw0cgs2 '

Figure 3. 2.4GHz LNA with Bias Circuitry

(5)

(6)

In the traditional cascode LNA design no matching has

been considered between the common-source stage and
the common-gate stage. This is not desirable for the
maximum power transfer. Loss of power directly affects

Figure 3 shows the complete 2.4GHz LNA using the

inter-stage matching inductor. Rbl, RbZ, M3, and M4
provide the biasing of the LNA. The resistor Rbl sets the
current of the bias circuitry, which generates the bias voltage at the gate of the transistor M I . The resistor Rb2
prevents the input signal from flowing into the bias circuitry. The capacitance Cbias provides the AC ground at
should
the gate of the transistor M2. The value. of
be large enough so that the capacitance does not affect
the LNA performance too much. Lout and Gout form the
output matching network.
L, and L, are implemented by combination of on-chip
spiral inductors and bond-wire inductors. Because L, and
L , are realized by on-chip spiral inductors, the parasitic
resistance will affect the noise performance significantly.
The value of L, is chosen about 2 n H , which can be easily implemented by a high Q bond wire inductor combining with an on-chip spiral inductor. According to the

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"
:
i
J
'
I

equation (3), the M I transistor size(W1) is chosen 600pm.

We can obtain the optimized load impedance of the first
stage(&).
From the obtained the value of Z,,,2, we
can determine the size of the transistor Mz(Wz), which
is 500pm.

20

'

............

.x .

'

x.

....

. . . . . .
x

% j l

..

....

..j .

; : i

. . .

.:.

*IP

..............

.I

La is implemented by an off-chip inductor which gives

us several advantages. First we can avoid large parasitic
capacitance. Second, it is good for noise performance.
Using the theory of Miller capacitance, La can introduce
a negative resistance at the input port, which can improve
the noise performance. Third, we can have some flexibility
which enables us to tune the circuit after fabrication.
Figure 4 shows simulation results of 5'11, the power gain,
and the noise figure versus frequency by sweeping the values of La. For the range of 0 5 n H La,the power gain
is improved by 4dB, and noise figure is decreased from
3.4dB to 2.5dB. When we increase La, we notice that the
input reflection coefficient becomes worse. This is because
the negative resistance by the Miller capacitance of Cgdi
partially decreases the input resistance. Considering all
the three parameters together, 5nH would be the best
choice for the La.

0 0

0 0 0 9 0 0

~..

L,S.OnH
L,=7.5nH
L,=lOnH

. . . . . .

+ + + + + +

. . . . . . . . . . . .

IV. CONCLUSION

+ + - + + + + +

26

The procedure of R F Low Noise Amplifier is presented

in this paper. As an example, a 2.4GHz Low Noise Amplier is designed and simulated. The result of the LNA
is summerized in the table 1. The inter-stage matching
inductor is added to the basic cascode LNA structure. Using the inter-stage off-chip inductor, we can achieve high
gain as well as good noise figure.

24

241

242

244

243

245

246

247

248

Frequency (GHz)

Figure 4. 2.4GHz LNA Results

(a) Sll vs. Frequency, (b) Power Gain vs. Frequency,
(c) Noise Figure vs. Freqilency

5
5
1
Table 1. 2.4 G-Hz LNA Simulation Results Summary
1 0.5um CMOS 1
1-Process
Supply Voltage I
3v
Freqiiency Range I 2.4 - 2.48GHz

-10 .................
+ + +

....t...'.

+.>..?..?...+

..+

.*...,

.c .

*...+,. . + . . + ..+..

1
2.4

2.41

2.42

2.43

2.44

Requency(GHI)

2.45

L:=ZSnHi
L,S.OnH
L,=7.5nH
L,=lOnH

4 1

Nciise Figure

-10dB
2.4dB

ACKNOWLEDGMENT

2.48

2.47

2.48

The authors acknowledge Texas Instruments Inc., Dallas, T X for supporting this work, and also thank Prof.
Filanovsky for h.is valuable suggestions.

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