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You are on page 1of 31

Feedback Flip-Flop

S. H. Rasouli, A. Amirabadi, A. S. Seyedi and

A. Afzali-Kusha

Low-power High-Performance Nanosystems Lab., Elec.

and Comp. Eng. Dept., University of Tehran, Tehran,

Iran

a.seyedi@ece.ut.ac.ir, hrasouli@ece.ut.ac.ir,

a.amirabadi@ece.ut.ac.ir ,afzali@ut.ac.ir

Outlines:

Introduction

Flip Flop Structures

Single-edge Triggered Flip-Flops

Double-edge Triggered Flip-Flops

Subthreshold current

Simulation Results

Summary and Conclusion

Introduction

Introduction

important parameter in modern VLSI circuits especially for

low power applications.

One of these techniques is to use low power logic styles

which should be used in design of latches and flip-flops.

Tclk-q (delay from clk to output of FF) and Cclk (the load

capacitance of the clock).

In addition to the dynamic power consumption, the high

leakage current in deep sub-micron regimes is a significant

contributor to the power dissipation of CMOS circuits as the

CMOS technology scales down.

Introduction

improving the speed and/or reducing the power

consumption.

Hybrid Latch Flip-Flop (HLFF).

Semi-Dynamic Flip-Flop (SDFF).

Conditional Capture Flip flop (CCFF).

Introduction

on the frequency, the voltage swing, and the load of clock

tree.

If the sampling of the input is performed in both rising and

falling edge of clock (double-edge triggered), then for same

applications and operational speeds, the frequency of the

clock can be half of the clock frequency of the single edge

triggered FF.

Low-Swing clock Double-edge triggered Flip-Flop (LSDFF).

Double-edge triggered Feedback Flip-Flop (DFFF) has less

dynamic power consumption, static power, and delay

compared to the previous flip-flops.

6

Flip-Flop Structures

It is based on generating an

explicit transparency window for

the time that the transition is

allowed.

In each clock cycle, when the

input is high, regardless of

previous state of the output a

glitch is generated.

The transistors in the stack

degrade the performance of the

logic.

Figure 1.Circuit diagram of HLFF.

These disadvantages make

HLFF not suitable for low power

applications.

8

HLFF due to its lower

number of transistors in the

stack.

The total number of

transistors is greater than

HLFF.

Similar to HLFF unnecessary

internal node transitions

Figure 2. Circuit diagram of SDFF.

exist in SDFF.

10

rising and falling edges of the clock.

To reduce the power consumption of the clock tree, a low

swing clock is used in this logic.

clock tree, a low swing clock is used in this logic. To have a

proper functioning, some of high-Vth transistors are

replaced with low-Vth transistors whose subthreshold

currents are controlled by high-Vth transistors.

For the same throughput, the frequency of the clock in

LSDFF could be half of the frequency of the clock in HLFF

or SDFF.

11

power consumption of LSDFF clock tree could be lower than

those of others.

Uncontrolled subthreshold current low-Vth transistors in the

clock tree leads to a more power consumption.

Since the charging (discharging) the internal node X2 (X1) is

done through three transistors, the speed of the circuit is

reduced.

12

(a)

(b)

13

The node transitions occur only when the inputs are different

in two successive clocks.

When the clock (CLK) makes a transition from low to high,

CLKBD remains high for a period equal to the delay of the

three inverters creating a transparency window. In this

period, C1 is high turning on MN1 and MN3. In this window,

if D is low and Q is high (D was high in the previous clock),

MP2 becomes turning on MN2 which forces the output to

low. If both D and Q are low, MP1 and MN2 are on before

the beginning of the transparency window making the delay

zero (similar to previous flip-flops). If D is high and Q is low,

node X becomes low turning on MP3 which forces the

output to high.

14

output change is alleviated.

If D is high and Q is high, node X will not change and,

therefore, redundant transitions are avoided.

There is no delay whenever D is high in two successive

clock cycles.

The charging of the node X is done through two paths. This

increases the speed of the FF compared to the previous

ones.

15

or MN2) that again leads to the reduction of the DFFF delay.

Choosing MP1 as a small pull-up device, a weak fighting

might exist during an input state change in two successive

clock cycles.

16

at the falling edge of the

clock is similar to its

operation at the rising edge

except that and MN2 and

MN4 play the role of MN1

and MN3, respectively.

C1 and C2 in DFFF.

17

Figure 6. the waveform of (a) the controlling signal (i.e. C1 and C2)

(b) The output of DFFF.

18

Subthreshold Current

the source and drain in an MOS transistor occurs when the

gate voltage is below Vth.

I ds = 0 C ox

(1 exp[

(V g V th )

W

2

( m 1)( v T ) exp[

]

L

mv T

V DS

])

vT

(1)

where

m = 1+

3 t ox

W dm

19

Subthreshold Current

voltage equal to Vdd is

applied across the first

branch in the pull down

network (consisting of

MN1, MN3 and MN5).

When the node X is low

then Q (output) will be high

and output pull down tree

sustains a voltage equal to

Vdd. This high VDS voltage

drop causes large leakage (again) Figure 1.Circuit diagram of HLFF

currents and hence high

leakage powers.

20

Subthreshold Current

in the case of SDFF where

this voltage exists across

two transistors compared to

the case of HLFF where

three transistors exist in the

output pull down network.

(again) Figure 2. Circuit diagram of SDFF

21

Subthreshold Current

22

Subthreshold Current

node X2 as well as VDS of MN1 is equal to Vdd. In the case

that D is high, the VDS of MN2 will be equal to Vdd and,

hence, only one transistor has a high VDS drop.

The leakage current will be higher than the previous flipflops.

23

Subthreshold Current

(a)

(b)

24

Subthreshold Current

The VDS of each transistor in the pulldown network will be

zero.

hence, both the drain and the source of MN1 and MN2 have

high logic values leading to an approximately zero VDS for

these transistors. When D as well as Q is high, the voltage

drop across the output pull-down tree will be approximately

zero too.

Compared to other flip flops, subthreshold current in DFFF

is very low. These very low VDS minimize the subthreshold

leakage current of the flip flop.

25

Simulation Results

CMOS process.

Vdd = 0.7V and the clock frequencies were 100MHz and 50

MHz for single-edge and double-edge triggered FFs. The

load capacitance=10 fF.

26

Simulation Results

No. of

Tr.

No. of

Clked

Tr.

Clk-Q

(ps)

Power

(uW)

P.D

(fj)

improvement

SDFF

23

124

1.9

.236

83%

HLFF

20

132

1.87

.247

84%

LSDFF

28

94

1.4

0.132

70%

DFFF

21

53

0.76

0.041

27

Simulation Results

Leakage

Power (nW)

SDFF

HLFF

LSDFF

DFFF

86

49

82

27

28

a better performance compared to previous logic.

Unnecessary internal node transitions were avoided in this

logic.

This logic may work with a lower clock frequency.

These two reduced the power consumption of the flip-flop

compared to other flip-flops.

Reducing the number of transistors in the stack for both the

internal and the output nodes and increasing the number of

charging and discharging paths decreased the delay of the

logic.

29

performance of DFFF is approximately between 70% and

84% compared to previous works.

30

Thank You!

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