A Hybrid Multilevel Inverter with Both Staircase and PWM Switching Schemes

Hossein Sepahvand

Mostafa Khazraei

Student Member, IEEE

Student Member, IEEE

Mehdi Ferdowsi

Keith Corzine

Member, IEEE

Senior Member, IEEE

Missouri University of Science and Technology

Rolla, MO 65409 USA
AbstractIn this paper, a new method to control multilevel
converters is proposed. The considered multilevel converter
consists of a three-phase three-level diode-clamped converter
(main converter). Two H-bridge cells are then connected in
series with each output phase of the main converter. The
operation of the main converter and one of the cascading Hbridge cells is based on the staircase switching method. The
firing angles of these converters are selected in a way that the dc
voltage required for the last H-bridge cell is minimized. The
switching pattern of the second H-bridge cell is based on the
pulse-width modulation method. This last cell generates the
remaining parts of the desired sinusoidal output voltage. The
combination of these converters and their switching methods
result in an output waveform with low harmonics. Here, a
fifteen-level converter is designed based on this approach.
Simulation results and laboratory measurements verify the
effectiveness of the proposed topology and modulation method.
Index TermsFundamental switching; H-bridge
Inverter; Multilevel inverter; Pulse width modulation

cell;

I. INTRODUCTION
Multilevel power electronic converters are mainly utilized
to synthesize a desired single- or three-phase voltage
waveform. The desired output voltage is obtained by
combining several individual dc voltage sources [1]. In
general, by increasing the number of levels, the synthesized
voltage waveform becomes closer to its sinusoidal reference.
The main advantages of such converters are the low harmonic
distortion of the generated output voltage, low
electromagnetic emissions, high efficiency, the capability to
operate at higher voltage ranges, and modularity [1-7].
Furthermore, due to high VA (volt-amp) ratings of multilevel
converters, they are one of the best choices for electric motor
drives in hybrid power-trains [2, 3, 8, 9].
In general, multilevel converters are categorized into
diode-clamped, flying capacitor, and cascaded H-bridge
topologies [1, 3-5]. The cascaded H-bridge multilevel
converter consists of two or more H-bridge cells connected in
series [1, 6]. These types of converters are widely accepted in

978-1-4244-5287-3/10/$26.00 2010 IEEE

industry as they can achieve higher output voltages with lowvoltage power switches [10, 11]. The cascaded H-bridge
multilevel converter has been applied to high-power and
high-quality applications including static VAR generation
(SVG) [7, 12], active filters, reactive power compensators
[13], photovoltaic power conversion [7, 14], and
uninterruptable power supplies (UPS).
In this paper, a fifteen-level converter, consisting of a
three-phase three-level diode-clamped inverter and two series
H-bridge cells on each phase is studied. First, a three-phase
three-level diode-clamped inverter is used as the main
inverter. Then, each phase of the main inverter is cascaded
with two H-bridge cells. The main inverter and the first Hbridge cell generate a staircase waveform. Their switching
angles are selected in a way to minimize the voltage level of
the dc source which is required to feed the second H-bridge
cell. The second H-bridge cell which operates based on the
pulse-width modulation (PWM) method generates the
difference between the reference signal and what the main
and first H-bridge converters generate. Minimizing the dc
source required for the second H-bridge cell is accomplished
by reducing the peaks of the remaining parts of the desired
sinusoidal waveform. Simulation results and laboratory
measurements verify the effectiveness of the proposed
topology and modulation method.
II. TOPOLOGY AND SIMULATION OF THE FIFTEEN-LEVEL
CONVERTER
The inverter topology which is used in this paper consists
of two cascaded H-bridge cells per phase and a three-phase
diode-clamped inverter. The topology of the fifteen-level
inverter is shown in Fig. 1. For the sake of simplicity, the Hbridge cells of only one of the phases of the converter are
depicted here. In this topology, the main converter is a diodeclamped three phase inverter fed with a dc voltage source of
8 . Each phase of the main converter is connected in series
with two H-bridge converters to form the final voltage of

4364

7Vdc

H-bridge2

Vdc

6Vdc

V3a

5Vdc
4Vdc
3Vdc
2Vdc
Vdc

H-bridge1

2Vdc

V2a

-Vdc

Va

-2Vdc
-3Vdc
-4Vdc
-5Vdc
-6Vdc
-7Vdc

Fig. 2. Staircase output voltage waveform made by the combination of

the main converter and H-bridge1 along with the desired sinusoidal
waveform

3 Phase
Main Inverter
a

8Vdc
n

1a

H-bridge2 is the subtraction of the staircase waveform from

the desired sinusoidal waveform.
The reference of H-bridge2 can be defined as

Fig. 1. Topology of the conveter

each phase of the multi-level converter. The voltage source

feeding the second H-bridge is chosen to be one fourth (i.e.
2 ) of the voltage source of the main converter. Based on
the firing method proposed in this paper, the dc voltage of the
second H-bridge cell can be as low as half of what feeds the
). The main converter and the first
first H-bridge cell (i.e.
H-bridge cell (H-bridge1) on each phase operate under the
staircase waveform generation mode. However the second Hbridge (H-bridge2) of each phase operates in PWM based
method of switching. The switching angles of the main and
the first H- bridge cell are selected in a way to minimize the
voltage of the dc source of the last H-bridge (H-bridge2). The
sum of the output waveforms of the main inverter and H) for phase a along with the desired
bridge1 (
sinusoidal waveform (reference) are shown in Fig. 2.

(1)

where m denotes the modulation index (with a range of 0 to

1),
is the maximum possible peak output voltage of the
is the output voltage of the main converter, and
converter,
is the output voltage of H-bridge1. In order to generate a
smooth waveform, H-bridge2 should cover half of the voltage
jump changing the state of switches of the main converter and
equals
. For
H-bridge1 at the instance when
this task, a simple method is used by defining a variable as

.
2

0.5

(2)

where floor is a common function that rounds to the nearest

integer toward minus infinity. By this definition
can be described as

.2
A. Selecting dc Voltage Sources for the Converters and
Switching Fundamentals of H-bridge2
By selecting the dc voltage source feeding H-bridge1 (see
Fig. 1) to be one fourth of the dc voltage source feeding the
three-phase converter, the maximum output voltage of Hbridge1 will be half of the maximum output voltage of the
main converter with respect to the neutral point (between the
two capacitors). If a staircase switching method is used for
the three-phase inverter and H-bridge1, using these two
converters, it is possible to synthesize a seven-level
waveform similar to the waveform which is shown in Fig. 2.
Since the ultimate goal is to generate a sinusoidal waveform,
the second H-bridge (H- bridge2) can be switched based on a
PWM method to make the remaining parts of the desired
sinusoidal waveform. In other words, the PWM reference for

sin

.2

(3)

where
is the status of the main converter and
is the
status of H-bridge1. Also, ,
{1, 0, 1}. For example,
is -1 the output voltage of the main converter is
when
and when
is 1 the output voltage of H-bridge2 is
4
2 . Table I shows all possible combinations of
and
for each State. When the state is 1 or -1, there are two
possible combinations. In the simulation and experimental
section of this paper, the combinations with asterisk signs are
used. Based on the topology and voltage ratios of the
cascaded converters, the maximum voltage that can be
7 .
generated by this converter is 7 ; therefore,
B. Simulation Results
The converter is modeled and simulated in
MATLAB/Simulink to verify the operation of the proposed

4365

(a)
V 1 a (V)

72
0
-72
0.01

0.02

0.03

0.02

0.03

0.02

0.03

0.02

0.03

0.02

0.03

0.02

0.03

(b)
V 2 a (V)

36
0
-36
0.01

V 1 a +V 2 a (V)

(c)
72
0
-72

PWM Ref (V)

0.01
(d)
18
0
-18
0.01

V 3 a (V)

(e)
18
0
-18
0.01

V a (V)

(f)
126
72
0
-72
-126
0.01
time (s)

Fig. 3. (a) Main converter output, (b) H-bridge1 output, (c) desired sinusoidal waveform and sum of the main and H-bridge1 converters, (d) PWM reference
of H-bridge2, (e) H-bridge2 output, and (f) total output waveform of phase
TABLE I
ALL COMBINATIONS OF S1 AND S2 FOR EACH STATE

method. Fig. 3 shows the output waveforms of all inverters

for
= 18V and m =0.9. In Figs. 3(a) and (b) the output
waveform of the main and H-bridge1 converters are shown,
respectively. The desired sinusoidal waveform and sum of the
voltages generated by the main and H-bridge1 converters
) are shown in Fig. 3(c). Note that the sinusoidal
(
reference waveform crosses the middle of the jumps in the
staircase waveform. The difference between the desired
) is shown in Fig. 3(d). As it
output waveform and (
is shown, the maximum value of the PWM reference is 18 V
. In Figs. 3(e) and (f), the output of H-bridge2
which is
and the total output of the converter are shown, respectively.

III. EXPERIMENTAL RESULTS

In order to verify the simulation results, a hardware
prototype of the system is developed. The voltage source of
the main converter is 144 V. Accordingly, 36 V and 18 V
voltage sources are used for H-bridge1 and H-bridge2,
respectively. The control scheme is implemented in a
TMS320F2812 digital signal processor (DSP) which is
connected to the IGBTs using fiber optic cables. The

State
3
2
1
0
-1
-2
-3

S1 (Main)
weight:2
1
1
0
1*
0
0
-1*
-1
-1

S2 (H-bridge1)
weight:1
1
0
1
-1*
0
-1
1*
0
-1

switching frequency for H-bridge2 is 6 kHz. Experimental

result for the converter when m is equal to 0.9 is shown in
Fig. 4. Fig. 4(a) shows the output of phase a of the converter
( ). Fig. 4(b) shows the output waveform of the main
converter with respect to the neutral point ( ). Figs. 4(c)
and (d) illustrate the output waveform of H-bridge1 ( ) and
H-bridge2 ( ), respectively. Fig. 5 shows the converters
output voltage when m is equal to 0.75.

4366

(a)
120
60
0
-60
-120

V a (V)

V a (V)

(a)
120
60
0
-60
-120
0.01

0.02

0.03

0.01

80
40
0
-40
-80

0.01

0.02

0.03

80
40
0
-40
-80

0.01

40
0
-40
0.02

0.01

0.03

0.02

0.03

0.02

0.02

0.03

0
-40
0.01

0
-30

0.02

40

0.03

(d)
V 3 a (V)

V 3 a (V)

0.01

0.03

(c)
V 2 a (V)

V 2 a (V)

(c)

30

0.02
(b)

V 1 a (V)

V 1 a (V)

(b)

0.03

time (s)

(d)

30
0
-30

0.01
time (s)

Fig. 4. Experimental results for m=0.9 (a) total output waveform of multilevel converter, (b) output waveform of the main converter, (c) output
waveform of H-bridge1, and (d) output waveform of H-bridge2

Fig. 5. Experimental results for m=0.75 (a) total output waveform of

multi-level converter, (b) output waveform of the main converter, (c)
output waveform of H-bridge1, and (d) output waveform of H-bridge2

IV. CONCLUSION
In this paper, a new method to implement and control
multilevel converters is proposed. In the proposed topology,
two H-bridge cells are connected in series with each phase of
a three-phase three-level diode-clamped converter. The
operation of the main converter and one of H-bridge cells is
based on the staircase switching method. Switching angles of
the staircase output voltage are chosen in a way to minimize
the level of the dc voltage source needed for the last Hbridge. The second H-bridge cell generates the remaining
parts of the desired sinusoidal waveform. The combination of
these converters and their switching methods results in a
fifteen-level output voltage waveform with low harmonics.
Simulation and laboratory results show the proper operation
of proposed method.

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