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Lecture 17
MSE 515
Topics
MOS Structure
MOS IV Characteristics
CCD
1 Billion
Transistors
100,000
Pentium 4
Pentium III
Pentium II
10,000
1,000
100
10
Pentium
i486
i386
80286
8086
1
75 80 85 90 95 00 05 10 15
Source: Intel
NMOS Structure
Substrate contact--to
reverse bias the pn junction
Connect to most negative supply voltage
in most circuits.
Short-Channel MOSFETs
Subthreshold Characteristics
Although no current should ideally conduct before threshold, a small
percentage of electrons with energy greater than or equal to a few kT have
sufficient energy to surmount the potential barriers!
As a result, there is a slight amount of current conduction below VT
Short-Channel MOSFETs
Potential contours in a long channel MOSFET.
Short-Channel MOSFETs
Narrow Width Effect
If the Polysilicon gate is atop the region of a LOCOS isolation where the oxide is
increasing in thickness.
It is possible to form a channel under LOCOS away from the thin gate oxide!
This is quite important for devices with L < 1 mm.
CMOS Structure
Connect to most positive
supply voltage in most circuits.
Reverse bias the pn
junction
NMOS
PMOS
MOS IV Characteristics
Threshold Voltage
Derivation of I/V Characteristics
I-V curve
Transconductance
Resistance in the linear region
Threshold Voltage
Implantation of p+ dopants to
alter the threshold
I-V Characteristics
Channel Charge
Application of VDS
Pinch Off
Linear
Region
Small VDS
Saturation
Region
Large VDS
No channel
I-V characteristics
Transconductance
Output resistance
Body transconductance
Transconductance
Analog applications:
How does Ids respond to changes in VGS?
IDS vs VGS
0.13 um NMOS
VDS=0.6 V
W/L=12um/0.12 um
VB=VS=0
Y axis: Ids
X axis: Vgs
Different Expressions of
Transconductance
L is really L1
MOS Capacitances
Detector zoology
X-ray
Visible
NIR
MIR
l [mm]
0.1
0.3
0.9
1.1
2.5
20
Si:As
Silicon CCD
Similar physics for IR
materials
CCD Introduction
A CCD is a two-dimensional array of metal-oxidesemiconductor (MOS) capacitors.
The charges are stored in the depletion region of
the MOS capacitors.
Charges are moved in the CCD circuit by
manipulating the voltages on the gates of the
capacitors so as to allow the charge to spill from
one capacitor to the next (thus the name
charge-coupled device).
An amplifier provides an output voltage that can
be processed.
The CCD is a serial device where charge packets
are read one at a time.
33
34
35
+5V
0V
-5V
+5V
0V
-5V
+5V
0V
-5V
36
37
good CTE
bad CTE
38
39
Threshold Voltage
VG=0.6 V
VD=1.2 V
CMOS: 0.13 um
W/L=12um/0.12 um
NFET
constant
gm as function of region
0.13 um NMOS
VGS=0.6 V
W/L=12um/0.12 um
VB=VS=0
Y axis: gm
X axis: vds
saturation
linear
gds
0.13 um NMOS
VGS=0.6 V
W/L=12um/0.12 um
VB=VS=0
Y axis: gm
X axis: vds
Slope due to
channel length
modulation
saturation
linear
Body Effect
W/L=12 um/0.12um
CMOS: 0.13 um process
VDS=50 mV
Simulator: 433 mV
Alternative method: 376 mV
Subthreshold current
Subtreshold
region
As VG increases, the surface
potential will increase.
There is very little majority carriers
underneath the gate.
There are two pn junctions. (B-S and B-D)
The density of the minority carrier
depends on the difference in the
voltage across the two pn junction diode.
A diffusion current will result the electron densities
at D and S are not identical.
Conceptual Visualization of
Saturation and Triode(Linear)
Region
NMOS
PMOS
VSB dependent
(VTH0: with out body effect)
(chain rule)
(Triode region)