High Density 3-D Integration Technology for Massively Parallel Signal Processing in

Advanced Infrared Focal Plane Array Sensors

D. Temple1, C. A. Bower1, D. Malta1, J. E. Robinson2, P. R. Coffman2, M. R. Skokan2 and T. B. Welch2
1
RTI International, Research Triangle Park, NC
2
DRS Infrared Technologies, Dallas, TX
Abstract
The paper describes a platform technology for threedimensional (3-D) integration of multiple layers of silicon
integrated circuits. The technology promises to dramatically
enhance on-chip signal processing capabilities of a variety of
sensor and actuator devices hybridized with Si electronics.
Among these applications are high performance infrared
focal plane array detectors.
Introduction
Three-dimensional (3-D) integration technology is expected
to dramatically enhance signal processing capabilities of
high-resolution infrared focal plane array (FPA) sensors.1
Figure 1 illustrates the conceptual transition from the state-ofthe-art 3-D detector (or actuator) architecture, limited to two
device layers and interconnected either by metal bumps (A)
or vertical interconnects through the detector layer (B), to the
structure consisting of multiple layers of Si ICs, which
represents true 3-D integration (C).
When the integration is limited to two layers, the detector and
one readout IC (ROIC), any signal processing circuitry needs
to fit within the confines of the pixel. The true 3-D

integration revolutionizes the device architecture by allowing

additional layers of silicon ICs to be incorporated (with
optimal short interconnect paths and enormous inter-layer
signal bandwidth), removing the IC real-estate limit and
greatly enhancing functionality of the detector array. Further,
different functions of the Si circuitry can be assigned to
different layers, e.g. an analog amplifier IC can be separated
from an analog-to-digital converter and from a digital
processor. As these different ICs are based on different
processes with different design rules, it is advantageous not to
have to produce them in a monolithic form, but rather as
separate components. Fabrication processes can then be
optimized for the specific functionalities, resulting in
increased yield and reduced cost.
The high density 3-D integration technology described in this
paper uses back-end, circuits-first methodology, and is
compatible with standard bulk silicon IC wafers, such as
those produced by a standard CMOS foundry. All processes
employed in the stacking of the Si IC layers and the
fabrication of vertical interconnects are conducted at low
temperature (<200C). The bonding of individual device
layers is done in either die-to-die or die-to-wafer
configuration, which allows only known-good-die to be
processed. This approach avoids the compound yield loss

Detector Array
ROIC

A
Microbumps

3-D Interconnects

Stacked
ROIC

Figure 1. Performance of state-of-the-art detector arrays hybridized to Si ROICs (A, B) can be dramatically improved by

the integration of multiple Si IC layers (C). The hybridization of the detector layer to the stacked ROIC can be
performed using interconnects through the detector layer (as shown in C) or microbumps.

1-4244-0439-8/06/$20.00 2006 IEEE

inherent in wafer-to-wafer stacking and allows for different

die sizes in the stack. Since each die is aligned in a separate
bonding event, the alignment accuracy is improved over
standard wafer-to-wafer alignment. The technology leads to
the formation of 3-D interconnects with high aspect ratios, a
key feature for compatibility with bulk Si IC wafers.
3-D Integration Process Flow
Figure 2 shows a diagram of the process flow for the
fabrication of the 3-D ROIC for the integrated FPA devices.
The process starts with fabricated IC wafers and is not
foundry-specific. A redistribution metal layer (RDL) is
deposited and patterned, and alignment marks are etched into
the IC2 wafer to facilitate the subsequent aligned bonding
step. The wafer is then mounted on a carrier wafer "face
down," and is thinned by grinding and chemical mechanical
polishing (CMP). While still mounted on the carrier, the IC2
wafer is diced, and the individual die are bonded to the IC1
wafer or die. A lithography sequence is performed to define
an etch mask for 3-D interconnects. This is followed by

Bulk CMOS
Wafers from
Foundry

IC3
IC2

Alignment
Mark RIE

Si IC 2

IC2

etching of high aspect ratio vias in the Si IC2 layer,

deposition of conformal insulator to prevent cross-talk
between the pixels, selective removal of the insulator in the
bottom portion of the via to open the contact to the landing
pad of the RDL, and deposition of metal into the 3-D
interconnect. The left hand side inset of Figure 2 shows a
two-plane cross-sectional scanning electron microscope
(SEM) photograph of the vertically integrated two-layer Si IC
stack. 3-D interconnects in this IC2 are 4 m in diameter and
are about 30 m long. The two IC layers are bonded using a
polymer adhesive. The alignment accuracy of about 2 m
was obtained for the aligned bonding. If additional layers are
required, the process of forming vertical interconnects is
repeated, as illustrated in Figure 2. The right hand side inset
shows a cross-section SEM micrograph of a three layer
passive Si stack with vertical interconnects spanning the top
two layers.
The hybridization of the infrared focal plane array detector
layer, used for the proof-of-concept of 3D integration
technology, begins with the patterning and passivation of the
top metal to form the landing RDL for vias subsequently

Thinning

Carrier
CarrierSubstrate
Substrate

singulate

IC3
IC2
IC2

Alignment
Mark RIE

IC2

Thinning

IC2
Si IC 2

IC1
IC1
IC2

Redistribution
Layer

Carrier
CarrierSubstrate
Substrate

singulate

Aligned Bonding of Thinned

Si IC2 & Carrier Removal

Si IC 1

Si IC 1

Vertical
Interconnects
& Top Pattern

Si IC 1
VISA D2W 3L Lot 1, Wafer 4, Die 11

Si #3

Vertical
Interconnects
& Top Pattern

Si #2

Si IC 1

Si #1

Figure 2. Process flow for the fabrication of integrated two-layer and three-layer readout ICs. The left-hand-side
SEM micrograph inset shows two layer Si IC stack with alignment accuracy of approximately 2 m. The right handside inset shows a three-layer vertically interconnected passive Si stack.

etched in the FPA layer. The FPA hybridization process

involves bonding and carrier removal of a thin layer of
HgCdTe of sub-10 m thickness followed by etching of vias
down to the underlying RDL. As a natural consequence of
the via etching process, a portion of the p-type HgCdTe
surrounding the via is converted into n-type
HgCdTe, resulting in the formation of a p-n junction
photodiode. Metal is deposited into the vias, making
electrical contact between the n-side of the diode and the
pixel input pad of the ROIC.2 The FPA hybridization
technique has been validated extensively and was shown to
withstand repeated thermal cycling (>2000 cycles) between
the room temperature and the operational temperature of
Figure 3 shows a two-plane cross-section SEM
77K.3
photograph of a 256x256 medium wave infrared (MWIR)
photodiode array hybridized with a two-layer Si IC stack
fabricated using the described 3-D integration technology.
The HgCdTe layer is 7 m thick, the FPA pixel size is 30
m.

sensitivity requirement of 3.5x1011 photons/cm2/s (the lower

the NE the higher the sensitivity). The results are at the
high performance levels seen in baseline MWIR FPAs
operating with the same readout IC. The distribution is
approximately Gaussian without a long tail indicating no
significant excess noise mechanisms are present. The NE
operability is 97.5% and limited in this FPA by open pixel
contacts at the detector and not attributable to the 3-D
integration process. Quality of the thermal image, shown in
Figure 4b, is excellent, with no defect clusters or pixel crosstalk.
This FPA test vehicle demonstrates that 3-D
interconnects fabricated using the described 3-D integration
technology can transfer the photon response of the detector
pixels to the underlying ROIC cells with high operability and
without the introduction of additional noise.

97.5% meet NE
Specification

Figure 3. Two-plane SEM micrograph of a three-layer

vertically integrated sensor array (VISA) device.

cm2)

A.
Proof-of-Concept Demonstration
A. Performance of MWIR FPA Detector with 3-D Si ROIC
For an initial demonstration, a passive Si layer was used as a
surrogate for Si IC2. A readout IC incorporating a
multiplexing function was used as Si IC1. The device had the
form of a 256x256 array of pixels on a 30 m pitch. Each
pixel contained one vertical interconnect 4 m in diameter.
Following the fabrication of 3-D interconnects and the
capping and patterning of the Cu film, the MCT FPA layer
was integrated into the stack. The arrays were tested both
before and after the fabrication of the FPA, the former to
verify the operability of the 3-D interconnects and of the
underlying IC. Following the integration of the FPA layer,
electrical testing was performed to obtain a histogram of the
noise equivalent flux, NE, which is a metric of signal-tonoise performance of the device, and a thermal image was
obtained. Figure 4a displays the NE histogram for the
demonstration vehicle. The dotted line indicates the NE

B.
Figure 4. A) Histogram of the noise equivalent flux
measured for the MWIR FPA demonstration vehicle;
B) Infrared image obtained using the demonstration
vehicle.

B. Electrical Properties of Vertical Interconnects

Operability maps obtained from the fully integrated FPA
device provide only qualitative information regarding the
resistance of vertical interconnects. To obtain quantitative
information, a two-layer passive Si stack, referred to as the
contact resistance testbar, was designed. The testbar contains
an 8x8 array of 3-D interconnects spanning the top thin layer.
These interconnects land on a fanout pattern on the bottom
die. The fanout is designed in such a way that the vertical
interconnects are electrically isolated from each other, and a
four-point measurement can be performed for each of the
interconnects, as illustrated in Figure 5. This four-point
measurement gives the value of the resistance of each
interconnect, eliminating the contribution of probe resistances
and lead resistances inherent in two-point measurements.
The measurement is performed in the so-called dry-circuit
mode at voltages below 20 mV.

C. Reliability of 3-D stack

To evaluate reliability of the 3-D integrated structure, several
of the 256x256 FPA test vehicles were subjected to thermal
cycling between the room temperature and the temperature of
liquid nitrogen. No change in operability was observed
following 1000 cycles. Similar tests, albeit less rigorous (~10
cycles), were performed for 8x8 contact resistance testbars.
No changes in values of contact resistance were measured.
Conclusions
A novel 3-D integration technology is under development to
enable stacking of multiple layers of Si ICs. The ICs in the
separate layers communicate by means of 3-D interconnects insulated and metallized vias etched through the body of the
chips. Among many potential applications of the technology
are high performance focal plane detector arrays where the
ability to integrate multiple layers of Si electronics within the
footprint of each pixel will open doors to dramatically
improved functionality of the readout circuit.
Acknowledgements

Figure 5. Schematic illustrating the common side fourwire resistance measurement used for the contact
resistance testbars and a SEM micrograph of the contact
resistance testbar resistance circuit.
Figure 6 shows an 8x8 resistance map obtained from such a
testbar. The four-wire resistance values across the die range
from 30 m to 3 , with an average resistance value around
140 m (excluding the 3 interconnect). Subtracting from
this value the resistance of the vertical interconnect one can
calculate the value for the specific contact resistivity between
the vertical interconnect and the pad. For the interconnects
of the testbar this value was found equal to approximately
1x10-8 cm2.

Figure 6. Resistance map for 8x8 array of 3-D

interconnects in contact resistance testbar.

This material is based on the work performed under the support

of DARPA under SSC-San Diego under contract no. 66001-C05-8020.
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2
M.A. Kinch, HDVIP FPA Technology at DRS,
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Peter D. Dreiske Development of Two-Color Focal-Plane
Arrays Based on HDVIP, Proc. of SPIE, Vol. 5783, 2005,
p. 325.
1