Chapter-9

Level I
10. Ans: (c)
Sol: A0 to A9 are used for line selection
A10 to A12 are used for chip selection of
RAM.
Output 4 (select code is 100) of 3 8 line
decoder is used to drive chip select of RAM.
A13 to A15 are used for chip selection of
Decoder.
A15 A14 A13 A12 A11 A10 A9 - - --A0
1
1 1 1 0 0
0----0

=F000H

12. Ans: (b)

Sol: A0 to A12 (13 Address lines) of 8085
microprocessor are used for line selection
A13, A14 & A15 of 8085 p are used for chip
selection.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0

0 0

0 0 0 0 0 0 0 0 0 0 0 = 0000H

1 1 1 1 1 1 1 1 1 1 1= 1FFFH

.
.
.

0 0

0 1

Address range occupied by the ROM is

0000H to 1FFFH
13. Ans: (d)
Sol: Number of chips =

1----1

=F3FFH

Address range for the chip is

F000H F3FFH

A3

A4

A5
A6
A7

1
1
0

1
1

14. Ans: (c)

Sol: A0 & A1 are used for port selection.
A2 is unused.
A3 to A7 are used for chip selection.
IO/M A A A A A A A A
7
6
5
4
3
2
1
0

11. Ans: (a)

Sol: A0 & A1 are used for line selection
A2 to A7 are used for chip selection
A2

2 20 8
32
216 4

Address space is 60H to 63H

Chip select 0

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

1
1
1
1

0
0
1
1

0
1
0
1

A2 can be either 0 or 1.
If A2 = 0, then Address Range becomes
F8 to FB.
If A2 = 1, then Address Range becomes
FC to FF.
The Range of Addresses for which the 8255
chip would get selected is F8 to FF.

15. Ans: (d)

Sol: The output Y5 is used for chip select of
device. The select code for Y5 is 101.
A15 A14 A13 A12 A11 A10 A9 A8 A7 - - - A0
1

0 1

0----0

1 0 1

1----1

=FD00H

=FDFFH

16.

Ans: (b)

Sol: Address range of IO device is D4H to D7H

D4H
D5H
D6H
D7H

A7
1
1
1
1

A6
1
1
1
1

A5 A4 A3 A2 A1 A0
0 1 0 1 0 0
0 1 0 1 0 1
0 1 0 1 1 0
0 1 0 1 1 1

12. Ans : (c)

Sol: RST instruction is a software interrupt which
is maskable. All maskable interrupts are
enabled only if EI instruction gets executed.
14. Ans : (b)
Sol: Line difference for 4K 8 memory
is
0FFFH.
End Address = AA00H + 0FFFH
= B9FFH
15. Ans: (c)
Sol: Line difference
= 9FFFH8000H
= 1 FFFH
1FFFH corresponds to 13 address lines
No of bytes = 213 = 8192
16. Ans: (a)
Sol: Ao to A11 are used for line selection
A12 to A15 are used for chip selection
A15 A14 A13 A12A11 - - - - - A01
1 00 - - - - - - - 0

A0 & A1 used for line selection

A5, A6 & A7 are used for chip enable of 3 8
Decoder
A2, A3 & A4 are used for selecting output 5.
101 is select code for output 5

Level II
04. Ans: (b)
Sol: Processor frequency =

fc
2

5MHz
2.5 MHz
2

Duration of one T-state

1

= processor frequency

1
= 0.4s
2.5MHz

06. Ans: (c)

Sol: In DMA, transfer of data between source &
Destination takes place without any
involvement of microprocessor, both in read /
write mode

1
=E000H

01 - - - - - - - - 1
=EFFFH

17.
Sol:

Ans: (d)
Both
the
chips have active high chip select
inputs.

Chip 1 is
selected when A8 = 1, A9 = 0
Chip 2 is selected when A8 = 0, A9 = 1
Chips

are not selected for combination of 00 &

11 of A8 & A9
Upon

observing A8 & A9 of given address

Ranges, F800 to F9FF is not represented

18. Ans: (d)

Sol: For 2 : 4 decoder
a1
a0
output
0
0

b0
0
1

b1
1
0

b2
1
1

b3
Chip selection cs must be low means A15 high

The Instruction for correct data transfer is

= LDA F8F8H
21.
Sol:

a1=1 a0=0
A15=1 A13=1 A14=0
A15 A14 A13 0 0 0 0 0 0 0 0 0
1
0
1
0 0 0 0 0 0 0 0 0
0 0

Ans: (b).
Out put 2 of 38 Decoder is used for
selecting the output port. Select code is
010
A15 A14 A13 A12 A11 A10 -- A0
0 1
0
1
0 0 --- - 0
5000H
This mapping is memory mapped I/o

0 0 0 0

0

= (C000)H

Chapter-10
Level I

19. Ans : (d)

Sol:

02. Ans: False

Sol: Stack operating principle is LIFO

A15 A14 A13 A12 A11 A10 A9 - - - - A0

0

0----0

=0800H

1----1

=0BFFH

0----0

=1800H

1----1

=1BFFH

0----0

=2800H

1----1

=2BFFH

0----0

=3800H

20.

03. Ans: (b)

Sol: DAA is Decimal Adjust Accumulator
which is an arithmetic instruction.
LXI instruction is used for initializing a 16
bit register with 16 bit number given in the
instruction. As such, it is a data movement
instruction.
RST is a software interrupt instruction.
JMP is a branch control or program control
instruction.
04. Ans: (c)
Sol: SHLD 2050H

=3BFFH

1----1

Ans: (d)

Sol: The I/O device is interfaced using Memory

Mapped I/O technique.
The address of the Input device is
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A A3 A2 A1 A0
4
1

1 1

1 0 0

0 =F8F8H

;
;

(2050H)
(2051H)

(L)
(H)

05. Ans: (a)

Sol: Carry flag will be set to 1 since borrow
required.
Zero flag will be reset since the result is nonzero.
06. Ans: (c)

Sol: XRA A instruction execution resets contents

of accumulator and hence sets zero flag.
07. Ans: (a)
Sol: (B) = 49 H
0100 1001
1s compliment of (B) 1011 0110
2s compliment of (B) 1011 0111
= 49
SUB B ; (A) (A) (B)
; (A) = 3AH 0011 1010
+
; (B) = 49 1 1011 0111
1111 0001
; (A) = 1111 0001
; (A) = F1H, CY = 1,
;
S = 1, Z = 0
08. Ans: (d)
Sol: According to given information:
IO/ M = 1 i.e., IO access operation
RD 1 , WR 0 i.e., write operation
Address 2020H, data 24H
The operation is IO write operation of data
24H into output port whose address 20H.
The instruction being executed is OUT
20H.
09. Ans: (c)
Sol: LXI H, 9258
; (HL) = 9258H
MOV A, M
; (A) ((HL)) = x
CMA
; (A) (A )
MOV M, A
; ((HL)) (A) = x
The contents of location 9258H is
complemented and stored at same address
10. Ans: (a)
Sol: XCHG ; (HL) (DE)
INR M ; ((HL)) ((HL)) + 1
11. Ans: (d)
Sol: XRA
A
MOV L, A
MOV H, L
INX
H

; (A) = 00H
; (L) (A) = 00H
; (H) (L) = 00H
; (HL) = 0001H

DAD

; (HL) (HL) + (HL)

; (HL) = 0002H

12. Ans: (PC) = 200AH, (SP) = 0FFEH

Sol:
2000H: LXI SP, 1000H ; (SP) = 1000H
PUSH H
; (TOS) (HL)
and (SP)
; (SP) = 0FFEH
PUSH D
; (TOS) (DE)
and (SP)
; (SP) = 0FFCH
CALL 2050H ; (SP) when
program
control is
transferred to
2050H
; (SP) when
program control
is returned back
to next to CALL
instruction
(SP) = 0FFCH
POP H ; (HL)(TOS) and (SP)
; (SP) = 0FFEH
2009H : HLT ; (PC) = 200AH
(PC) = 200AH and (SP) = 0FFEH
13. Ans: (d)
Sol:
MVI
LOOP: ADD
DCR
JNZ
HLT
END
14. Ans: (c)
Sol: LXI
MOV
INR
MOV
ADD
INR
MOV
XRA

A, 00H
B
C
LOOP

H, 1FFF ; (HL) =1FFE

B, M ; (B) (1 FFE)=x
L
; (L) = FF
A, M ; (A) (1FFF)=y
B
; (A) (A)+(B)
; (A) = x+y
L
; (L) = 00
M, A ; (1F00) (A)=x+y
A
; (A) = 00

 on

completion of the execution of the

program the result of addition is found at
address 1F00

15. Ans: (c)

Sol: 2710H : LXI H,30A0H ; (HL)=30A0H
2713H : DAD H
; (HL)(HL)+(HL)
; (HL) = 6140H
2714H : PCHL
; (PC) (HL)
= 6140H
16. Ans: (c)
Sol:
6010H : LXI H,8A79H ; (HL) = 8A79H
6013H : MOV A, L ; (A)(L) = 79
6014H : ADD H
; (A) = 0111 1001
+
; (H) = 1000 1010
; (A) = 0000 0011
CY = 1, AC = 1
6015H : DAA
; 66 Added to (A)
since CY=1 & AC=1
; (A) = 69H
6016H : MOV H,A
; (H)(A) =69H
6017H : PCHL

; (PC)(HL) = 6979H

(PC) = E000H
(SP) = 23FEH

05. Ans: (c)

Sol:
0100H : LXI SP, 00FFH ; (SP) = 00FFH
0103H : LXI H, 0107 H ; (HL) = 0107H
0106H : MVI A, 20H ; (A) = 20H
0108H : SUB M
; (A)(A)-(0107)
; (0107) = 20H
; (A) = 00H
The contents of Accumulator is 00H
06. Ans : (c)
Sol: 0109H : ORI 40H ; (A) 00H+40H
= 40H
010BH : ADD M ; (A)(A)+(0107H)

; (A) = 60H
The result in Accumulator is 60H
07.
Sol:

Ans: (b)
MVI B, 87H ; (B) = 87H
MOV A, B ; (A) (B) = 87H
JMP NEXT ; Jumps to NEXT
NEXT: XRA B ; (A)(A)=87H

Level -2
01. Ans: (c)
Sol: Compare instructions
(CMPC & CPI 3A) execution doesnt alter
content of operands involved in comparison.
And, ORA A instruction retains the value in A
02. Ans: (d)
Sol: Initial contents:
(SP) = F000H
(PC) = 2400H
For the execution of CALL E000, the
current contents of program counter i.e, 2400
is pushed into top of stack and then program
counter will be initialized with E000.
Because of pushing, contents of stack
pointer will be decremented by 2.

(B)=87H
; (A)=00H,(B)=87H,
S=0
JP START; Jumps to START
since S = 0
START: JMP NEXT
NEXT: XRA B ; (A) (A) = 00H
(B)= 87H
; (A) = 87H,
(B) = 87H, S=1
JP START ; Test fails since S=1
OUT PORT 2 ; (PORT 2)(A)
=87H
HLT
; Halted

08.

SP HL + SP
= 0000H + 200EH
= 200EH
XCHG HL & DE will exchange
DE 200EH

Ans: (b)

DAD

Sol: LXI SP, EFFFH ; (SP) =EFFFH

CALL 3000H ; (TOS)3000H---Next instr. Address
; (SP)i.e.,(SP)=EFFD

10. Ans: (b)

Sol: SUB1 : MVI A, 00H
A00H
CALL SUB program will shifted to SUB
2 address location

; (PC) 3000H--Target
Address
3000H: LXI H,3CF4H ; (HL) = 3CF4H
PUSH PSW

SUB 2 : INR A

; (TOS)(PSW)

RET returned to the main program

The contents of Accumulation after
execution of the above SUB2 is 01H

; (SP) = EFFB
SPHL

; (SP)(HL) = 3CF4H

POP PSW

; (PSW)(TOS) and
(SP)
; (SP) = 3CF6H

RET

; (SP)
; (SP) = 3CF8H

11. Ans: (d)

Sol: The loop will be executed until the value in
register equals to zero, i.e. 10 times, then,
Execution time
= 10 (7T 4T 4T 10T ) 7T
= 257T

09. Ans: (a)

H
Sol: LXI H, 0000H 0000H

PUSH

12. Ans:- (d)

Sol:

H
00 00

H=255 :L=255, 254, 253, ----0

H=254 :L=0, 255, 254, -------0
|

00

2010

00

200F

HL
00 00

POP

A
01H

and (SP)

PUSH

H=1 :L=0,255,254,253,---0
H=0 :
In first iteration (with H=255), the value in L
is decremented from 255 to 0 i.e., 255
times
In further remaining 254 iterations, the value in
L is decremented from 0 to 0 i.e., 256 times
DCRL instruction gets
executed for
[255 (254 256)]
65279 times

BC
00 00

00

200E

00

200D

00

200F

00

200D

13. Ans: (a)

Sol: MVI A, 05H
MVI B, 05H
ADD B
;(A)(A)=05+(B)=05H
; (A)=0A H
DCR B
; (B)=04 H
JNZ PTR ; Jumps to PTR since Z=0

PTR:ADD B ; (A)(A)=0AH+(B)
=04H
; This looping is continued till
; (B) becomes 0 due to
DCR B instruction
; (A) = 14H
ADI 03H ; (A) = 17H
HLT
At the end of program, Accumulator
contains 17H
14. Ans: (a)
Sol: STA 1234H is a 3Byte Instruction and it
requires 4 Machine cycles (Opcode fetch,
Operand1 Read, Operand2 Read, Memory
write). The Higher order Address (A15 A8)
sent in 4 machine cycles is as follows
Given STA 1234 is stored at 1FFEH
i.e.,
Address

Instruction

1FFE, 1FFF, 2000 : STA 1234H

Machine
cycle

Address
(A15-A0)

1. Opcode
fetch
2. Operand1
Read
3. Operand2
Read
4. Memory
Write

1FFEH

Higher order
address
(A15-A8)
1FH

1FFFH

1FH

2000H

20H

1234H

12H

i.e. Higher order Address sent on A15A8 for

4 Machine Cycles are 1FH, 1FH,20H, 12H
15.
Sol:

Ans: (a) .
B
04

A
03

Cy
0

initial values

For each iteration :

(A) = 0000 0001 , Cy = 1
(B) = 03, Z = 0
(A) = 1000 0000 , Cy = 1
(B) = 02 , Z = 0
(A) = 1100 0000 , Cy = 0
(B) = 01 , Z = 0

(A) = 0110 0000 , Cy = 0

(B) = 00 , Z = 1 iteration terminated with
(A) = 60 H

16. Ans: (c)

Sol: LHLD 2100 H
L M ( 2100 )
H M ( 2101 )