EMT 235/3 DIGITAL PRINCIPLES II

LAB MODULE

EMT 235
DIGITAL ELECTRONIC
PRINCIPLES II

School of Microelectronic Engineering

Universiti Malaysia Perlis

EMT 235/3 DIGITAL PRINCIPLES II

LAB 2: DESIGN OF COUNTERS

OBJECTIVES:
1. To recognize the operation of counters.
2. To practise sequential logic circuits design.
3. To implement the design of counters in the Quartus II software

EQUIPMENT & COMPONENTS:

Computer unit
Altera Quartus II software

INTRODUCTION:
A counter is:
A register that counts through a specific sequence of states upon the application
of a sequence of input pulses, i.e. clock and/or other input signals.
A register is:
A group of flip-flops that can be used to store more than one-bit of data.
A flip-flop is a synchronous bistable device.
The inputs together with present state determine the outputs and its next state, at
either the positive edge or the negative edge of the clock pulse.
Edge-triggered flip-flops comprise of: SR flip-flop, JK flip-flop, D flip-flop and T flipflop. The Excitation Table for these flip-flops is as depicted in Table 3.1.
Table 2.1 Excitation Tables for JK, SR, D and T flip-flops
Q

Q+

EMT 235/3 DIGITAL PRINCIPLES II

PRE-LAB PREPARATION:
Develop the design for the two Design Problems given in the EXPERIMENTAL
METHOD part using the pen and paper technique, by means of these steps:

Develop the State Diagram (include only valid states)

Build the Karnaugh maps.

Derive the Boolean expressions.

Sketch the logic circuit.

EXPERIMENTAL METHOD:
Both Design Problems I and II involve synchronous counter circuits.
1. Use JK flip-flops. Set CLOCK of each JK flip-flop as input ports and Q0 to Qn as
output ports, with Q0 as the Least Significant (LSB) bit and Qn as the Most
Significant (MSB) bit.
2. Use Quartus II to draw the schematic diagram, simulate the circuit and generate
the logic symbol.

Connect the PRESET and CLEAR pins of the JK flip-flops to Vcc (logic 1)
since both input pins are working on active low. The JK flip-flop symbol can
be found under the primitives | storage library; its component name is
jkff.

3. Verify the simulated outputs with the theoretical outputs.

The output waveforms of the counter can be merged together as one group,
with its values converted from n-bit binary values, to be declared either as a
hexadecimal (hex) or a decimal value.

To do this, select the counter output waveforms, from Q0 to Qn. Then, right
click | grouping | group, followed by giving a name to the group, e.g. Q
[n..0].

EMT 235/3 DIGITAL PRINCIPLES II

Design Problem I
Construct the design for the 4-bit Up-Counter illustrated by the state diagram in Figure
2.2.

START

15

14

13

3
4

12

11

5
10

6
9

Figure 2.2 4-bit Up-Counter State Diagram

Design Problem II
Design of a 3-bit Up-Down Binary counter.

The Counting UP sequence (UPDOWN=1): 02 4 6

The Count DOWN sequence (UPDOWN=0): 7 5 3 1

EMT 235/3 DIGITAL PRINCIPLES II

EMT 253/3 DIGITAL ELECTRONIC

PRINCIPLES II ASSESSMENT FORM
LAB 2

NAME:

MATRIX NO:

COURSE:

DATE:

RESULTS VERIFICATION:
Design Problem I

Item
Schematic

Status

Instructor
Verification

Drawing completed
Error-free upon compilation
Symbol generated

Waveform

All I/O nodes available

Input waveforms properly generated
Output waveforms confirms expected results
Run functional simulation
Observed timing simulation

Design Problem II

Item
Schematic

Status
Drawing completed
Error-free upon compilation
Symbol generated

Waveform

All I/O nodes available

Input waveforms properly generated
Output waveforms confirms expected results
Run functional simulation
Observed timing simulation

Instructor
Verification