Contents

1. INTRODUCTION ............................................................................................... 4
1.1 ARCHITECTURE ....................................................................................................................................... 5
1.2 DATA TRANSMISSION ............................................................................................................................ 5
1.3 BIT TIMING ............................................................................................................................................. 7
1.4 LAYERS.................................................................................................................................................... 7
1.5 DATA FRAME ........................................................................................................................................ 11

2. EMBEDDED SYSTEMS ................................................................................. 13

2.1 INTRODUCTION .................................................................................................................................... 13
2.2 DEFINITION OF AN EMBEDDED SYSTEM .............................................................................................. 14
2.3 FEATURES OF AN EMBEDDED SYSTEM ................................................................................................ 15
2.4 CHARACTERISTICS OF AN EMBEDDED SYSTEM.................................................................................... 16
2.5 TYPES OF EMBEDDED SYSTEMS ........................................................................................................... 16

3. HARDWARE DESCRIPTION ........................................................................ 18

3.1 ATmega32 Controller ....................................................................................................................... 18
3.1.1 OVERVIEW ..................................................................................................................................... 18
3.1.2 FEATURES ...................................................................................................................................... 20
3.1.3 I/O AND PACKAGES ....................................................................................................................... 21
3.1.4 OPERATING VOLTAGES ................................................................................................................ 22
3.1.5 SPEED GRADES .............................................................................................................................. 22
3.1.6 PIN CONFIGURATION ................................................................................................................... 22
3.1.7 PIN DESCRIPTIONS ....................................................................................................................... 23

4.LIQUID CRYTAL DISPLAY ........................................................................... 25

4.1 INTRODUCTION .................................................................................................................................... 25
4.2 PIN DESCRIPTION of LCD ...................................................................................................................... 26
4.2.1 PIN DESCRIPTIONS ........................................................................................................................ 26
4.3 ADVANTAGES ....................................................................................................................................... 27
4.4 BASIC COMMANDS of LCD ................................................................................................................... 27
4.5 COLLISION AVOIDANCE SENSOR .......................................................................................................... 27
4.5.1 INTRODUCTION ............................................................................................................................. 27

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4.6 MCP 2515 & MCP 2551 CHIPS ........................................................................................................... 28

4.6.1 DESCRIPTION & PIN DIAGRAM...................................................................................................... 28
4.6.2 FEATURES ...................................................................................................................................... 28
4.6.3 DEVICE OVERVIEW ........................................................................................................................ 29
4.6.4 DEVICE OVERVIEW ....................................................................................................................... 30
4.6.5 PIN DIAGRAM ................................................................................................................................ 30
4.6.6 FEATURES ...................................................................................................................................... 30
4.7 APPLICATIONS ...................................................................................................................................... 31

5. CONCLUSION .................................................................................................. 32

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LIST OF FIGURES
Figure 1 Bit timing ........................................................................................................................................... 7
Figure 2 CAN Layers ....................................................................................................................................... 8
Figure 3 Base frame format ........................................................................................................................... 11
Figure 4 CAN circuit diagram ...................................................................................................................... 19
Figure 5 Pin diagram...................................................................................................................................... 22
Figure 6 Liquid crystal display ....................................................................................................................... 25
Figure 7 Pin diagram of MCP2515................................................................................................................. 28
Figure 8 Pin diagram of MCP 2551 .............................................................................................................. 30

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1. INTRODUCTION
The Controller Area Network (CAN) is a Serial, Asynchronous, Multi-master communication
protocol for connecting electronic control modules in Automotive and industrial applications.
CAN protocol have many features like low cost, Easy to implement, peer to peer network with
powerful Error checking, higher transmission rates 1MBitps.
The CAN Network is a Peer to Peer Network consisting of different nodes. Different parameters
can be monitored by these nodes and can be updated to the Central control unit. Mostly used in
Industry and Auto Mobiles in a hazardous environment and is reliable.
This project is designed for collision avoidance system for automobiles using CAN protocol.
Using CAN protocol we can send data from one node to other node. Here we are having
two nodes each node contains ATmega32 (AVR Controller), MCP2515 (CAN Controller)
MCP2551 (CAN Transceiver). In first node we are interfacing Collision avoidance sensor to find
the object. Second node contains DC motor. If any object is found in front of Collision avoidance
sensor in node1, DC motor in node2 stops running by using CAN protocol. For this we have to
develop two different application programs in AVR studio.
The CAN bus may be used in vehicles to connect engine control unit and transmission, or (on a
different bus) to connect the door locks, climate control, seat control, etc. Today the CAN bus is
also used as a field bus in general automation environments; primarily due to the low cost of some
CAN Controllers and processors.

CAN bus (for controller area network) is a vehicle bus standard designed to allow
microcontrollers and devices to communicate with each other within a vehicle without a host
computer. CAN bus is a message-based protocol, designed specifically applications but now also
used in other areas such as aerospace, maritime , industrial automation and medical equipment.

Development of the CAN bus started originally in 1983 at ROBERT. The protocol was officially
released in 1986 at the Society of Automotive Engineers (SAE) congress in Detroit, Michigan. The
first CAN controller chips, produced by Intel and Philips, came on the market in 1987. Bosch
published the CAN 2.0 specification in 1991. In 2012 Bosch has specified the improved CAN data
link layer protocol, called CAN FD, which will extend the ISO 11898-1.CAN bus is one of five
protocols used in the on-board diagnostics (OBD)-II vehicle diagnostics standard. The OBD-II
standard has been mandatory for all cars and light trucks sold in the United States since 1996, and
the EOBD standard has been mandatory for all petrol vehicles sold in the European Union since
2001 and all diesel vehicles since 2004.

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1.1 ARCHITECTURE
CAN is a multi-master serial bus standard for connecting ECUs.
Each node requires a

Central processing unit or host processor

The host processor decides what received messages mean and which messages it wants to
transmit itself
Sensors, actuators and control devices can be connected to the host processor.

CAN controller; hardware with a synchronous clock.

Receiving: the CAN controller stores received bits serially from the bus until an entire
message is available, which can then be fetched by the host processor (usually after the
CAN controller has triggered an interrupt).
Sending: the host processor stores its transmit messages to a CAN controller, which
transmits the bits serially onto the bus.

Transceiver
Receiving: it adapts signal levels from the bus to levels that the CAN controller expects
and has protective circuitry that protects the CAN controller.
Transmitting: it converts the transmit-bit signal received from the CAN controller into a
signal that is sent onto the bus.

Each node is able to send and receive messages, but not simultaneously. A message consists
primarily of an ID (identifier), which represents the priority of the message, and up to eight data
bytes. The improved CAN FD extends the length of the data section to up to 64 bytes per frame. It
is transmitted serially onto the bus. This signal pattern is encoded in non-return-to-zero (NRZ)
format and may be received by all nodes.
The devices that are connected by a CAN network are typically sensors, actuators, and other
control devices. These devices are not connected directly to the bus, but through ahost
processor and a CAN controller.

1.2 DATA TRANSMISSION

CAN features an automatic arbitration-free transmission. A CAN message that is transmitted with
highest priority will succeed, and the node transmitting the lower priority message will sense this
and back off and wait. This is achieved by CAN transmitting data through a binary model of
"dominant" bits and "recessive" bits where dominant is a logical 0 and recessive is a logical 1. This
means open collector, or wired or physical implementation of the bus (but Since dominant is 0,
this is sometimes referred to as wired and). The idle state is represented by recessive level
(Logical 1). If one node transmits a dominant bit and another node transmits a recessive bit then
the dominant bit "wins" (a logical AND between the two).

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Truth tables for dominant/recessive, logical or, and logical and (for
comparison)
Bus state with two nodes transmitting
Dominant

Recessive

Dominant

Dominant

Dominant

Recessive

Dominant

Recessive

Logical or
0

Logical and
0

So, if a recessive bit is being transmitted while a dominant bit is sent, the dominant bit is
displayed, evidence of a collision. (All other collisions are invisible.) A dominant bit is asserted by
creating a voltage across the wires while a recessive bit is simply not asserted on the bus. If any
node sets a voltage difference, all nodes will see it. Thus there is no delay to the higher priority
messages, and the node transmitting the lower priority message automatically attempts to retransmit six bit clocks after the end of the dominant message.
When used with a differential bus, a carrier sense multiple access/bitwise arbitration (CSMA/BA)
scheme is often implemented: if two or more devices start transmitting at the same time, there is a
priority based arbitration scheme to decide which one will be granted permission to continue
transmitting. The CAN solution to this is prioritized arbitration (and for the dominant message
delay free), making CAN very suitable for real time prioritized communications systems.
During arbitration, each transmitting node monitors the bus state and compares the received bit
with the transmitted bit. If a dominant bit is received when a recessive bit is transmitted then the
node stops transmitting (i.e., it lost arbitration). Arbitration is performed during the transmission of
the identifier field. Each node starting to transmit at the same time sends an ID with dominant as
binary 0, starting from the high bit. As soon as their ID is a larger number (lower priority) they will
be sending 1 (recessive) and see 0 (dominant), so they back off. At the end of ID transmission, all
nodes but one have backed off, and the highest priority message gets through unimpeded.
For example, consider an 11-bit ID CAN network, with two nodes with IDs of 15 (binary
representation, 00000001111) and 16 (binary representation, 00000010000). If these two nodes
transmit at the same time, each will transmit the first six zeros of their ID with no arbitration
decision being made. When the 7th bit is transmitted, the node with the ID of 16 transmits a 1
(recessive) for its ID, and the node with the ID of 15 transmits a 0 (dominant) for its ID. When this
happens, the node with the ID of 16 will realize that it lost its arbitration, and allow the node with
ID of 15 to continue its transmission. This ensures that the node with the lower bit value will
always win the arbitration. The ID with the smaller number will win the right to use.

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Bit rates up to 1 Mbit/s are possible at network lengths below 40 m. Decreasing the bit rate allows
longer network distances (e.g., 500 m at 125 kbit/s). The improved CAN FD extends the speed of
the data section by a factor of up to 8 of the arbitration bit rate.

1.3 BIT TIMING

Each node in a CAN network has its own clock, and no clock is sent during data transmission.
Synchronization is done by dividing each bit of the frame into a number of segments:
synchronization, propagation, phase 1 and phase 2. The length of each phase segment can be
adjusted based on network and node conditions. The sample point falls between phase buffer
segment 1 and phase buffer segment 2, which helps facilitate continuous synchronization.
Continuous synchronization in turn enables the receiver to be able to properly read the
messages.

Figure 1 Bit timing

An example CAN bit timing with 10 time quanta per bit.

1.4 LAYERS
The CAN protocol, like many
thefollowing abstraction layers:

networking

protocols,

can

be

decomposed

into

Application layer
Object layer

Message and status handling

Transfer layer
Most of the CAN standard applies to the transfer layer. The transfer layer receives messages from
the physical layer and transmits those messages to the object layer. The transfer layer is
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responsible for bit timing and synchronization, message framing, arbitration, acknowledgement,
error detection and signaling , and fault confinement. It performs:

Fault Confinement

Error Detection
Message Validation
Acknowledgement
Arbitration
Message Framing
Transfer Rate and Timing

Information Routing

Physical layer

Figure 2 CAN Layers

CAN bus electrical sample topology with terminator resistors

CAN bus (ISO 11898-1:2003) originally specified the link layer protocol with only abstract
requirements for the physical layer, e.g., asserting the use of a medium with multiple-access at the
bit level through the use of dominant and recessive states. The electrical aspects of the physical
layer (voltage, current, number of conductors) were specified in ISO 11898-2:2003, which is now
widely accepted.
However, the mechanical aspects of the physical layer (connector type And number, colors, labels,
pin-outs) have yet to be formally specified. As a result, an automotive ECU will typically have a
particularoften customconnector with various sorts of cables, of which two are the CAN bus
lines. Nonetheless, several de facto standards for mechanical implementation have emerged, the
most common being the 9-pin D-sub type male connector with the following pin-out:

pin 2: CAN-Low (CAN-)

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pin 3: GND (Ground)

pin 7: CAN-High (CAN+)
pin 9: CAN V+ (Power)

This de facto mechanical standard for CAN could be implemented with node having both male and
female 9-pin D-sub connectors electrically wired to each other in parallel within the node. Bus
power is fed to a node's male connector and the bus draws power from the node's female
connector. This follows the electrical engineering convention that power sources are terminated at
female connectors.
Adoption of this standard avoids the need to fabricate custom splitters to connect two sets of bus
wires to a single D connector at each node. Such nonstandard (custom) wire harnesses (splitters)
that join conductors outside the node reduce bus reliability, eliminate cable interchangeability,
reduce compatibility of wiring harnesses, and increase cost.
The absence of a complete physical layer specification (mechanical in addition to electrical) freed
the CAN bus specification from the constraints and complexity of physical implementation.
However it left CAN bus implementations open to inter- interoperability issues due to mechanical
incompatibility.

Noise immunity on ISO 11898-2:2003 is achieved by maintaining the differential impedance of the
bus at a low level with low-value resistors (120 ohms) at each end of the bus. However, when
dormant, a low-impedance bus such as CAN draws more current (and power) than other voltagebased signaling busses. On CAN bus systems, balanced line operation, where current in one signal
line is exactly balanced by current in the opposite direction in the other signal provides an
independent, stable 0 V reference for the receivers. Best practice determines that CAN bus
balanced pair signals be carried in twisted pair wires in a shielded cable to minimize RF emission
and reduce interference susceptibility in the already noisy RF environment of an automobile.

ISO 11898-2 provides some immunity to common mode voltage between transmitter and receiver
by having a 0 V rail running along the bus to maintain a high degree of voltage association
between the nodes. Also, in the de facto mechanical configuration mentioned above, a supply rail
is included to distribute power to each of the transceiver nodes. The design provides a common
supply for all the transceivers. The actual voltage to be applied by the bus and which nodes apply
to it are application-specific and not formally specified. Common practice node design provides
each node with transceivers which are optically isolated from their node host and derive a 5 V
linearly regulated supply voltage for the transceivers from the universal supply rail provided by the

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bus. This usually allows operating margin on the supply rail sufficient to allow interoperability
across many node types. Typical values of supply voltage on such networks are 7 to 30 V.

However, the lack of a formal standard means that system designers are responsible for supply rail
compatibility. ISO 11898-2 describes the electrical implementation formed from a multi-dropped
single-ended balanced line configuration with resistor termination at each end of the bus. In this
configuration a dominant state is asserted by one or more transmitters switching the CAN- to
supply 0 V and (simultaneously) switching CAN+ to the +5 V bus voltage thereby forming a
current path through the resistors that terminate the bus. As such the terminating resistors form an
essential component of the signaling system and are included not just to limit wave reflection at
high frequency.
During a recessive state the signal lines and resistor(s) remain in a high impedances state with
respect to both rails. Voltages on both CAN+ and CAN- tend (weakly) towards rail voltage. A
recessive state is only present on the bus when none of the transmitters on the bus is asserting a
dominant state.
During a dominant state the signal lines and resistor(s) move to a low impedance state with respect
to the rails so that current flows through the resistor. CAN+ voltage tends to +5 V and CAN- tends
to 0 V.
Irrespective of signal state the signals lines are always in low impedance state with respect to one
another by virtue of the terminating resistors at the end of the bus.
This signalling strategy differs significantly from other balanced line transmission technologies
such as RS-422/3, RS-485, etc. which employ differential line drivers/ receivers and use a
signalling system based on the differential mode voltage of the balanced line crossing a notional
0 V. Multiple access on such systems normally relies on the media supporting three states (active
high, active low and inactive tri-state) and is dealt with in the time domain. Multiple access on
CAN bus is achieved by the electrical logic of the system supporting just two states that are
conceptually analogous to a wired OR network.

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1.5 DATA FRAME

The data frame is the only frame for actual data transmission. There are two message formats:

Base frame format: with 11 identifier bits

Extended frame format: with 29 identifier bits

The CAN standard requires the implementation must accept the base frame format and may accept
the extended frame format, but must tolerate the extended frame format.
Base frame format

Figure 3 Base frame format

CAN-Frame in base format with electrical levels without stuffbits

The frame format is as follows:

Field name

Length
(bits)

Purpose

Start-of-frame

Denotes the start of frame transmission

Identifier (green)

11

A (unique) identifier for the data which also

represents the message priority

Remote
transmission
request (RTR)

Dominant (0) (see Remote Frame below)

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Identifier extension
1
bit (IDE)

Declaring if 11 bit message ID or 29 bit message ID

is used. Dominant (0) indicate 11 bit message ID
while Recessive (1) indicate 29 bit message.

Reserved bit (r0)

Reserved bit (it must be set to dominant (0), but

accepted as either dominant or recessive)

Data length code

4
(DLC) (yellow)

Number of bytes of data (08 bytes)[a]

Data field (red)

064 (0-8 Data to be transmitted (length in bytes dictated by

bytes)
DLC field)

CRC

15

Cyclic redundancy check

CRC delimiter

Must be recessive (1)

ACK slot

Transmitter sends recessive (1) and any receiver can

assert a dominant (0)

ACK delimiter

Must be recessive (1)

End-of-frame
(EOF)

Must be recessive (1)

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2. EMBEDDED SYSTEMS
2.1 INTRODUCTION
Each day, our lives become more dependent on 'embedded systems', digital information
technology that is embedded in our environment. More than 98% of processors applied today are
in embedded systems, and are no longer visible to the customer as 'computers' in the ordinary
sense. An Embedded System is a special-purpose system in which the computer is completely
encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose
computer, such as a personal computer, an embedded system performs one or a few pre-defined
tasks, usually with very specific requirements. Since the system is dedicated to specific tasks,
design engineers can optimize it, reducing the size and cost of the product. Embedded systems are
often mass-produced, benefiting from economies of scale. The increasing use of PC hardware is
one of the most important developments in high-end embedded systems in recent years. Hardware
costs of high-end systems have dropped dramatically as a result of this trend, making feasible
some projects which previously would not have been done because of the high cost of non-PCbased embedded hardware. But software choices for the embedded PC platform are not nearly as
attractive as the hardware.
An embedded system is a computer system with a dedicated function within a larger mechanical
or electrical system, often with real-time computing constraints. It is embedded as part of a
complete device often including hardware and mechanical parts. By contrast, a general-purpose
computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range of
end-user needs. Embedded systems control many devices in common use today.

Modern embedded systems are often based on microcontrollers (i.e. CPUs with integrated memory
and/or peripheral interfaces)[4] but ordinary microprocessors (using external chips for memory and
peripheral interface circuits) are also still common, especially in more complex systems. In either
case, the processor(s) used may be types ranging from rather general purpose to very specialised in
certain class of computations, or even custom designed for the application at hand. A common
standard class of dedicated processors is the digital signal processor (DSP).

The key characteristic, however, is being dedicated to handle a particular task. Since the embedded
system is dedicated to specific tasks, design engineers can optimize it to reduce the size and cost of
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the product and increase the reliability and performance. Some embedded systems are massprod,.uced, benefiting from economies of scale.

Typically, an embedded system is housed on a single microprocessor board with the programs
stored in ROM. Virtually all appliances that have a digital interface -- watches, microwaves,
VCRs, cars -- utilize embedded systems. Some embedded systems include an operating system,
but many are so specialized that the entire logic can be implemented as a single program.
Physically, Embedded Systems range from portable devices such as digital watches and MP3
players, to large stationary installations like traffic lights, factory controllers, or the systems
controlling nuclear power plants.
In terms of complexity embedded systems can range from very simple with a single
microcontroller chip, to very complex with multiple units, peripherals and networks mounted
inside a large chassis or enclosure.

2.2 DEFINITION OF AN EMBEDDED SYSTEM

An Embedded system is defined as, for a particular/specific application implementing the software
code to interact directly with that particular hardware what we built. Software is used for providing
features and flexibility, Hardware = {Processors, ASICs, Memory...} is used for Performance (&
sometimes security).
(Or)
An embedded system is a special-purpose computer system designed to perform one or a few
dedicated functions, often with real-time computing constraints. It is usually embedded as part of a
complete device including hardware and mechanical parts. In contrast, a general-purpose
computer, such as a personal computer, can do many different tasks depending on programming.
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(Or)
An embedded system is a single-purpose computer built into a larger system for the purposes of
controlling and monitoring the system. A computer system that is part of a larger system or
machine.
There are many definitions of embedded system but all of these can be combined into a single
concept. An embedded system is a special purpose computer system that is used for particular task.

2.3 FEATURES OF AN EMBEDDED SYSTEM

The versatility of the embedded computer system lends itself to utility in all kinds of enterprises,
from the simplification of deliverable products to a reduction in costs in their development and
manufacture. Complex systems with rich functionality employ special operating systems that take
into account major characteristics of embedded systems. Embedded operating systems have
minimized footprint and may follow real-time operating system specifics.
The special computers system is usually less powerful than general-purpose systems, although
some expectations do exist where embedded systems are very powerful and complicated. Usually a
low power consumption CPU with a limited amount of memory is used in embedded systems.
Many embedded systems use very small operating systems; most of these provide very limited
operating system capabilities.
Since the embedded system is dedicated to specific tasks, design engineers can optimize it,
reducing the size and cost of the product, or increasing the reliability and performance. Some
embedded systems are mass-produced, benefiting from economies of scale.
Some embedded systems have to operate in extreme environment conditions such as very high
temperature & humidity.
For high volume systems such as portable music players or mobile phones, minimizing cost is
usually the primary design consideration. Engineers typically select hardware that is just good
enough to implement the necessary functions.

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For low volume or prototype embedded systems, general purpose computers may be adapted by
limiting the programs or by replacing the operating system with a real-time operating system.

2.4 CHARACTERISTICS OF AN EMBEDDED SYSTEM

An Embedded computing systems generally exhibit rich functionality complex functionality is
usually the reason for introducing CPUs into the design. However, they also exhibit many nonfunctional requirements that make the task especially challenging:
Real-time deadlines that will cause system failure if not met;
Multi-rate operation;
In many cases, low power consumption;
Low manufacturing cost, which often means limited code size.
Workstation programmers often concentrate on functionality. They may consider the performance
characteristics of a few computational kernels of their software, but rarely analyze the total
application. They almost never consider power consumption and manufacturing cost. The need to
juggle all these requirements makes embedded system programming very challenging and is the
reason why embedded system designers need to understand computer architecture.

2.5 TYPES OF EMBEDDED SYSTEMS

Based on functionality and performance embedded systems categorized as 4 types
1. Stand alone embedded systems
2. Real time embedded systems
3. Networked information appliances
4. Mobile devices
Stand alone embedded systems:
As the name implies, stand alone systems work in standalone mode. They take i/p, process them
and produce the desire o/p. The i/p can be an electrical signal from transducer or temperature
signal or commands from human being. The o/p can be electrical signal to drive another system an
led or LCD display
Ex digital camera, microwave oven, CD player, Air conditioner etc
Real time embedded systems:
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In this type of an embedded system a specific work has to be complete in a particular period of
time.
Hard Real time systems: - embedded real time used in missiles
Soft Real time systems: - DVD players
Networked information appliances:
Embedded systems that are provided with n/w interfaces and accessed by n/w's such as local area
n/w or internet are called Network Information Appliances.
Ex: A web camera is connected to the internet. Camera can send pictures in real time to any
computers connected to the internet
Mobile devices:
Actually it is a combination of both VLSI and Embedded System. Mobile devices such as Mobile
phone, Personal digital assistants, smart phones etc are special category of embedded systems.

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3. HARDWARE DESCRIPTION
3.1 ATmega32 Controller
3.1.1 OVERVIEW

The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves
throughputs approaching 1 MIPS per MHz allowing the system designed to optimize power
consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than
conventional CISC microcontrollers.

The ATmega32 provides the following features: 32K bytes of In-System Programmable Flash
Program memory with Read-While-Write capabilities, 1024 bytes EEPROM, 2K byte SRAM, 32
general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary
scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare

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Figure 4 CAN circuit diagram

The ATmega32 provides the following features: 32K bytes of In-System Programmable Flash
Program memory with Read-While-Write capabilities, 1024 bytes EEPROM, 2K byte SRAM, 32
general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary
scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare
modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire
Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with
programmable gain (TQFP package only), a programmable Watchdog Timer with Internal
Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops
the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters,
SPI port, and interrupt system to continue functioning. The Power-down mode saves the register
contents but freezes the Oscillator, disabling all other chip functions until the next External
Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run,
allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise
Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to
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minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up
combined with low-power consumption. In Extended Standby mode, both the main Oscillator and
the Asynchronous Timer continue to run.
The device is manufactured using Atmels high density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the Application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
Combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the
Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective
solution to many embedded control applications.

3.1.2 FEATURES
High-performance, Low-power AVR 8-bit Microcontroller
Advanced RISC Architecture
131 Powerful Instructions Most Single-clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 16 MIPS Throughput at 16 MHz
On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

32K Bytes of In-System Self-programmable Flash program memory
1024 Bytes EEPROM
2K Byte Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85C/100 years at 25C
Optional Boot Code Section with Independent Lock Bits
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In-System Programming by On-chip Boot Program True Read-While-Write Operation

Programming Lock for Software Security

JTAG (IEEE std. 1149.1 Compliant) Interface

Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features
Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
Real Time Counter with Separate Oscillator
Four PWM Channels
8-channel, 10-bit ADC
-8 Single-ended Channels
-7 Differential Channels in TQFP Package Only
-2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
Byte-oriented Two-wire Serial Interface
Programmable Serial USART
Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator

Special Microcontroller Features

Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and -

--

Extended Standby

3.1.3 I/O AND PACKAGES

32 Programmable I/O Lines
40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

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3.1.4 OPERATING VOLTAGES

2.7 - 5.5V for ATmega32L
4.5 - 5.5V for ATmega32

3.1.5 SPEED GRADES

0 - 8 MHz for ATmega32L
0 - 16 MHz for ATmega32
Power Consumption at 1 MHz, 3V, 25C for ATmega32L
Active: 1.1 mA
Idle Mode: 0.35 mA
Power-down Mode: < 1 A

3.1.6 PIN CONFIGURATION

Figure 5 Pin diagram

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3.1.7 PIN DESCRIPTIONS

VCC

:Digital supply voltage.

GND

:Ground.

Port A (PA7-PA0 :Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port A output buffers have
symmetrical drive characteristics with both high sink and source capability. When pins PA0 to
PA7 are used as inputs and are externally pulled low, they will source current if the internal pullup resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port B (PB7-PB0): Port B is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port B output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port B pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition
becomes active, even if the clock is not running.

Port C(PC7-PC0): Port C is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port C output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port C pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition
becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up
resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. The
TD0 pin is tri-stated unless TAP states that shift out data are entered.

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Port D (PD7-PD0): Port D is an 8-bit bi-directional I/O port with internal pull-up resistors
(selected for each bit). The Port D output buffers have symmetrical drive characteristics with both
high sink and source capability. As inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition
becomes active, even if the clock is not running.

RESET: Reset Input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running.

XTAL1: Input to the inverting Oscillator amplifier and input to the internal clock operating
circuit.

XTAL2: Output from the inverting Oscillator amplifier.

AVCC: AVCC is the supply voltage pin for Port A and the A/D Converter. It should be
externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be
connected to VCC through a low-pass filter.

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4.LIQUID CRYTAL DISPLAY

4.1 INTRODUCTION
Liquid crystal display is a type of display used in digital watches and many portable computers.

Figure 6 Liquid crystal display

LCD displays utilize two sheets of polarizing material with a liquid crystal solution between them.
An electric current passed through the liquid causes the crystals to align so that light cannot pass
through them. Each crystal, therefore, is like a shutter, either allowing light to pass through or
blocking the light.
The liquid crystals can be manipulated through an applied electric voltage so that light is allowed
to pass or is blocked.
By carefully controlling where and what wavelength (color) of light is allowed to pass, the LCD
monitor is able to display images. A back light provides LCD monitors brightness.
Other advances have allowed LCDs to greatly reduce liquid crystal cell response times.
Response time is basically the amount of time it takes for a pixel to change colors. In reality
response time is the amount of time it takes a liquid crystal cell to go from being active to inactive.
Here the LCD is used at both the Transmitter as well as the receiver side.
The input which we give to the microcontroller is displayed on the LCD of the transmitter side and
the message sent is received at the receiver side which displays at the receiver end of the LCD and
the corresponding operation is performed
They make complicated equipment easier to operate. LCDs come in many shapes and sizes but the
most common is the 16 character x 4 line display with no backlight.

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It requires only 11 connections eight bits for data (which can be reduced to four if necessary) and
three control lines (we have only used two here). It runs off a 5V DC supply and only needs about
1mA of current. The display contrast can be varied by changing the voltage into pin 3 of display.
4.2 PIN DESCRIPTION of LCD

From this description, the interface is a parallel bus, allowing simple and fast reading/writing of
data to and from the LCD. This waveform will write an ASCII Byte out to the LCD's screen.

4.2.1 PIN DESCRIPTIONS

Vcc, Vss and Vee
While Vcc and Vss provide +5V and ground respectively, Vee is used for controlling LCD
contrast
The ASCII code to be displayed is eight bits long and is sent to the LCD either four or eight bits at
a time.
If four bit mode is used, two "nibbles" of data (Sent high four bits and then low four bits with an
"E" Clock pulse with each nibble) are sent to make up a full eight bit transfer.
The "E" Clock is used to initiate the data transfer within the LCD.
Deciding how to send the data to the LCD is most critical decision to be made for an LCD
interface application.
Eight-bit mode is best used when speed is required in an application and at least ten I/O pins are
available.
The "R/S" bit is used to select whether data or an instruction is being transferred between the
microcontroller and the LCD.
If the Bit is set, then the byte at the current LCD "Cursor" Position can be reader written.
When the Bit is reset, either an instruction is being sent to the LCD or the execution status of the
last instruction is read back
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4.3 ADVANTAGES
LCD interfacing with 8051 is a real-world application. In recent years the LCD is finding
widespread use replacing LEDs (seven segment LEDs or other multi-segment LEDs).
This is due to following reasons:
1. The declining prices of LCDs.
2. The ability to display numbers, characters and graphics. This is in contrast to LEDs, which
are limited to numbers and a few characters. An intelligent LCD display of two lines, 20
characters per line, which is interfaced to the 8051.
3. Incorporation of a refreshing controller into the LCD, thereby relieving the CPU to keep
displaying the data.
4. Ease of programming for characters and graphics.

4.4 BASIC COMMANDS of LCD

When LCD is powered up, the display should show a series of dark squares, possibly only on part
of display.
These characters are actually in their off state, so the contrast control should be adjusted anticlockwise until the squares are just visible.
The display module resets itself to an initial state when power is applied, which curiously the
display has blanked off so that even if characters are entered, they cannot be seen.
It is therefore necessary to issue a command at this point, to switch the display on.

4.5 COLLISION AVOIDANCE SENSOR

4.5.1 INTRODUCTION
The sensor is based on the principle of Infrared Reflection. It makes use of Infrared rays
modulated at 38 kHz and then receiving the reflected rays. The circuit is built around the popular
NE555 timer IC operating in Astable Multivibrator mode.
A continuous beam of IR rays modulated at 38k Hz is emitted by the IR LED connected to the O/P
pin of the 555 (pin-3). The receiver used is TSOP1738 from Vishay; it has a built-in filter and
gain-amplifier.
When theres an Obstacle in front of the module, the IR rays are reflected back and fall on the
receiver (TSOP1738), making its output LOW, which is otherwise HIGH. The LED indicator
should not be confused with Active High o/p. The LED is connected across the +Vcc and Data pin
of TSOP with a 1K resistor in series.

QUICK REFERENCE:
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Obstacle
No Obstacle

: LED Glow
: LED Off

: Output is 0.0 - 0.2V

: Output is 5.0 - 5.2 V

4.6 MCP 2515 & MCP 2551 CHIPS

MCP 2515:
4.6.1 DESCRIPTION & PIN DIAGRAM
Microchip Technologys MCP2515 is a stand-alone Controller Area Network (CAN) controller
that implements the CAN specification, version 2.0B. It is capable of transmitting and receiving
both standard and extended data and remote frames. The MCP2515 has two acceptance masks and
six acceptance filters that are used to filter out unwanted messages, thereby reducing the host
MCUs overhead. The MCP2515 interfaces with microcontrollers (MCUs) via an industry standard
Serial Peripheral Interface (SPI).

Figure 7 Pin diagram of MCP2515

4.6.2 FEATURES
Implements CAN V2.0B at 1 Mb/s:
- 0 8 byte length in the data field
- Standard and extended data and remote
frames
Receive buffers, masks and filters:
- Two receive buffers with prioritized message
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storage
- Six 29-bit filters
- Two 29-bit masks
Data byte filtering on the first two data bytes
(applies to standard data frames)
Three transmit buffers with prioritization and abort
features
High-speed SPI Interface (10 MHz):
- SPI modes 0,0 and 1,1
One-shot mode ensures message transmission is
attempted only one time
Clock out pin with programmable prescaler:
- Can be used as a clock source for other
device(s)
Start-of-Frame (SOF) signal is available for
monitoring the SOF signal:
- Can be used for time-slot-based protocols
and/or bus diagnostics to detect early bus
degradation
Interrupt output pin with selectable enables
Buffer Full output pins configurable as:
- Interrupt output for each receive buffer
- General purpose output
Request-to-Send (RTS) input pins individually
configurable as:
- Control pins to request transmission for each
transmit buffer
- General purpose inputs
Low-power CMOS technology:
- Operates from 2.7V 5.5V
- 5 mA active current (typical)
- 1 A standby current (typical) (Sleep mode)
Temperature ranges supported:
- Industrial (I): -40C to +85C
- Extended (E): -40C to +125C

4.6.3 DEVICE OVERVIEW

The MCP2515 is a stand-alone CAN controller developed to simplify applications that require
interfacing with a CAN bus. A simple block diagram of the MCP2515 is shown in Figure 1-1. The
device consists of three main blocks:
1. The CAN module, which includes the CAN
protocol engine, masks, filters, transmit and
receive buffers.
2. The control logic and registers that are used to
configure the device and its operation.
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3. The SPI protocol block.

MCP 2551:

4.6.4 DEVICE OVERVIEW

The MCP2551 is a high-speed CAN, fault-tolerant device that serves as the interface between a
CAN
protocol controller and the physical bus. The MCP2551 provides differential transmit and receive
capability for the CAN protocol controller and is fully compatible with the ISO-11898 standard,
including 24V requirements. It will operate at speeds of up to 1 Mb/s. Typically, each node in a
CAN system must have a device to convert the digital signals generated by a CAN controller to
signals suitable for transmission over the bus cabling (differential output). It also provides a buffer
between the CAN controller and the high-voltage spikes that can be generated on the CAN bus by
outside sources (EMI, ESD, electrical transients, etc.).

4.6.5 PIN DIAGRAM

Figure 8 Pin diagram of MCP 2551

4.6.6 FEATURES
Supports 1 Mb/s operation
Implements ISO-11898 standard physical layer
requirements
Suitable for 12V and 24V systems
Externally-controlled slope for reduced RFI
emissions
Detection of ground fault (permanent dominant)
on TXD input
Power-on reset and voltage brown-out protection
An unpowered node or brown-out event will not
disturb the CAN bus
Low current standby operation
Protection against damage due to short-circuit
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conditions (positive or negative battery voltage)

Protection against high-voltage transients
Automatic thermal shutdown protection
Up to 112 nodes can be connected
High noise immunity due to differential bus
implementation
Temperature ranges:
- Industrial (I): -40C to +85C
- Extended (E): -40C to +125C

4.7 APPLICATIONS
Used as a Warning System to avoid Collision in National Highways.
Used by Police to Track the speed of the approaching vehicles.
Used to detect an object in Extreme conditions like Fog and misty areas.
Can be implemented in Robotic Applications.
Can be used in large vehicles like Trucks and buses.
Can be implemented in Aircraft and aerospace electronics.
Can be used in Passenger and cargo trains.
Can be implemented in Maritime electronics.

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5. CONCLUSION
CAN is ideally suited in applications requiring a large number of short messages with high
reliability in
rugged operating environments. Because CAN is message based and not address based, it is
especially
well suited when data is needed by more than one location and system-wide data consistency is
mandatory.
Fault confinement is also a major benefit of CAN. Faulty nodes are automatically dropped from
the bus,
which prevents any single node from bringing a network down, and ensures that bandwidth is
always
available for critical message transmission. This error containment also allows nodes to be added
to a bus
while the system is in operation, otherwise known as hot-plugging.
The many features of the TI CAN transceivers make them ideally suited for the many rugged
applications
to which the CAN protocol is being adapted. Among the applications finding solutions with CAN
are
automobiles, trucks, motorcycles, snowmobiles trains, buses, airplanes, agriculture, construction,
mining,
and marine vehicles.

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