DLC MCQ

Digital signal processing
ObjectiveTypeQuestions
_____________________________________________________________________________________________________
UNIT : I
NUMBER SYSTEMS & DIGITAL LOGIC CIRCUITS
A.
B.
C.
D.
1.To guarantee correction of up to t errors in all cases, the minimum Hamming distance in a block code
must be
d min = 2s -1
d min = s + 1
d min= s-1
d min == 2t+ 1
2. Which of the examples below expresses the commutative law of multiplication?
A.A + B = B + A
B. A B = B + A
C. A (B C) = (A B) C
D.A B = B A
The Boolean expression
A.NAND
C. AND
is logically equivalent to what single gate?

B. NOR
D.OR
4. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is
referred to as:
A.a Karnaugh map
B. DeMorgan's second theorem
C. the commutative law of addition
D.the associative law of multiplication
5. The systematic reduction of logic circuits is accomplished by:
A.symbolic reduction
B. TTL logic
C. using Boolean algebra
D.using a truth table
6. Logically, the output of a NOR gate would have the same Boolean expression as a(n):
A.NAND gate immediately followed by an INVERTER
B. OR gate immediately followed by an INVERTER
C. AND gate immediately followed by an INVERTER
D.NOR gate immediately followed by an INVERTER
Dhanalakshmi College of Engineering
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7. Which of the examples below expresses the distributive law of Boolean algebra?
A.A (B C) = (A B) + C
B. A + (B + C) = (A B) + (A C)
C. A (B + C) = (A B) + (A C)
D.(A + B) + C = A + (B + C)
8. Which output expression might indicate a product-of-sums circuit construction?
A.
B.
C.
D.
9. One of DeMorgan's theorems states that

. Simply stated, this means that logically there is
no difference between:
A.a NAND gate and an AND gate with a bubbled output
B. a NOR gate and an AND gate with a bubbled output
C. a NOR gate and a NAND gate with a bubbled output
D.a NAND gate and an OR gate with a bubbled output
10. The commutative law of addition and multiplication indicates that:
A.the way we OR or AND two variables is unimportant because the result is the same
B. we can group variables in an AND or in an OR any way we want
C. an expression can be expanded by multiplying term by term just the same as in ordinary algebra
the factoring of Boolean expressions requires the multiplication of product terms that contain like
D.
variables
11. Which of the following expressions is in the sum-of-products (SOP) form?
A.Y = (A + B)(C + D)
B. Y = AB(CD)
C.
D.
12.
What is the equivalent of (10110011100011110000)2 n base 32?
A. 11 9 23 31
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B. 22 14 7 16
C. 11 9 7 16
D. 11 14 23 16
13. A computer with a 32-bit word size uses 2's complement to represent numbers. The range of
integers that can be represented by this computer is
a)
- 232 to 232
b) -232 to 231
c) -231 to 231-1
d) 232 to 231
14. The decimal number 80 can be represented in BCD code as
A.
1000 0001
B.
0101 0000
C.
0010 0001
D.
1000 0000
224174
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15. If (12A7C )16 = (X)8 then value of X is
a)
224174
425174
b) 17325
c) 225174
16. The Gray code for decimal number 6 is equivalent to
(A) 1100 (B) 1001

(C) 0101 (D) 0110
Ans: C
17. The digital logic family which has minimum power dissipation is
(A) TTL (B) RTL
(C) DTL (D) CMOS
Ans: D
18. Which of the following is the fastest logic
(A) TTL (B) ECL

(C) CMOS (D) LSI
Ans: B
19. The digital logic family which has the lowest propagation delay time is
(A) ECL (B) TTL

(C) CMOS (D) PMOS
Ans: A
20. The most widely used bipolar technology for digital ICs is
a) DTL
b) TTL
c) ECL
D) CMOS
21. Which of the following is the fastest logic family?
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a) DTL
b) TTL
c) ECL
D) CMOS
22. The recommended fan out for TTL is
a) 10
b)15
c) 20
d) 25
23. Which of the following has least propagation delay?
a) DTL
b) TTL
c) ECL
D) CMOS
24. The logic type used in CMOS is
a. +ve AND/NAND
b. +ve NOR/NAND
c. +ve OR
d. +ve AND
25.
If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each transistor in the circuit?
A.
Q1-ON, Q2-OFF, Q3-ON, Q4-OFF
B.
Q1-ON, Q2-ON, Q3-OFF, Q4-OFF
C.
Q1-OFF, Q2-OFF, Q3-ON, Q4-ON
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D.
Q1-OFF, Q2-ON, Q3-OFF, Q4-ON
26. How many gates would be required to implement the following Boolean expression before
simplification? XY + X(X + Z) + Y(X + Z)
A.
B.
C.
D.
27.
Which Boolean algebra property allows us to group operands in an expression in any order without
affecting the results of the operation [for example, A + B = B + A]?
A.
associative
B.
commutative
C.
Boolean
D.
distributive
28. Applying DeMorgan's theorem to the expression
, we get ________
A.
B.
C.
D.
29.
The NAND or NOR gates are referred to as "universal" gates because either:
A.
can be found in almost all digital circuits
B.
can be used to build all the other types of gates
C.
are used in all countries of the world
D.
were the first gates to be integrated
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30.
For the SOP expression
, how many 0s are in the truth table's output column?
A.
zero
B.
C.
D.
UNIT II COMBINATIONAL
CIRCUITS
1. How many inputs are required for a 1-of-10 BCD decoder?

A.4
B. 8
C. 10
D.1
2. Most demultiplexers facilitate which of the following?
A.decimal to hexadecimal
B. single input, multiple outputs
C. ac to dc
D.odd parity to even parity
3. One application of a digital multiplexer is to facilitate:
A.code conversion
B. parity checking
C. parallel-to-serial data conversion
D.data generation
4.
5. A multiplexed display:
A.accepts data inputs from one line and passes this data to multiple output lines
B. uses one display to present two or more pieces of information
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C. accepts data inputs from multiple lines and passes this data to multiple output lines
D.accepts data inputs from several lines and multiplexes this input data to four BCD lines
6. When two or more inputs are active simultaneously, the process is called:
A.first-in, first-out processing
B. priority encoding
C. ripple blanking
D.priority decoding
7. Which type of decoder will select one of sixteen outputs, depending on the 4-bit binary input value?
A.hexadecimal
B. dual octal outputs
C. binary-to-hexadecimal
D.hexadecimal-to-binary
8. A magnitude comparator determines:
A.A B and if A B or A >> B
B. A B and if A > B or A B or A B
9. A circuit that responds to a specific set of signals to produce a related digital signal output is called a(n):
A.BCD matrix
B. display driver
C. encoder
D.decoder
10. Which digital system translates coded characters into a more intelligible form?
A.encoder
B. display
C. counter
D.decoder
11. A basic multiplexer principle can be demonstrated through the use of a:
A.single-pole relay
B. DPDT switch
C. rotary switch
D.linear stepper
12. In a BCD-to-seven-segment converter, why must a code converter be utilized?
A.No conversion is necessary.
B. to convert the 4-bit BCD into gray code
C. to convert the 4-bit BCD into 10-bit code
D.to convert the 4-bit BCD into 7-bit code
SEQUENTIAL LOGIC CIRCUIT
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1. A ripple counter's speed is limited by the propagation delay of:

A.each flip-flop
B. all flip-flops and gates
C. the flip-flops only with gates
D.only circuit gates
2. To operate correctly, starting a ring counter requires:
A.clearing all the flip-flops
B. presetting one flip-flop and clearing all the others
C. clearing one flip-flop and presetting all the others
D.presetting all the flip-flops
3. What type of register would shift a complete binary number in one bit at a time and shift all the stored
bits out one bit at a time?

A.PIPO
B. SISO
C. SIPO
D.PISO
4. Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters
because the:
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage
5. One of the major drawbacks to the use of asynchronous counters is that:

A. low-frequency applications are limited because of internal propagation delays
B. high-frequency applications are limited because of internal propagation delays
C.
Asynchronous counters do not have major drawbacks and are suitable for use in high- and low-frequency
counting applications.
D. Asynchronous counters do not have propagation delays, which limits their use in high-frequency applications.
6. Which type of device may be used to interface a parallel data format with external equipment's serial
format?
A. key matrix
B. UART
C. memory chip
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D. serial-in, parallel-out
When the output of a tri-state shift register is disabled, the output level is placed in a:
A. float state
B. LOW state
C. high impedance state
D. float state and a high impedance state
8. A comparison between ring and johnson counters indicates that:

A. a ring counter has fewer flip-flops but requires more decoding circuitry
B. a ring counter has an inverted feedback path
C. a johnson counter has more flip-flops but less decoding circuitry
D. a johnson counter has an inverted feedback path
9. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
A. shift register sequencer
B. clock
C. johnson
D. binary
10. What is meant by parallel-loading the register?

A. Shifting the data in all flip-flops simultaneously
B. Loading data in two of the flip-flops
C. Loading data in all four flip-flops at the same time
D. Momentarily disabling the synchronous SET and RESET inputs
11. What is a shift register that will accept a parallel input and can shift data left or right called?
A. tri-state
B. end around
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C. bidirectional universal
D. conversion
12. What happens to the parallel output word in an asynchronous binary down counter whenever a clock
pulse occurs?
A. The output word decreases by 1.
B. The output word decreases by 2.
C. The output word increases by 1.
D. The output word increases by 2.
13. Mod-6 and mod-12 counters are most commonly used in:
A. frequency counters
B. multiplexed displays
C. digital clocks
D. power consumption meters
FLIP FLOPS
1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input
clock frequency of 20.48 MHz.

A. 10.24 kHz
B. 5 kHz
C. 30.24 kHz
D. 15 kHz
2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

A. The logic level at the D input is transferred to Q on NGT of CLK.
B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
C. The Q output is ALWAYS identical to the D input when CLK = PGT.
D. The Q output is ALWAYS identical to the D input.
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3. Propagation delay time, tPLH, is measured from the ________.

A. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output
B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output
C. preset input to the LOW-to-HIGH transition of the output
D. clear input to the HIGH-to-LOW transition of the output
4. How is a J-K flip-flop made to toggle?

A. J = 0, K = 0
B. J = 1, K = 0
C. J = 0, K = 1
D. J = 1, K = 1
5. How many flip-flops are in the 7475 IC?

A.1
C. 4
B. 2
D.8
How many flip-flops are required to produce a divide-by-128 device?

A.1
B. 4
C. 6
D.7
7. Which is not an Altera primitive port identifier?

A.clk
C. clr
B. ena
D.prn
8. The timing network that sets the output frequency of a 555 astable circuit contains ________.
A. three external resistors are used
B. two external resistors and an external capacitor are used
C. an external resistor and two external capacitors are used
D. no external resistor or capacitor is required
9. What is the difference between the enable input of the 7475 and the clock input of the 7474?
A. The 7475 is edge-triggered.
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B. The 7474 is edge-triggered.
10. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called
________.
A. parity error checking
B. ones catching
C. digital discrimination
D. digital filtering
11. What is another name for a one-shot?

A.Monostable
C. Bistable
B. Multivibrator
D.Astable
12. On a master-slave flip-flop, when is the master enabled?

A. when the gate is LOW
B. when the gate is HIGH
C. both of the above
D. neither of the above
13. One example of the use of an S-R flip-flop is as a(n):

A. racer
B. astable oscillator
C. binary storage register
D. transition pulse generator
4. What is the difference between the 7476 and the 74LS76?

A. the 7476 is master-slave, the 74LS76 is master-slave
B. the 7476 is edge-triggered, the 74LS76 is edge-triggered
C. the 7476 is edge-triggered, the 74LS76 is master-slave
D. the 7476 is master-slave, the 74LS76 is edge-triggered
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15. Which of the following is correct for a gated D flip-flop?

A. The output toggles if one of the inputs is held HIGH.
B. Only one of the inputs can be HIGH at a time.
C. The output complement follows the input when enabled.
D. Q output follows the input D when the enable is HIGH.
16. With regard to a D latch, ________.

A. the Q output follows the D input when EN is LOW
B. the Q output is opposite the D input when EN is LOW
C. the Q output follows the D input when EN is HIGH
D. the Q output is HIGH regardless of EN's input state
17. How can the cross-coupled NAND flip-flop be made to have active-HIGH S-R inputs?
A. It can't be done.
B. Invert the Q outputs.
C. Invert the S-R inputs.
18. When is a flip-flop said to be transparent?

A. when the Q output is opposite the input
B. when the Q output follows the input
C. when you can see through the IC packaging
COUNTERS
1. How many flip-flops are required to make a MOD-32 binary counter?

A.3
B. 45
C. 5
D.6
2. Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a
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modulus of 50,000?
A.50,000
B. 65,536
C. 25,536
D.15,536
3. A MOD-16 ripple counter is holding the count 10012. What will the count be after 31 clock pulses?
A.10002
B. 10102
C. 10112
D.11012
4. The terminal count of a modulus-11 binary counter is ________.

A.1010
B. 1000
C. 1001
D.1100
5. List which pins need to be connected together on a 7493 to make a MOD-12 counter.
A. 12 to 1, 11 to 3, 9 to 2
B. 12 to 1, 11 to 3, 12 to 2
C. 12 to 1, 11 to 3, 8 to 2
D. 12 to 1, 11 to 3, 1 to 2
6. How can a digital one-shot be implemented using HDL?

A. By using a resistor and a capacitor
B. By applying the concept of a counter
C. By using a library function
D. By applying a level trigger
7. Integrated-circuit counter chips are used in numerous applications including:

A. timing operations, counting operations, sequencing, and frequency multiplication
B. timing operations, counting operations, sequencing, and frequency division
C. timing operations, decoding operations, sequencing, and frequency multiplication
D. data generation, counting operations, sequencing, and frequency multiplication
8. Synchronous construction reduces the delay time of a counter to the delay of:
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A. all flip-flops and gates

B. all flip-flops and gates after a 3 count
C. a single gate
D. a single flip-flop and a gate
9. Synchronous counters eliminate the delay problems encountered with asynchronous counters because
the:
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D. input clock pulses are applied simultaneously to each stage
10. What is the difference between combinational logic and sequential logic?
A. Combinational circuits are not triggered by timing pulses, sequential circuits are triggered by timing pulses.
B. Combinational and sequential circuits are both triggered by timing pulses.
C. Neither circuit is triggered by timing pulses.
1. How many outputs are on a BCD decoder?

A.4
C. 8
B. 16
D.10
2. In a Gray code, each number is 3 greater than the binary representation of that number.
A.True
B.False
3. Use the weighting factors to convert the following BCD numbers to binary.
0101 0011
0010 0110 1000
A. 01010011 001001101000
B. 11010100 100001100000
C. 110101
100001100
D. 101011
001100001
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4. Which digital system translates coded characters into a more useful form?
A.encoder
B. display
C. counter
D.decoder
5. From the following list of input conditions, determine the state of the five output leads on a 74148 octal-
to-binary encoder.
I0 = 1 I3 = 1 I6 = 1
I1 = 1 I4 = 0 I7 = 1
I2 = 1 I5 = 1 EI = 0
A. GS = L, A0 = L, A1 = L, A2 = H, EO = H
B. GS = L, A0 = H, A1 = L, A2 = L, EO = H
C. GS = L, A0 = L, A1 = H, A2 = L, EO = H
D. GS = L, A0 = H, A1 = H, A2 = L, EO = H
6. What is the function of an enable input on a multiplexer chip?

A. to apply Vcc
B. to connect ground
C. to active the entire chip
D. to active one half of the chip
7. The expansion inputs to a comparator are used for expansion to a(n):

A. 4-bit system
B. 8-bit system
C. BCD system
D. counter system
8. What do the mathematical symbols A B mean?

A. A B means A is less than B.
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B. A > B means A is less than B. A B means A is greater than B.
9. A basic multiplexer principle can be demonstrated through the use of a:

A. single-pole relay
B. DPDT switch
C. rotary switch
D. linear stepper
10. How many inputs will a decimal-to-BCD encoder have?

A.4
B. 8
C. 10
D.16
Answer : b
2. The output of anti causal LTI system is
n
a) y(n)=
h(k)x(n
k)
b) y (n)=
h(k)x(n
k)
K 0
K 0
c) y(n)=
h(k)x(n
k)
Answer : c
4.
(n-k) * x(n-k)is equal to
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a) x(n-2k)
b) x(n-k)
c) x(k)
d) none
d) y (n)=
h(k)x(n
k)
Answer : b
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5. Given x(n) they(n) =x(2n 6) is

a) x(n)is Compressed by2 and shifted by 6
b) x(n)is Compressed by2 and shifted by3
c) x(n)is Expanded by2and shifted by3
d) none
Answer : c
6. Decimation by a factor N is equivalent to
a) Sampling x(t) at intervals ts/ N
c) N fold increase in sampling rate
Answer : b
b) Sampling x(t) at intervals tsN

d) none
7. In fractional delay, x(n-M/N), specify the order of operation.

a)Decimation by N, shift by M, Interpolation by N
b)Shift by M, Decimation by N and Interpolation by N
c)Interpolation by N, Shift by M and Decimation byN
d)All are correct
Answer : c
8. Given g(n) ={1,2,3}, find x(n)=g(n / 2), usinglinear interpolation
a) 1, 0, 2, 0, 3
b) 1,1, 2, 2, 3, 3
c) 1, 3/2, 2, 5/2, 3
d) none
Answer : a
9. The h(n) is periodic with period N, x(n)is non periodic with M samples, the output y(n)is
a) Periodic with period N
b) Periodic with period N+M
c) Periodic with period M
d) none
Answer : a
10.Determine the noncausal system
a)
c)
b)
d)
Answer : a
11. Two signals x1(n)={1,2,3,4} and x2(n)={4,3,2,1}, then x1(n)+x2(n)=
a) {2,2,2,2}
b) {3,2,4,1}
c){1,1,1,1}
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d) {5,5,5,5}
Answer : d
12. Identify the dynamic system

a)y(n)= ax2(n)
b) y(n)= ax(n)
c)y(n)= ax2(n) +x(n)
d) y(n)= x(n)+x(n-1)
Answer : c
13.
Determine the period of the signal x[n] = u[n] (Step function)

(a) 1
(b)
(c) Non periodic
(d) Zero
Answer : c
14.
Energy of signal A
(a) A2 / 2
(b) 0
(c) A2 / 4
(d) A2
is :
Answer : d
15.Energy of unit step sequence is
(a)
(b) 1
(c)
(d) 0
Answer : a
16.Which of the following is true?
(a)
is an odd function
(b) Step function is periodic
(c) Time scaling can be applied to step function and effect can be seen
(d) None
Answer : d
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17.Shifting in time of certain sequence is equivalent to

(a) Change in Magnitude spectrum
(b) Change in phase spectrum
(c) Change in both
(d) Change in phase spectrum keeping magnitude spectrum same
Answer : d
18.If a function f(t)u(t) is shifted to the right side by t0, then the function can be expressed as
(a) f (t - t0 )u(t)
(b) f(t)u (t - t0 )
(c) f (t - t0 )u(t - t0)
(d) f (t + t0 )u(t)
Answer : c
19.
(a)
(b)
(c)
(d)
Causal and stable

Causal but not stable
Not causal but stable
Neither causal nor stable
Answer : c
20.When the output of signal is finite for any finite input then the system is called_______ stable.
(a) Bounded input
(b) Bounded output
(c) Bounded input and Bounded output
(d) None
Answer : c
21.A signal with large magnitude and short duration is
(a) Step signal
(b) Ramp signal
(c) Impulse signal
(d) Parabolic
Answer : c
22.What is period of the signal x [n] = u [n 1] u [n 7]
(a) 1
(b) 7
(c) Not periodic
(d) 6
Answer : c
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23.Unit step function can be obtained from unit ramp function by ___________
(a) Integrating
(b) Adding
(c) Multiplying
(d) Differentiating
Answer : d
24.Unit ramp function is a ____________ of Parabolic function
(a) Integral
(b) Multiple
(c) Derivative
(d) Factor
Answer : c
25.The signal x(t) = e-2tu(t) is
(a) Power signal with P = W
(b) Energy signal with E = J
(c) Power signal with P = 0
(d) Energy signal with E = 0
Answer : b
26.Which of the following impulse response is non causal?
(a) Anu[n-2]
(b) An-2u[n]
(c) An+2u[n]
(d) Anu[n+2]
Answer : d
27.The value of
(a) 1/3
(b) 3
(c)
(d) 1
is
Answer : a
28.Which of the following is stable system
(a) y(t) = t x(t)
(b) y(t) =t2 x(t)
(c) y(t) =
(d) y(t) =
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Answer : d
29.Which of the following is not a static system
(a) y (t) = x (t2)
(b) y (t) = x2 (t)
(c) y (t) = t x(t)
(d) y (t) = e x(t)
Answer : a
30.What is the event component of
(a)
(b)
(c)
(d)
Answer : a
31.The period of signal x(t) = 4sin7t is

(a)
(b)
(c) 2
(d) 7
Answer : a
32.Condition for energy signal:
(a) E is finite, P is zero
(b) E is infinite, P is finite
(c) E is infinite, P is zero
(d) E is zero, P is finite
Answer : a
33.Determine the frequency response of ( )
(a)
(b)
(c)
(d)
Answer : b
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34.Let x(n) be a signal with x(n) = 0 for n < -2, n > 4. Then the signal x(-n + 2) is guaranteed to be zero in the
region
(a) n < 1 and n >7
(b) n <2 and n > -4
(c) n < -2 and n > 4
(d) n < -6 and n > 0
Answer : c
35.Which of the following statements are true?

A. An LTI system is always stable
B. An LTI system is stable only if the integer of its impulse response is finite
C. In a system, if the input is bounded then output is always bounded.
D. In a system even if the input is unbounded the output can be bounded.
(a) B only
(b) B and D only
(c) C only
(d) A and D only
Answer : b
36.Even part of function x[n] = u[n] u[n-4] is
(a) {u[n+3] u[n-4] +
(b) {u[n] + u[n-4] -
}
}
(c) {1 - u[n-4] + 4u[-n-4] +
(d) All the above

Answer : a
37.The system described by the equation y[n] = x[n]cos
(a) Time invariant and causal
(b) Time variant and non-causal
(c) Time variant and causal
(d) Time invariant and non- causal
is:
Answer : c
38.Find whether the given signal is periodic:
x1(t) = 2sint + 3cos3t
x2(t) = 2cos5t + 5cos7t
(a) x1(t) is periodic, x2(t) is not periodic
(b) x1(t) is not periodic, x2(t) is periodic
(c) x1(t) and x2(t) is both periodic
(d) x1(t) and x2(t) is both not periodic
IV SEM EEE
Answer : c
39.The response of a LTI system to a unit step input is impulse
will be:
(a) n
(b) nu[n]
(c) u[n]
(d) n
. The system response to a ramp nu(n)
Answer : c
40.Impulse response of certain system is given as h(t) =
(a)
(b)
(c)
(d)
| |
, then the step response is given by
Answer : c
41.Range of values of a and b for which the linear time invariant system with impulse response h[n] =
{
is stable.
(a)
(b)
(c)
(d)
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Answer : d
42.Find whether the given signal is causal and/or stable h[n] = an u[n]
(a) Causal and not stable
(b) Causal and stable
(c) System is causal, stability depends on a
(d) System is causal and stability is independent of a
Answer : c
IV SEM EEE

UNIT : II
DISCRETE TIME SYSTEM ANALYSIS
1. If z-transform of x(n) is X(z), then z-transform of x(-n) is

(a) X(z)
(b) X(-z)
(c) X(z-1)
(d) X(z-1)
Answer : d
2. The Fourier transform of a finite energy discrete time signal, x(n) is defined as
(a)
(b)
(c)
(d)
Answer : a
3. Region of convergence of a causal LTI system
(a) is the entire s-plane
(b) is the right-half of s-plane
(c) is the left-half of s-plane
(d) does not exist
Answer : b
4. The Z transform of (n m) is
(a)
(b)
(c)
(d)
Answer : b
5. The z-transform converts convolution of time-signals to

(a) addition
(b) subtraction
(c) multiplication
(d) division
IV SEM EEE
Answer : c
6. The ROC of x(n) contains
(a) poles
(b) zeros
(c) no poles
(d) no zeros
Answer : c
7. The ROC of the sequence x(n) = u(-n) is
(a) | |
(b) | |
(c)
(d)
| |
Answer : b
8. The z transform is a
(a) finite series
(b) infinite power series
(c) geometric series
(d) both a and c
Answer : b
9. The ROC of the signal x(n) = an for -5 n 5 is
(a) entire z plane
(b) entire z plane except z = 0 and z =
(c) entire z = plane except z = 0
(d) entire z = plane except z =
Answer : b
10. If X(z) has a single pole on the unit circle, on negative real axis then, x(n) is
(a) signed constant sequence
(b) signed decaying sequence
IV SEM EEE
(c) signed growing sequence

(d) constance sequence
Answer : a
11. An LTI system with impulse response, h(n) = (-a)n u(n) and a -1 will be
(a) stable system
(b) unstable system
(c) anticausal system
(d) neither stable nor causal
Answer : b
12. For a stable LTI discrete time system poles and unit circle should lie
(a) outside unit circle, included in ROC
(b) inside unit circle, outside of ROC
(c) inside unit circle, included in ROC
(d) outside unit circle, outside of ROC
Answer : c
13. The inverse z transform of X(z) can be defined as
(a)
(b)
(c)
(d)
Answer : c
14. The z transform of a ramp function x(n) = n u(n) is

(a)
| |
(b)
| |
(c)
| |
(d)
| |
IV SEM EEE
(e) Answer : a
15. If all the poles of the system function H(z) have magnitude smaller than 1, then the system will be
(a) stable
(b) unstable
(c) BIBO stable
(d) a and c
Answer : a
16. The z-transform of a-n u(- n -1) is
(a)
(b)
(c)
(d)
Answer : a
17. If x(n) = { 0.5, -0.25, 1}, then z-transform of the signal is
(a)
(b)
(c)
(d)
Answer : c
18. The z-transform of x(n) = sin(n/2) u(n) is
(a)
(b)
(c)
(d)
Answer : d
IV SEM EEE
19. The system function H(z) = (z3-2z2+z) / (z2+0.25z+0.125) is

(a) causal
(b) non-causal
(c) unstable but causal
(d) can not be defined
Answer : b
20. The Fourier transform of x(n) = 1 for all n is
(a)
(b)
(c)
(d)
Answer : a
21. If F{x(n)} = X(ej), then F{x(n-3)}will be
Answer : c
22. If h(n) is real, then magnitude of H(ej) and phase of H(ej) is

(a) symmetric, antisymmetric
(b) antisymmetric, symmetric
(c) symmetric, symmetric
(d) antisymmetic, antisymmetric
Answer : a
.
IV SEM EEE
23. The discrete time Fourier transform of the signal, x(n) = 0.5n-1 u(n-1) is
Answer : a
24. The Fourier transform of, x(n) = (0.8)n ; n = 0, 1, 2, is
Answer : a
25. The region of convergence of a causal finite duration discrete-time signal is

(a) the entire z-plane except z = 0
(b) the entire z-plane except z =
(c) the entire z-plane
(d) a strip in z-plane enclosing j axis
Answer : a
26. The inverse discrete time Fourier transform of X(ej) is defined as
IV SEM EEE
Answer : c
27. If X(ej) = e-j for , then the discrete time signal x(n) is
Answer : c
28. A first order LTI system will behave as a

(a) Low pass filter
(b) Low pass or high pass filter
(c) High pass filter
(d) Band pass filter
Answer : b
29. A first order LTI system will behave as a

(a) Low pass filter
(b) Low pass or high pass filter
(c) High pass filter
(d) Band pass filter
Answer : d
30. The inverse z-transform of X(z) = ea/z ,z> 0 is,
IV SEM EEE
Answer : b
31. ROC of a causal signal is the exterior of a circle of some radius r. True or False
Answer : True
32. ROC of a anti causal signal is the exterior of a circle of some radius r. True or False
Answer : False
33. ROC of a two sided finite duration frequency is entire Z-plane. True or False
Answer : True
34. A linear time invariant system with a system function H (Z) is BIBO stable if and only if the ROC for
H (Z) contains unit circle. True or False
Answer : False
IV SEM EEE
UNIT III - DISCRETE FOURIER TRANSFORM & COMPUTATION

1.
The inverse Discrete Fourier Transform

(a) converts from the frequency domain to the time domain
(b) converts from the time domain to the frequency domain
(c) converts from the phasor domain to the magnitude domain
(d) is used to make real-time spectrum analysers
Answer : a
2.
How many complex multiplications are required by DFT

(a)
(b)
(c)
(d)
Answer : d
3.
How many complex additions are required by DFT

(a)
(b)
(c)
(d)
Answer : b
4.
Number of complex additions required to calculate Radix 2 FFT is

(a)
(b)
(c)
(d)
Answer : c
5.
How many methods are available to perform FFT

(a) 1
(b) 2
(c) 3
(d) 4
Answer : b
6.
Number of complex multiplication required to calculate Radix-2 FFT is..

(a)
(b)
IV SEM EEE
(c)
(d)
Answer : b
7.
Which is the following filtering method is used for DFT

(a) IIR
(b) FIR
(c) LPF
(d) Overlap-add method & Overlap-slave method
Answer : d
8.
Appending zeros to a sequence in order to increase the size or length of the sequence is called
Ans :zero padding
9.
In DFT radix-2 FFT is the name of domain to be decimated

Ans :DIT and DIF
10. In N-point DFT using radix 2 FFT, the decimation is performed times.
(a)
(b)
(c)
(d)
Answer : b
11. What is the speed improvement factor in calculating 64 point DFT of a sequence using direct
computation and FFT algorithm
(a) 40.33
(b) 30.33
(c) 10.33
(d) 21.33
Answer : a
12. The linear convolution of two sequences x(n)={1,2} and h(n)={3,4}is

(a) {3, 10}
(b) {10, 3, 8}
(c) {3, 10, 8}
(d) {3, 8, 10}
Answer : c
IV SEM EEE
13. Advantage of FFT algorithm

(a) Less Bandwidth required
(b) Less number of computations
(c) Less power required
(d) All
Answer : b
14. The phase spectrum of the periodic sequence is
(a) even
(b) odd
(c) real
(d) none
Answer : b
15. The DFT of a sequence is_______function of
(a) continuous
(b) discrete
(c) depends on sequence
(d) none
Answer : b
16. If x(n) is even, then X(K) is________
(a) real
(b) complex
(c) imaginary
(d) none
Answer : a
17. What is the advantage of FFT over DFT
(a) Symmetry property
(b) Differentiation property
(c) Integration property
(d) Linearity property
Answer : a
18. The Fourier transform of x(n)*h(n) is equal to
Ans : X(k) + H(k)
19. In 8-point DFT by radix 2 FFT, there are stages of computations with
butterflies per stage.
(a) 3, 2
(b) 4, 5
(c) 1, 2
IV SEM EEE
(d) 2, 2
Answer : a
20. If X(k) is DFT of a sequence x(n), then DFT of imaginary part of x(n) is
Ans : real
21. The DFT of sequence can be evaluated as
Ans : Spectrum
22. Compute the DFT of the four point sequence x(n) = (0 1 2 3)

(a) 6, -2+2j, -2, -2-2j
(b) 6,-2-2j,-2,2-2j
(c) 6,-2+2j,-2,-2+2j
(d) 6,-2+2j,-0,-2-2j
Answer : a
23. The linear convolution of x(n) ={1,2,3} and h(n) ={3,2,1}
(a) {3, 8, 14, 8, 3}
(b) {5, 8, 3, 7, 20}
(c) {8, 3, 8, 14, 3}
(d) {7, 9, 2, 6, 1}
Answer : a
24. If x(n) ={1,1,1,1} ,then X(k) using DIT FFT is
(a) {4,0,0,0}
(b) {1,1,1,1}
(c) {4,0,4,0}
(d) {4,1,0,1}
Answer : a
25. If x(n) is of length 4 and h(n) is of length 4 then length of x(n)* h(n) is _____
(a) 7
(b) 3
(c) 4
(d) 8
Answer : a
IV SEM EEE
26. If a system is relaxed then y[-1] and y[-2] are

(a) y[-1]=0, y[-2]=1
(b) y[-1]=1=y[-2]
(c) y[-1]=0, y[-2]=0
(d) y[-1]=1, y[-2]=0
Answer : c
27. x[n] X[k] then x*[n] _______
(a) X[K]
(b) X*[-k]
(c) X[k]
(d) X*[k]
Answer : b
28. Given that W e

(a) 0
(b) 1
(c) 1
(d) e
2
i
, where N 3 . Then F W N can be computed as F
Answer : b
29. Given that W e
(a) 0
(b) 1
(c) 1
(d) e
2
i
, where N 3 . F W
N
2
can be computed as F
Answer : c
7
30. If the forcing function F (t ) is given as F (t ) 10 sin(2nt ) . Then, to avoid aliasing phenomenon,
n 0
the minimum number of sample data points N m in should be

(a) 8
(b) 16
(c) 24
(d) 32
Answer : b
IV SEM EEE
UNIT IV DESIGN OF DIGITAL FILTERS

FIR FILTER DESIGN
1. A Blackman window can eliminate ripple in FIR filters. The tradeoff is
(a) larger transition bandwidth
(b) smaller transition bandwidth
(c) a non-linear phase response
(d) possible instability
Answer : a
2. Two digital filters can be operated in cascade. Or, the same effect can be achieved by
(a) adding their coefficients
(b) subtracting their coefficients
(c) convolving their coefficients
(d) averaging their coefficients and then using a Blackman window
Answer : c
3. A DSP convolves each discrete sample with four coefficients and they are all equal to 0.25. This must
be an
(a) IIR filter
(b) FIR filter
(c) RRR filter
(d) All of the above
Answer : b
4. Coefficient symmetry is important in FIR filters because it provides
(a) a smaller transition bandwidth
(b) less passband ripple
(c) less stopband ripple
(d) a linear phase response
Answer : d
Answer : c
6. The impulse response of a symmetrical FIR filter is
(a) h(n)=h(N-1)/2
(b) h(n)=h(N-1-n)
(c) h(n)=h(-n)/2
(d) h(n)=h(n)/2
IV SEM EEE
Answer : b
7. The Bandwidth of a Hanning window is
(a) 2/N
(b) 6/N
(c) 12/N
(d) 8/N
Answer : d
8. The Bandwidth of a Hamming window is
(a) 2/N
(b) 6/N
(c) 12/N
(d) 8/N
Answer : d
9. The Bandwidth of a Blackman window is
(a) 2/N
(b) 6/N
(c) 12/N
(d) 8/N
Answer : c
11. Which of the following is used to alter FIR filter coefficients so they smoothly approach zero
at both ends?
(a) rectangular window
(b) Blackman window
(c) Laplace window
(d) Hilbert window
Answer : b
12. The basic process that's going on inside a DSP chip is
(a) quantization
(b) MAC
(c) logarithmic transformation
(d) vector calculations
Answer : b
13. For the rectangular window function, the transition width of the main lobe is approximately
(here M is the length of the filter)
(a) 4*pi*M
(b) pi/4M
(c) pi*M/4
(d) 4*pi/M
IV SEM EEE
Answer : d
14. For the rectangular window function, the first sidelobe will be __________ dB down the
peak of the main lobe.
(a) 12 dB
(b) 11 dB
(c) 13 dB
(d) 14 dB
Answer : c
15. The desired frequency response of a LPF is
(a)
(b)
(c)
(d)
Answer : b
16. The peak side lobe of Hamming window is
(a) -30db
(b) -43db
(c) -10db
(d) -32db
Answer : b
17. The peak side lobe of rectangular window is
(a)-30db
(b) -23db
(c)-13db
(d) -10db
Answer : c
18. The peak side lobe of Bartlett window is
(a) -30db
(b) -27db
(c) -10db
(d) -22db
Answer : b
IV SEM EEE
19. The peak side lobe of Hanning window is

(a) -30db
(b) -27db
(c) -10db
(d) -32db
Answer : d
21. A quantizer operates at a sampling frequency of 16 kHz. What is its Nyquist limit?
(a) 4 kHz
(b) 8 kHz
(c) 16 kHz
(d) 32 kHz
Answer : b
22. If a linear phase filter has a phase response of 40 degrees at 200 Hz, what will its phase
response be at a frequency of 400 Hz (assuming that both frequencies are in the passband of
the filter)?
(a) 35 degrees
(b) 40 degrees
(c) 45 degrees
(d) 80 degrees
Answer : d
23. This windowed sinc FIR filter has ripple caused by
(a)
(b)
(c)
(d)
non-symmetrical coefficients
Gibb's phenomenon
too few taps
a defective accumulator
Answer : b
24. An FIR system is described by the system function

The system is
(a) Maximum phase
(b) Minimum phase
(c) Mixed phase
(d) Zero phase
IV SEM EEE
Answer : d
25. If N=53 and c=0.3 radians. Find
(a) 12
(b) 26
(c) 20
(d) 40
Answer : b
26. If h (n) = (n).Find the H (ej)
(a)1
(b) 4
(c) 6
(d) 2
Answer : a
5
27. If h(n) =
0
0 n N 1
elsewhere
the frequency response is
5 e jN
(a)
j
5e
5 e jN
(b)
j
5e
5 e jN
(c)
j
5e
5 e jN
(d)
j
5e
Answer : a
1
28. If h(n) =
0
0 n N
elsewhere
the frequency response is
1 e jN
(a)
j
1 e
1 e jN
(b)
j
1 e
1 e jN
(c)
j
1 e
IV SEM EEE
1 e jN
(d)
j
1 e
Answer : a
28. If h (n) = (n).Find the H (ej)
(a) 1
(b) 4
(c) 6
(d) 2
Answer : a
IIR FILTER DESIGN
1.
The magnitude response of the following filter decreases monotonically as frequency increases
(a)
(b)
(c)
(d)
Butterworth Filter
Chebyshev type 1
Chebyshev type 2
FIR Filter
Answer : a
2.
IIR filters
(a) use feedback
(b) are sometimes called recursive filters
(c) can oscillate if not properly designed
(d) all of the above
Answer : d
3.
The transition band is more in

(a) Butterworth Filter
(b) Chebyshev type - 1
(c) Chebyshev type - 2
(d) FIR Filter
Answer : a
4.
In the design a IIR Digital filter for the conversion of analog filter in to Digital domain the desirable
property is
(a) The axis in the s - plane should map outside the unit circle in the z - Plane
(b) The Left Half Plane(LHP) of the s - plane should map in to the unit circle in the Z - Plane
(c) The Left Half Plane(LHP) of the s-plane should map outside the unit circle in the z-Plane
(d) The Right Half Plane(RHP) of the s-plane should map in to the unit circle in the Z Plane
Answer : b
5.
The IIR filter design method that overcomes the limitation of applicability to only Low pass filter and a
limited class of band pass filters is
(a) Approximation of derivatives
IV SEM EEE
(b) Impulse Invariance

(c) Bilinear Transformation
(d) Frequency sampling
Answer : c
6.
Curve A is the
(a)
(b)
(c)
(d)
phase response of a low pass filter

amplitude response of a low pass filter
both of the above
none of the above
Answer : b
7.
Point C is called
(a)
(b)
(c)
(d)
a phase reversal
the half-power point
a phase discontinuity
a phase wrap
Answer : a
8.
Direct form I required less no.of memory elements as compared to Canonic form. [True/False]
ANS: True
9.
The poles of Butterworth filter lies on

(a) sphere
(b) circle
(c) ellipse
(d) parabola
Answer : b
IV SEM EEE
10. In IIR digital filter the present output depends on

(a) Present and previous Inputs only
(b) Present input and previous outputs only
(c) Present input only
(d) Present Input, Previous input and output
Answer : d
be a
(a) Low pass filter
(b) High pass filter
(c) Band pass filter
(d) Band stop filter
Answer : a
12. A quantizer operates at a sampling frequency of 16 kHz. What is its Nyquist limit?
(a) 4 kHz
(b) 8kHz
(c) 16kHz
(d) 32kHz
Answer : c
13. This is the impulse response of
(a)
(b)
(c)
(d)
an IIR high pass filter

an FIR band pass filter
an IIR low pass filter
an FIR low pass filter
Answer : c
IV SEM EEE
14. This time graph shows the
(a)
(b)
(c)
(d)
frequency response of an IIR filter

amplitude response of an IIR filter
impulse response of an IIR filter
none of the above
Answer : c
Answer : c
16. In the Impulse Invariance method the mapping from analog frequency to the digital frequency is
(a)
(b)
(c)
(d)
one to one
one to many
many to many
many to one
Answer : d
17. The nonlinear relation between the analog and digital frequencies is called
(a) aliasing
(b) warping
(c) prewarping
(d) anti-aliasing
Answer : b
18. What is the disadvantage of impulse invariant method
(a) Aliasing
(b) one to one mapping
(c) anti aliasing
(d) warping
Answer : a
19. A causal and stable IIR filter has
(a) Linear phase
IV SEM EEE
(b) No Linear phase

(c) Linear amplitude
(d) No Amplitude
Answer : b
20. Which of the IIR Filter design method is anti-aliasing method?

(a) The method of mapping of differentials
(b) Impulse invariant method
(c) Bilinear transformation
(d) Matched Z - transformation technique
Answer : c
21. A filter has the difference equation: y(nt-2T)+x(nT)+x(nT-T). What traditional filter type best describes
this filter?
(a) Integrator
(b) differentiator
(c) subtractor
(d) multiplier
Answer : a
be an
(a) IIR filter
(b) FIR filter
(c) RRR filter
(d) All of the above
Answer : a
23. After point D (as frequency is increasing)
(a)
(b)
(c)
(d)
the phase response is linear

the phase response is non-linear
the stop band is infinite
the Nyquist limit has been exceeded
Answer : b
IV SEM EEE

24.
A DSP convolves each discrete sample with these coefficients: -0.25, -0.25, 1.0, -0.25, and -0.25.
This must be a
(a) Low pass filter
(b) High pass filter
(c) Band pass filter
(d) Band stop filter
Answer : b
25. Neither the Impulse response nor the phase response of the analog filter is Preserved in the digital filter
in the following method
(a) The method of mapping of differentials
(b) Impulse invariant method
(c) Bilinear transformation
(d) Matched Z - transformation technique
Answer : c
26. In the case of IIR filter which of the following is true if the phase distortion is tolerable
(a) More parameters for design
(b) More memory requirement
(c) Lower computational Complexity
(d) Higher computational complexity
Answer : c
27. The analog transfer function of a third order Butterworth filter is defined by
(a) H(s)= 1/s3-2 s2-2s-1
(b) H(s)= 1/s3+2 s2-2s+1
(c) H(s)= 1/s3-2 s2+2s+1
(d) H(s)= 1/s3+2 s2+2s+1
Answer : a
28. The analog transfer function of a fourth order Butterworth filter is defined by
(a) H(s)= 1/ s4+2.613 s3+3.41s2+2.61s+4
(b) H(s)= 1/ s4-2.613 s3+3.41s2+2.61s+1
(c) H(s)= 1/ s4+2.613 s3+3.41s2+2.61s+2
(d) H(s)= 1/ s4+2.613 s3+3.41s2+2.61s+1
Answer : d
29. The fourth order Chebychev polynomial CN(x) is
(a) 8x4- 8x2+7
(b) 8x4- 8x3+1
(c) 8x4- 8x2+1
(d) 16x4- 8x2+1
Answer : c
IV SEM EEE
30. If H(s) =3 / s+3. Find H(z)
10
e z
1
H(z) 3T 1
e z
1
H(z) 3T 1
e z
1
H(z) 3T 2
e z
H(z)
(a)
(b)
(c)
(d)
3T 1
Answer : a
FILTER DESIGN
1. The Linear Phase symmetric Impulse response having even number of samples cannot be used to
design the following filter
a) Low pass
b) High pass
c) Band pass
d) Band stop
Answer : b
2. The following filter is always stable
a) Butterworth filter
b) Chebyshev filter
c) IIR filter
d) FIR filter
Answer : d
3. Which of the filter can be realized in both recursive and non recursive structure?
a) Butter worth filter
b) Chebyshev filter
c) IIR filter
d) FIR filter
Answer : d
4. Which filter is free of Limit cycle oscillations when implemented on a finite word length
digital system
a) Butter worth filter
b) Chebyshev filter
c) IIR filter
IV SEM EEE
d) FIR filter
Answer : d
5. In which filter the memory requirement and execution time are very high
a) Butterworth filter
b) Chebyshev filter
c) IIR filter
d) FIR filter
Answer : d
6. Which of the following window is used instead of Hanning window for the same main lobe width
a) Rectangular window
b) Triangular window
c) Hamming window
d) Kaiser Window
Answer : c
7. The cascaded form of realization is used
a) When complex poles with absolute magnitude less than one
b) When complex poles with absolute magnitude greater than one
c) When complex zeros with absolute magnitude less than one
d) When complex zeros with absolute magnitude greater than one
Answer : c
8. In the following window the amplitude of the side lobes is unaffected by the length of the window
c) Hamming window
d) Kaiser Window
Answer : a
9. In which of the following windows the transition region is more and stop-band attenuation is less
c) Hamming window
d) Kaiser Window
Answer : b
IV SEM EEE
10. The main lobe width of the Hanning window is twice that of
c) Hamming window
d) Kaiser window
Answer : a
11. The Gibbs oscillations are due to
a) Abrupt truncation of the Fourier series
b) No truncation of the Fourier series
c) Abrupt termination of the Fourier transform
d) Slow termination of the Fourier series
Answer : a
12. One of the desirable characteristic of the window is that the central lobe of the frequency
response of the window should contain
a) Most of the energy and should be narrow
b) Lowest energy and should be narrow
c) Most of the energy and should be broad
d) Lowest of the energy and should be broad
Answer : a
13. In a window the desirable characteristic is that the side lobes of the frequency response should
a) Increase in energy rapidly as tends to
b) Decrease in energy rapidly as
tends to
c) Increase in frequency response
d) Contain most of the energy and should be narrow
Answer : b
14. Which window has the advantage of flexibility of side lobe level and N?
c) Hamming window
d) Kaiser window
Answer : d
IV SEM EEE
15. In which filter closed form design equations exist

a) FIR Filter
b) IIR Filter
c) Butterworth
d) Chebyshev
Answer : b
16. In which filter all the poles are located at origin
a) FIR Filter
b) IIR Filter
c) Butterworth
d)Chebyshev
Answer : a
17. In which filter high selectivity can be achieved by using higher order
a) FIR Filter
b) IIR Filter
c) Butterworth
d)Chebyshev
Answer : a
18. Which filter has less flexibility specially for obtaining on-standard frequency response?
a) FIR Filter
b) IIR Filter
c) Butterworth
d)Chebyshev
Answer : b
19. Which filter design methods are iterative procedures that require powerful Computational
facilities for Implementation
a) FIR Filter
b) IIR Filter
c) Butterworth
d) Chebyshev
Answer : a
20. Frequency sampling method is suitable for
a) Broad band frequency selective filters
b) Narrow band frequency selective filters
c) Pass band frequency selective filters
IV SEM EEE
d) Stop band frequency selective filters

Answer : b
21. The frequency sample method can be improved by
a) Introducing the stop band
b) Introducing ripples
c) Introducing the transition samples
d) Eliminating the transition samples
Answer : c
22. In the frequency sampling method the Peak side lobe level can be reduced by
a) Increasing Transition width
b) Decreasing Transition width
c) Increasing Ripples
d) Decreasing Ripples
Answer : a
23. In which of the following filter the errors due to round off noise are more
a) FIR Filter
b) IIR Filter
c) Butterworth
d)Chebyshev
Answer : b
24. In which of the following filter the poles are placed any where inside the Unit circle and
not always stable is
a) FIR Filter
b)IIR Filter
c)Butterworth
d)Chebyshev
Answer : b
IV SEM EEE
UNIT V DIGITAL SIGNAL PROCESSORS

1. The clock frequency of the fastest processor of TMS 320C54X is
a) 160 MHz
b) 40 MHz
c) 200 MHz
d) 120 MHz
Answer : a
2. TMS C54X contains ------------- number of address bus
a) Two
b) Three
c) Four
d) Five
Answer : c
3. Accumulator A & B of TMS C54x contains ----------- guard bits.
a) 4
b) 8
c) 2
d) 16
Answer : c
4. In compiler mode, if CPL = 1, ----------------- is selected.
a) Data Page Pointer
b) Program Counter
c) Stack Pointer
d) Auxillary Register Pointer
Answer : c
5. The 5-bit ASM field specifies
a) Positive values corresponds to left shift
b) Negative value corresponds to left shift
c) Positive value corresponds to right shift
d) None of the above
Answer : a
IV SEM EEE
6. Overflow flag is set if there is an overflow

a) Only in the ALU
b) Only in the multiplier adder
c) In either the ALU or multiplier adder
d) In the ALU or multiplier adder or the exponent
Answer : c
7. RSBX instruction is used to
a) Reset external flag
b) Set external flag
c) Reset test / control flag
d) Set test / control flag
Answer : a
8. ST0 register contains
a) C, TC, OVA and OVB flag
b) C, TC, O and zero flag
c) C, sign, O and zero flag
d) C, sign OVA and TC flag
Answer : a
9. In TMS 54x, rounding operation is implemented
a) Round to nearest
b) Convergent rounding
c) Clearing bits
d) None of these
Answer : a
10. Barrel shifter in TMS processor produces
a) Left Shift of 0 to 31 bits or right shift of 0 to 31 bits
b) Left Shift of 0 to 16 bits or right shift of 0 to 16 bits
c) Left Shift of 0 to 16 bits or right shift of 0 to 31 bits
d) Left Shift of 0 to 31 bits or right shift of 0 to 16 bits
Answer : d
IV SEM EEE
11. TMS 54X has -------------- interrupts.

a) 16
b) 8
c) 12
d) 32
Answer : d
12. TMS 54X has -------------- hardware non-maskable interrupts.
a) 6
b) 8
c) 2
d) 4
Answer : c
13. TMS 54x has 16-bit timer, with a ---------------- pre-scalar.
a) 4-bit
b) 8-bit
c) 16-bit
d) 2-bit
Answer : a
14. Host port is a synchronous ---------------.
a) Parallel port
b) Serial port
c) Buffered serial port
d) Multichannel serial port
Answer : a
15. DMCTR register is used to
a) Store address of DMA operation
b) Store destination address of DMA operation
c) Store number of elements to be transferred in a frame
d) Store size of data and frame count
Answer : c
IV SEM EEE
16. The --------------- addressing mode is used to implement filters

a) Circular
b) Bit Reversal
c) Direct
d) Stack
Answer : a
17. The number of instruction cycles required for execution of a program in a non-pipelined
processor is
a) One
b) Two
c) Three
d) Four
Answer : d
18. TMS320C54x processor has ------------ stages of pipeline.
a) Three
b) Four
c) Five
d) Six
Answer : c
19. In bit reversal addressing mode, new address is obtained by
a) Adding half length of FFT and propagating carry in the reverse direction
b) Adding half length of FFT and propagating carry in the next bit
c) Propagating carry in the reverse direction
d) Propagating carry to the next bit
Answer : a
20. To prevent overflow and underflow conditions in TMS320C5X processor product
register is shifted automatically right by
a) 8-bits
b) 6-bits
c) 4-bits
d) 12-bits
Answer : b
IV SEM EEE
21. Accumulator addressing is used to move data between

a) Program memory and data memory
b) Accumulator and data memory
c) Accumulator and data memory
d) Accumulator and ports
Answer : a
22. In bit reversed addressing mode, --------- register specifies one half of the size of the FFT
a) AR0
b) AR1
c) AR7
d) AR4
Answer : a
23. Function of RPT #k instruction is
a) Repeat next instruction k times
b) Repeat next instruction k-1 times
c) Repeat next instruction k+2 times
d) Repeat next instruction k+1 times
Answer : d
24. In C54X instruction, SHIFT is ----------- value.
a) 4-bit
b) 5-bit
c) 8-bit
d) 6-bit
Answer : b
25. ------------ register is used as the index register in 54X.
a) AR1
b) AR0
c) AR7
d) AR3
Answer : b
IV SEM EEE
26. In SHARC/Super Harvard architecture,

a) Data is transferred into the memory, passing through the shadow register.
b) Data is transferred directly into the memory without passing through the processor register.
c) Data is transferred into the memory, passing through the general purpose register
d) None of the above
Answer : b
27. The number of memory accesses / clock that can be achieved using on chip DARAM of a
P-DSP is
a) 1
b) 2
c) 3
d) 4
Answer : d
28. The addressing mode that is convenient for FFT computation is ----------------.
a) Indirect addressing
b) Circular addressing
c) Bit reversed addressing
d) Memory mapped addressing
Answer : c
29. The basic process that is going on inside the DSP chip is
a) quantization
b) MAC
c) Logarithmic transformation
d) Vector calculations
Answer : b
30. The result of operations performed in central ALU are stored in
a) ACC
b) ACCB
c) TREG0
d) PREG
Answer : a
IV SEM EEE

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Digital signal processing

NUMBER SYSTEMS & DIGITAL LOGIC CIRCUITS

is logically equivalent to what single gate?

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9. One of DeMorgan's theorems states that

What is the equivalent of (10110011100011110000)2 n base 32?

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(A) TTL (B) ECL

(A) ECL (B) TTL

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Q1-ON, Q2-OFF, Q3-ON, Q4-OFF

Q1-ON, Q2-ON, Q3-OFF, Q4-OFF

Q1-OFF, Q2-OFF, Q3-ON, Q4-ON

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Q1-OFF, Q2-ON, Q3-OFF, Q4-ON

28. Applying DeMorgan's theorem to the expression

can be found in almost all digital circuits

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, how many 0s are in the truth table's output column?

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bits out one bit at a time?

5. One of the major drawbacks to the use of asynchronous counters is that:

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8. A comparison between ring and johnson counters indicates that:

10. What is meant by parallel-loading the register?

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clock frequency of 20.48 MHz.

2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop?

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3. Propagation delay time, tPLH, is measured from the ________.

4. How is a J-K flip-flop made to toggle?

5. How many flip-flops are in the 7475 IC?

How many flip-flops are required to produce a divide-by-128 device?

7. Which is not an Altera primitive port identifier?

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B. The 7474 is edge-triggered.

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13. One example of the use of an S-R flip-flop is as a(n):

4. What is the difference between the 7476 and the 74LS76?

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15. Which of the following is correct for a gated D flip-flop?

16. With regard to a D latch, ________.