ASIC Solution for Fuel Cell Monitoring in Space

Matt Engelman, Ronald Carlsten, Justin Judkins, and Esko Mikkola

Ridgetop Group Inc., Tucson, Arizona 85704
This paper describes the development of a radiation-hardened fuel cell monitor Application-Specific
Integrated Circuit (ASIC) designed to measure 48 differential cell voltages in series, in the range of 0-2
VDC per cell. The analog signals are sampled and converted to digital words with 10-bit resolution. The
XFAB XDM10 SOI Foundry process was chosen because it includes devices capable of withstanding
drain-to-source voltages greater than 100 VDC. High-voltage breakdown vulnerability is mitigated
laterally using oxide trenches to surround high-voltage transistors while a buried oxide layer provides
vertical isolation and latch-up immunity. Individual switched input sampling circuits store differential
cell voltages on a capacitor using two non-overlapping clock signals, thus eliminating the common-mode
gain error introduced by a diff-amp input stage. The chip includes prognostic cells for measuring the
cumulative effects of radiation and provides early warning of an impending failure due to charge
accumulation from high-energy particle strikes. We report on the performance and feasibility of the
design in simulation.

Nomenclature
DMOS: Double-diffused Metal-Oxide Semiconductor
CMOS: Complementary Metal-Oxide Semiconductor
BCD: Bi-polar, CMOS, DMOS process
SOI: Silicon on Insulator
TID: Total Ionizing Dose
SEE: Single-Event Effects

I.

Introduction

Fuel cell technology is an attractive energy storage option for manned space exploration missions due to its high
power density, high reliability, and scalability. However, troubles caused by one or a few degrading cells can result
in premature failure of the entire system. Therefore, to use this option safely in space, the voltage output of all
individual cells within the system must be precisely and continuously monitored in real time. A good monitoring
solution can quickly identify failing cells, and early adjustments from the control system can maintain or extend the
lifetime of the remaining fuel cell system. Currently, monitoring of fuel cell stacks is accomplished using discrete
components. The typical method to monitor a 48-cell stack is to employ 48 separate differential amplifiers along
with 2 to 3 resistors per cell. The voltage levels can then be digitized using an analog selector and a single ADC, but
this solution still requires many discrete components and takes up a significant area on the control unit printed
circuit board. The reliability of this board degrades as the number of discrete components is increased.
Control electronics for fuel cells used in space applications must also be hardened to radiation effects, such as
total ionizing dose (TID) and single-event effects (SEE), which degrade transistor performance over time and cause
logic upsets. This is particularly troublesome to systems that are designed around discrete commercial components.
However, specific design techniques can be employed to minimize degradation and improve lifetime of the control
electronics in the space environment through the design of an application-specific integrated circuit (ASIC).
Typical CMOS devices cannot withstand the high common mode voltage required by a 48-cell stack. This
problem is solved by using high-voltage CMOS structures that provide deeper wells and greater isolation than
standard CMOS. With this process, a fuel cell monitoring ASIC can be designed to withstand up to 96 volts
common mode, for instance, when the cells are in electrolysis mode.
Both the radiation and voltage conditions must be met in order to have a feasible design for a fuel cell monitor for
space applications. The remainder of this paper details the circuit architecture as well as process requirements and
design techniques that enable a high-voltage rad-hard monitor.

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II.

Foundry

Process selection is an important initial step due to the unusual electrical requirements and the harsh
environment that the fuel cell monitor ASIC will be subjected to. Fundamentally, the evaluation was constrained to
CMOS processes because it is the most reliable and mature process, and is relatively easy to design for. Next,
beginning with a comparison study of several compatible mixed-signal foundries, X-FAB was selected for the
fabrication of this chip. This foundry provides commercial access to a process that is well characterized and meets or
exceeds all of the necessary requirements for the design. Key requirements that were considered included: (1) high
voltage isolation, (2) intrinsic radiation tolerance, (3) full range of device models, and (4) access to multi-project
wafer (MPW) runs. Moreover, this process uses a silicon-on-insulator (SOI) wafer, which provides additional
benefits for radiation hardness (discussed in more detail in Section V). The circuit simulations presented in this
report are based on the process design kit (PDK) for the XDM10 1.0 m 350 V SOI process. The devices are
simulated using HSPICE models.
The selected process was developed for power applications and has a 1.0 m minimum feature size. It is a SOI
process and provides up to 350 volts of isolation at DC. Smart power processes can be grouped according to the two
main methods of achieving high-voltage device isolation: PN-Junction Isolation, or JI, and Dielectric Isolation, or
DI. The DI approach has the advantage of being a non-polarized isolation, unlike JI processes; thus simplifying chip
layout and bulk biasing. The SOI DI process also has the added benefit of being insensitive to transient radiation due
to heavy ion strikes, thus providing a rad-hard-by-process solution to latch-up failures. The XFAB PDK offers a
variety of high voltage MOS, bipolar, and passive devices required for this design. Table 1 gives a description of the
process.
Table 1: XFAB XDM10 Process Description
Process

XFAB XDM10 1.0 m 350 V Process

Variety of 275 V and 350 V DMOS, 360 CORE
High-Voltage PMOS (Standard CMOS)

High-Voltage Devices
Used

80 V lateral PNP
80 V vertical NPN
200 V diode
350 V tolerant sandwich capacitor

Process Description

n-type SOI substrate, trench/buried oxide isolation, single well, single poly, 3 metal layers

Advantages

Non-polarized isolation due to buried oxide; wide variety of high-voltage devices including
350 V capacitor; breakdown of devices is two and three times the highest voltage seen in
the fuel cell ASIC application; increased packing density compared to JI; typically a lower
mask count than JI; full dielectric isolation suppresses substrate currents, eliminating
latch-up problems (inherent SEL radiation hardness); mature process with multi-project
wafer (MPW) and multi-level mask (MLM) runs available at relatively low cost

III.

Architecture

The design goals for the project were as follows:

Monitor 48 differential cell voltages
Cell voltage measurement range of 0-2 Volts DC
Maximum common mode voltage of 100 Volts DC
Measurement accuracy within 10 mV
Digital control of cell selection and measurement
Radiation-hardened to 300 krads
The block diagram of the fuel cell monitor chip is shown in Figure 1. A separate microcontroller close to the
ASIC sends clock and control signals to the fuel cell monitor ASIC. These signals provide timing control and
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sequencing for cell voltage measurements and also select which cells to monitor. The input control block
communicates with a sample-and-hold decoder, and a 6-bit word selects each of the 48 cells. The selected cell
voltage is then applied to the sampling capacitor with ground as the reference (the common mode voltage is stripped
off), and the sample voltage is converted to a 10-bit digital word by the ADC. This is sent off-chip to the
microcontroller as parallel bit lines. The differential switched-capacitor sample-and-hold circuit is controlled by the
input control function in the microcontroller. The four non-overlapping clock signals drive the switched capacitor
sample and hold, and 15 total clock cycles are needed to charge the sampling capacitor. The frequency of the nonoverlapping clock signals is 100 kHz; therefore the sampling time is 150 sec. The ADC is an over-sampling
Incremental Delta-Sigma ADC that will take 2.5 msec to convert the analog voltage to a digital word. Therefore,
measuring 48 cell voltages takes about 130 msec. The master clock for the ADC is 100 KHz. Two radiation
prognostic sensors provide data on the degradation of the circuit due to exposure to the space environment. These
cells measure total dose effects due to charge accumulation in the field oxide (RadCell FOX) and changes in the
threshold voltage parameter (RadCell VT). These cells will communicate with the microcontroller IVHM function to
continuously update the health status of the monitor circuit.

Figure 1: Fuel cell block diagram

IV.

Switched-Capacitor Sample and Hold

One of the design questions is how to sample a small differential input at high voltages. Figure 2 shows the
schematic of the differential switched-capacitor sample-and-hold designed to overcome this challenge. This input to
the circuit is the differential voltage across one single cell within the fuel cell stack. Through a switched-capacitor

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network, this differential voltage is converted to a single-ended voltage with ground reference. The conversion is
fast with respect to changes in the fuel cell stack, and it is minimally sensitive to large common mode voltages.
Referring to Figure 2, the switched-cap circuit is driven by four non-overlapping clock signals (P, P_BAR, and
N, N_BAR), which come from the microcontroller. The P and P_BAR drive the CMOS FETs near the input and
N and N_BAR drive the CMOS FETs near the output. During the first clock phase, the transistors M1-5 and M7 are
switched on and the capacitor CP is charged to the input voltage V-. In the following clock phase, M6 and M8-10 are
turned on and the voltage V+ is applied to capacitors CP and CS in series. However, CP is already charged to V- so
only the differential voltage V is considered in calculating new charge distribution to the two capacitors. This
distribution is determined by simple voltage divider relationship, and in one complete clock cycle the voltage on CS
rises by a factor of CP/ (CP+CS). Successive clock cycles ( and _BAR) incrementally pump charge to CS, causing
the voltage Vo to rise toward V in a geometric progression series. The ratio of the two capacitors is chosen such
that it takes 15 clock cycles to reach a steady output voltage that is within measurement error. The T-GATE is part
of the decoder circuit and is turned on when a cell is being monitored. When the cell voltage is not being measured,
the SELECT line turns off the T-GATE and the clock lines are disabled using AND gates, which are also tied to the
SELECT line. This keeps the 47 nonmeasured cells from affecting the charge on the sampling capacitor (CS).
Ideally, the switches built from the transistor networks would have infinite resistance when turned OFF and zero
resistance when turned ON. Of course this is not the case, and it was discovered that the ratio of OFF-to-ON
resistance was too low to achieve the ideal results, so multiple transistors were arranged in series to increase OFF
resistance on the V- leg. The asymmetric arrangement was necessary because the two input switches form a voltage
divider circuit during the second clock phase and do not allow the total V to be achieved. By increasing M1 to M1-5,
the OFF resistance increases enough to sample V to within the measurement resolution.

V-

V+

P
M1-5

M6
M8-10

N
CP

M7
T
CS

SELECT

Vo

Figure 2: Differential switched-capacitor sample and hold

Figure 3 shows how the sampling capacitor is charged to V by the clock. Once the voltage level settles, the
clock is paused and the voltage is converted to a 10-bit word by the Incremental Delta-Sigma ADC. This process is
repeated for each successive fuel cell, so a characterization of the entire fuel stack is completed in about 130 msec.

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Figure 3: Simulation of cell voltage measurement

V.

Effects of Radiation

The electronics on-board space missions face reliability threats due to radiation particles from different origins.
The space radiation environment in the vicinity of Earth consists of three different radiation components: trapped
particles in the Van Allen belts (protons and electrons), solar particles (protons, electrons, and ions), and galactic
cosmic rays (high energy ions and protons). All three of these radiation components cause both single-event upsets
and TID effects in the electronic circuits.
Hardening Against TID Effects
Our design on the selected XFAB 1.0 m BCD process contains CMOS and DMOS transistors. The process uses
SOI substrates to build dielectric isolation structures against high voltages, but the CMOS and DMOS transistors are
constructed with fairly wide and deep bulk silicon body areas, thus the radiation effects of these transistors will be
close to equivalent transistors in bulk processes. The NMOS transistors will face two types of TID degradation in
the space environment: threshold voltage shifts (VTH shift) and off-state leakage currents. There are three types of
TID-induced off-state leakage currents: 1) source-to-drain leakage in an NMOS transistor due to isolation oxide
sidewall inversion (marked with 1 in Figure 4), 2) NMOS to N-well leakage due to inversion of the silicon bulk
under the isolation oxides (marked with 2 in Figure 4), and 3) NMOS to NMOS leakage that is also due to inversion
of the silicon bulk under the isolation oxides. All three of these leakage mechanisms are caused by radiation-induced
trapped charge in the isolation oxides (LOCOS or STI), whereas VTH shifts are due to trapped charge in the gate
oxide and in the interface between the gate oxide and the silicon body region.

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Figure 4: Two leakage paths that are formed due to total ionizing dose
The source-to-drain leakage can be effectively eliminated with the enclosed gate layout technique (Figure 6).
This technique will be used throughout the design. The NMOS to N-well and NMOS to NMOS leakage currents will
be blocked with guard rings surrounding NMOS transistors (Figure 5). These guard rings also eliminate single-event
latch-up (SEL).

Figure 5: Enclosed gate NMOS transistors and p+ guard rings

VTH shifts have been shown to be approximately -30 mV for NMOS and -(100-200) mV for the PMOS
transistors in common 0.8-1.2 m commercial processes after 100 krads of TID radiation [3]. 100 krads is a
common TID value used to describe 10 years of operation in space behind normal shielding thicknesses. VTH shifts
of this magnitude are not serious reliability concerns for the 5 V digital circuits in this application. However, these
VTH shifts have to be mitigated in the analog circuits, such as the on-chip ADC. Standard offset cancelling
techniques, such as the auxiliary amplifier technique [4], can be used for this purpose.
The greatest concern related to TID in this application is the VTH shift in the thick oxide, high-voltage (HV)
devices used in the front end of the chip. These thicker oxide devices can have TID-induced VTH shifts equaling a
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few volts at a dose level of 100 krads [5]. The thick oxide PMOS devices degrade less than their NMOS
counterparts [5], and the drive current-reducing effect of the negative VTH shift in a PMOS switch can be effectively
canceled out by increasing the gate overdrive. The added benefit from using solely PMOS devices in the front end is
the absence of TID leakage currents. Our design uses PMOS HV devices in the high-voltage front end as switches,
and we will also use increased gate overdrive to cancel out any large VTH shifts in these devices. This overdrive
voltage is taken from an external reference or generated on-chip with a charge pump. The amount of the needed
overdrive voltage is controlled by the RAD VTH, a radiation effect monitoring circuit that measures the amount of
threshold voltage shift due to TID. This monitor circuit is discussed in Section VI of this paper.
Hardening Against Single-Event Effects
The most prominent single-event effects of the CMOS and DMOS transistors in this application will be singleevent latch-up (SEL), single-event upset (SEU), and single-event transient (SET). Since the MOS transistors in this
BCD process have fairly thick silicon bodies, the SEE sensitivity is not significantly reduced as it is in SOI
processes with thin transistor silicon body regions. The SEL condition will be avoided by implementing guard rings
throughout the layout. SEU in storage units, such as registers, will be mitigated using redundant latches. SETs are
only a problem if they cause data to be lost. Increased currents and capacitance in critical nodes can be used to
mitigate this problem. The effectiveness of the used mitigation techniques will be evaluated by simulation.

VI.

Radiation Prognostic Cells

In order to know the level of radiation degradation any time during the mission, Ridgetop will include radiation
effect monitoring circuits on the chip. In addition to giving accurate information about the radiation effects, these
circuits can be used to control the amount of overvoltage on the gates of the front-end high-voltage PMOS devices
needed to compensate for VTH shifts, or to trigger an anneal cycle to reduce the trapped charges. Ridgetop has
designed two radiation monitoring prognostic cells, RAD FOX and RAD VTH.
RAD FOX Block
The schematic circuit for the field oxide leakage radiation prognostic cell (RAD FOX) is shown in Figure 6. The
leakage mechanism has a special monitor transistor structure N1. The drain of the monitor transistor is fed from a
constant current source whose value is set to 50 nA, which is the allowed radiation degradation limit. If the leakage
of the transistor under test is not degraded sufficiently by radiation, the transistor will not be able to sink the current
from the current source and the output voltage will be high. However, if the leakage of the monitor transistor has
become sufficiently high due to degradation by ionizing radiation, it will be able to sink the current from the current
source. The output will be pulled low, and this will be detected as a failure signal.

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Figure 6: Schematic circuit of the field oxide (FOX) leakage radiation prognostic cell

The monitor transistor is basically a wide transistor with the drain and the source area cut into pieces to provide a
large number of source-to-drain edges. The device shown in Figure 7 has 20 field oxide edges from the source to an
adjacent drain, as opposed to two edges in a normal MOS transistor. Hence this snaked structure has 200 source-todrain edges and would be 100 times more sensitive to the end-around leakage damage, when compared to a
prototype MOS device. This significantly enhances detection of this type of radiation-induced leakage path. The
stress transistor is biased at VDD during irradiation and biased at ground during measurement mode. Ridgetops chip
will include RAD FOX monitors targeting TID leakage effects in both CMOS and DMOS transistors.

Figure 7: Snaked segmented gate transistor with many edges as a detection device
for end-around leakage monitoring

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RAD VTH BLOCK

The VTH shifts due to charge trapping in the gate oxide are highly dependent on transistor bias, process
technology, and the radiation environment. The concept of the prognostic cell design is to utilize the difference in
radiation response when different gate bias conditions are present. As shown in Figure 8, during the stress cycle, the
two monitor transistors are held at different gate biases. Since the two gate oxides have different fields while being
subjected to ionizing radiation, they will exhibit a different amount of VTH shift. The gate of the stressed device is
biased at VDD and the gate of the reference device is biased to ground, in order to apply the worst-case radiation
conditions over the stressed monitor device. During the measurement cycle, the difference in the threshold voltage
between the two transistors is measured. A fall in VTH of the stressed device by a factor of 5% triggers the detection
circuitry and the output of the prognostic cell is pulled low.

Figure 8: Schematic circuit of the threshold voltage shift radiation prognostic cell
During the measurement mode, both the transistors are diode-connected, as shown in Figure 9, with the current
supplied by the two legs of a current mirror, and the difference in the drain voltages is used to trigger the prognostic
cell. The relative amount of shift in the threshold voltage between the two devices is used in the VTH shift radiation
prognostic cell to determine whether the circuit will remain functional.

Figure 9: Schematic circuit of the threshold voltage shift radiation prognostic cell
during the measurement cycle
Since the degradation is expected to be small in magnitude, a transistor implementation of an amplifier and a
comparator is used in the detection between the drain voltages of the stressed and the reference transistors. The
detection is very sensitive, and it triggers when the difference in voltages reaches a precise, pre-specified amount.
The output was found to trigger at the correct preset level (5% negative threshold voltage shift).

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VII.

Conclusion

This paper reports on the design and simulation of an ASIC chip that will be used to measure the cell voltages of
a fuel cell stack. The chip will be designed in XFAB 1.0 BCD process. The chip will be radiation-hardened both
by process and by design. The effects of radiation will be measured by two prognostic circuits that will be reported
to the main -processor. A large common mode voltage is mitigated by the use of a novel switched-capacitor
sample-and-hold circuit. The measured cell voltage will be converted to a digital output by a 10-bit Incremental
Delta-Sigma ADC. Simulation results of the high-voltage sample-and-hold circuit show the mitigation of the
common mode voltage and accurate measurement of the differential voltage at the cell.

Acknowledgements
The authors wish to thank Kenneth Burke from NASA Glenn Research Center in Cleveland, Ohio for his help
and support on this Phase I SBIR project from NASA Glenn Research Center.

References
1.

L.G.van den Berghe, CMOS integrated circuit for differential monitoring of spacecraft battery cell
voltages, IEEE Proceedings, Vol. 135, Pt.I, No. 6, December 1988.

2.

Mike Rebeschini, Nicholas R. Van Bavel, Patrick Rakers, Robert Greene, James Caldwell, and John R.
Haug, A 16-b 160KHz CMOS A/D Converter Using Incremental Delta-Sigma Modulation, IEEE Journal
of Solid-State Circuits, Vol. 25, No. 2, April 1990.

3.

J.V. Osborn, R.C. Lacoe, D.C. Mayer, and G. Yabiku, Total Dose Hardness of Three Commercial CMOS
Microelectronics Foundries, IEEE Transactions on Nuclear Science, Vol. 45, No. 3, June 1998.
B. Razavi, Principles of Data Conversion System Design, IEEE Press, 1995.

4.
5.

T. P. Ma and P. V. Dressendorfer, Ionizing Radiation Effects in MOS Devices and Circuits, John Wiley
& Sons, 1989.

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