DETAILED MODELING OF STATIC VAR COMPENSATORS USING

THE ELECTROMAGNETIC TRANSIENTS PROGRAM (EMTP)

Sang Y.Lee
Subroto Bhattacharya
Member IEEE Senior Member IEEE
ABB Power Systems Inc.
Advanced Systems Technology
Pittsburgh, Pennsylvania

Tommy Lejonberg
Non-Member
ABB Power Systems
Viisterh, Sweden

ABSTRACT
A detailed model of Static VAr Compensators has
been developed for digital simulation of electrical
transients. The model is applicable to SVC configurations
employing thyristor-switched capacitors (TSC) and
thyristor-controlled reactors (TCR).
A modeling
technique based on EMTP data modularization is used to
represent essential parts of the SVC main circuit and
control system. To verify the model, an actual SVC is
simulated with the EMTP and the results are compared
with the TNA-type simulator using actual SVC controls.

Keywords
Static VAr Compensator (SVC), Thyristor Switched
Capacitor (TSC), Thyristor Controlled Reactor (TCR),
Electromagnetic Transients Program (EMTP) Modeling
Techniques.
INTRODUCTION
Static VAr Compensators (SVC) installed in power
transmission systems serve in various ways to improve the
system performance. By the rapid control of their reactive
power output, the SVCs regulate system voltages, improve
transient stability, increase transmission capacity, reduce
temporary overvoltages, increase damping of power
oscillations, and damp subsynchronous resonances and
torsional oscillations.
Power system simulation plays an important role in
the design and analysis of SVCs. Two types of simulation
tools are currently available. The Transient Network
Analyzer (TNA) generally uses scaled models of the
network and the SVC main circuit combined with the
actual SVC control system. Digital computer programs
employ mathematicalmodels to simulate the entire system.

Adel Hammad
Fellow IEEE
ABB Power Systems
Baden, Switzerland

Serge Lefebvre
Member IEEE
IREQ

Montreal,Canada

The EMTP is one of the most widely used programs

for simulation of electrical power system transients. The
program offers accurate representation of power system
equipments including sources, lines, transformers,
breakers, loads, arresters, thyristors, etc.
The EMTP is well suited for simulation of SVCs as
demonstrated in References [l,2, 31. Transient Analysis
of Control Systems (TACS) allows detailed modeling of
the SVC control system so that power system and control
system transients can be simulated simultaneously. The
EMTP data modules (EDM), which became available in
1983,have significantly improved the EMTP usage [4,5].

This paper presents a detailed model of SVCs

employing thyristor-switched capacitors (TSC) and
thyristor-controlled reactors (TCR). The characteristicsof
the model are as follows:
The model is flexible enough to represent different
SVC configurations including the two most widely
used the fured capacitors and thyristor-controlled
reactors (FC/TCR), and the combined
thyristor-switched capacitors and thyristor-controlled
reactors (TSC/TCR).
The model represents an SVC control circuit based on
the phase-locked loop (PLL) and voltage regulation
loop. The control functions are modeled with TACS.
A modeling technique based on EMTP data
modularization (EDM) has been adopted for the
model development. The model, therefore, takes the
form of modularized EMTP data stored in a EMTP
module library.
The steady-state model initialization is improved by
using the calculation section, an enhanced feature
added to the EDM. This feature, which was
developed with the model, allows the EDM to
calculate system parameters and incorporate them
into the EMTP data.
The model has been developed with the DCG/EPRIreleased version 2.0 of EMTP.

0-7803-0219-2/91/0009-0941$01.00
01991IEEB

reactor (TSC/TCR)

The model has been tested using an existing SVC

design. The comparison of test results with the
transient responses obtained by TNA-type simulation
has served as verification of the EMTP model.
Selected test results are presented in this paper.

The SVC control system is an integral part of the

power network. Providmg firing signals to the SVC
thyristors allows the system to interact with the power
network over a wide frequency range. An objective for the
detailed SVC model development is to produce a control
system representation which is valid over a frequency band
from a few Hertz up to a few kHz. The heart of the SVC
control system is the two feed-back control loops: the
phase-locked loop (PLL) and the voltage regulator loop.

The modeling work described in this paper is part of

the development efforts conducted by the Advanced
Systems Technology Division of ABB Power Systems as a
participant in the EMTP Development Coordination
Group (DCG). These development efforts are jointly
coordinated by DCG and the Electric Power Research
Institute (EPRI).

2.

Essential Model Elements

The major elements of the SVC main circuit are: the

step-down transformer, the TCR unit, the TSC Unit, and
the harmonic filters. These are modeled with EMTP
branch and switch cards. Thyristor valves are represented
by TACS controlled switches. Essential control circuits
are: the phase-locked loop (PLL), the voltage regulator,
the measurement circuit, the allocator, the linearizer, and
the TCR and TSC firing circuits.
a. Thyristor controlled reactor (TCR)

FC/TCR

A three-phase TCR unit is formed by three

delta-connected single-phase branches. Each branch has
a pair of anti-parallel thyristor valves connected in series
between two reactor units. Each thyristor valve is
modeled by a type-11 TACS controlled switch. The
thyristors in the three-phase TCR unit are controlled as a
&pulse group by gate signals from a TCR firing circuit.
The TCR is usually connected to the trammission system
through a step-down transformer.

TSC/TCR

1*
Fixed ~pacitor/th~istor-controued
reactor (FC/TCR) and
switched
(TSC/TCR)
capacitor/thyristor-controlled
SVC configurations

b. Thyristor switched capacitor (TSC)

STATIC VAr COMPENSATOR (SVC) MODEL
A three-phase TSC unit consists of three branches in
delta connection. Each TSC branch has a pair of antiparallel thyristor valves connected in series with a
capacitor bank and a tuning and/or current limiting
reactor. The thyristor valves switch the capacitor banks
either fully on or fully off. A TSC firing circuit controls
the TSC unit. The model allows connection of a number
of TSC units in parallel to achieve a multiple-step control
of capacitive MVAr.

1. s v c c onfieurations
SVCs consist of thyristor and mechanically switched
shunt devices which generate or absorb reactive power.
The SVC model takes intd account three types of shunt
devices: the thyristor-codtrolled reactor (TCR), the
thyristor-switched capacitor (TSC), and the fixed or
mechanically switched capacitor (FC) bank or harmonic
filter. A TCR can change its reactive power output
continuously. A TSC provides step MVAr changes.
Properly combining these shunt devices, an SVC can
control its reactive power output continuously over a wide
range from inductive to capacitive. Figure 1 depicts the
most widely used combinations: the fured capacitor and
thyristor-controlledreactor (FC/TCR) ,and the combined
thyristor-switched capacitors and thyristor-controlled

c.

Harmonic filters

Two types of harmonic filters are included in the SVC

model: the single-tuned band-pass type and the high-pass
type damped filters. A three-phase filter unit consists of
three identical filter branches in a wye-connection with the
neutral floating. The neutral can be grounded through an
942

impedance branch if desired. Electrical characteristics of

these fdters are well known [6].

phase-locked loop consists of four functional blocks: a

phase comparator, a regulator, a voltage controlled
oscillator (VCO), and a frequency divider.

Figure 2 shows the fdter configurations.

ACBUSA

ACBUSB

Figure 3 shows the block diagram of the PLL circuit

with a proportional-integral (PI) type regulator,

ACBUSC

e.
I-

7=

The voltage regulator performs the closed loop voltage

control. The difference between the voltage reference
(UREF) and the network voltage response (URESP) is
fed as the control error signal to a PI-regulator which
changes the total SVC susceptancereference (BREF). The
input AUREF is provided for interface with higher-level
control blocks.

ACBUSN

ACBUSA

ACBUSB

Voltage regulator

ACBUSC

Figure 4 shows the block diagram of the voltage

regulator.

:"":-

ACBUSN

Figure 2. SVC fdter configurations

Pl REGULATOR

UPPER UMK

BREF

- -

PHCOMPA
PHASE COUPMATOR.
BCOUNTER
FREQUENCY DIVIDER.
PlREG
PROPORTIOW INTEGRAL REGULATOR.
EASE
WEOUENCY

FRZPLl
UNORMI

LOWER UMlT

PLlATC
PHCOMPA
PLlAPC
PLlANc

DEWATION

BCOUNTER

Figure 4. The SVC voltage regulator

Figure 3. The phase-locked loop control
f.

Allocator

The allocator converts the susceptance reference

(BREF) signal from the voltage regulator to logical orders
(on/off signals) for the TSCs and arithmetic orders for the
TCRs. The module outputs two quantities: the number of
TSC units required to be on (NOTSCS) and the
susceptance order for the TCRs (BTCR). The two output
signals are piece-wise functions of BREF. Since the range
of BTCR is normally greater than the susceptance of each
TSC, there is a hysterisis between BREF and the two
outputs. In the hysterisii region, there are two output
states causing the same MVAr supply from the SVC to the
network.

d. Phase-locked-loop
The phase-locked loop (PLL) produces an output
pulse train in response to an input ac voltage signal,
reducing the phase error between the two signals by the
negative feed-back control. When the two signals have the
same frequency and phase, the control system is said to be
phase-locked. When this happens, the output pulses will
come exactly at the peaks of the sinusoidal input voltage.
The output signal of the PLL is used as the reference
for the TCR and TSC thyristor valve firing angles. The
943

Figure 5 shows the block diagram of the allocator.

TSCwIr

1
.

difference between ALPHON and ALPHOF is the firing

pulse width which is approximately equal to the thyristor
conduction angle Q :ALPHOF - ALPHON = Q .
Figure 6 shows the block diagram of the linearizer.

h. TCR firing circuit

Figure 5. The SVC allocator

The TCR firing circuit generates firing pulses to the

three-phase TCR unit. Inputs to the Circuit are: the
synchronizing signal from the PLL circuit and the firing
angles determined by the linearizer (ALPHON and
ALPHOF). A firing pulse is on while the elapsed time
since the occurrence of the last peak voltage is greater
than the current value of the ALPHON signal but less
than that of the ALPHOF. The pulse is directed to one
of the anti-parallel thyristor valve pairs.
Figure 7 shows the block diagram of the TCR firing
circuit.

1 .o

PLlHLD-

i.

The TSC firing circuit generates firing pulses to a

three-phase TSC unit. Each TSC unit is assigned a
priority number by the user and the TSC is activated when
the NOTSCS signal from the allocator is greater than or
equal to this number. In this way, TSC units are turned
on sequentially from the lowest priority number to the
highest.

Figure 6. The SVC linearher

Figure 8 shows the block diagram of the TSC firing

circuit.

g. Linearizer

The linearher converts the susceptance order (BTCR)

from the allocator to a firing angle order a which is
measured from the time of the last voltage peak. To
maintain the same control response over the entire SVC
operating range, the anglea is determined as a non-linear
function of the BTCR. This function is given as a table
which is derived from the following formula:
l-X,-B(a)

TSC firing circuit

a +

j.

Measurement circuit

The main function of the measurement circuit is to

provide the voltage regulator with the power system
voltage response measurement (URESP).
The
measurement circuit also provides the signal conditioning
required to achieve a typical steady-state SVC regulation
characteristic with the slope determined by a control
setting SLOPE. The output signal AURESP represents
this feature.

sin(3t.U)

The model allows representation of measurement circuits

with different techniques. Figure 9 shows the block
diagram for one of such circuits.

where
is the TCR reactance at the fundamental
frequency, B (a) is the susceptance of the TCR fired at
a , and a is the angle in per unit of 90 degrees.

3. Additional Control Functions

The module generatestwo output signals derived from

a: the anglea given in per unit of 90 degrees (ALPHON)
and the angle of thyristor turn-off (ALPHOF) . The

Other typical SVC control functions are also included

in the EMTP module library:
944

PLLAPC

SClABG

s c l BAG

Puspc

SC1 ECG

PLLBNC

SClCEG

PLLCPC

PLLCNC

Figure 7. The TCR firing circuit

-=

sclACc

Figure 8. The TSC firing circuit

TCR overcurrent control. This circuit prevents

excessive current in the TCR during system
overvoltage conditions by imposing a delay of the
trigger pulses to the TCR.

Lq7-

'

Secondary overvoltage limiter. This circuit prevents

excessive voltage on the secondary side of the SVC
transformer by acting on the limits for the voltage
regulator output.

BASE kV

URESP

BASE SUSCEPTANCE-

Undervoltage strategy. To prevent excessive voltages

in connection with fault clearing, this circuit applies
predetermined control actions during conditions of
abnormally low ac voltages.

Figure 9. The measurement circuit

Higher level control functions, such as power and

reactive power modulations, are not included in the SVC
model. The characteristics of these circuits are normally
unique for each specific SVC application and can easily be
modeled with the TACS program.

MODELING TECHNIQUE

A modeling techniaue based on EMTP data

modularization (IEDM) h& been adopted for the model
development. The technique can be described in terms of
design rules observed during the model development and
testing. These rules help avoiding duplicate use of names
945

After the naming is completed, connect the system by

supplying proper names as arguments to the modules.
This is done by listing the names in the $INCLUDE
statements in the EMTP data file.

for different variables and to facilitate the trace of names

of electrical nodes or control signals inside a device.
1. Variable Names in a Module

To complete the system representation, all necessary

numerical data must be supplied to the $INCLUDE
statements. Attention must be given not to exceed the
maximum width of numerical field allowed by the
modules.

Each module has three sections: the declaration, the

calculation, and the body. The calculation section is
optional and can be omitted.
During the model development, the variable names in
a module were specified in the declaration as follows:

It should be noted that, if the first three characters of

all devices, nodes and control signals are distinct, there
will be no duplication of names.

The first three characters of the names of selected

electrical nodes and control signals used only within
the module are declared as 'ARG'. All these names,
therefore, have the identical first three characters. The
remaining three characters are determined by the
module to make the names unique. The threecharacter root name is the device name.

3.
n -

The EMTP simulations take place in two steps: the

steady-state initialization followed by the time-step
solution.

The names of the electrical nodes and the control

signals connected to the outside of the module are
declared 'ARG'. Only the five-character root name
may be specified for a three-phase node. The last
character is determined by the module to distinguish
the phase,

The initialization of a power system with SVCs is

usually difficult. The reasons are:
The EMTP uses a sinusoidal steady-state solution of
the linearized a.c. system to calculate the initial
condition without taking full account of the control
system.

All other six-character variables within a module that

are neither fully nor partially specified through the
'ARG' are declared 'DUM'.

TCR is a harmonic source and the EMTP calculates

the steady-state solution only at one frequency.
Ignoring the harmonics, the initialization is only
approximate.

2. Module Connection
The detailed SVC model can represent various SVC
configurations including TCR and TSC units and harmonic
filters. The EMTP user is required to connect the
modules by following simple rules and to supply proper
data to the modules:

Some control blocks need time to be correctly

initialized.
A simple but effective initialization method is used.
The SVC model is initialized by using the EMTP's a.c.
system initialization. The TCRs are blocked during the
steady-state initialization. All thyristor valves of initially
operating TSC units are "CLOSED"for initialization. The
control system is not allowed to operate in full closed-loop
control mode immediately after t = 0 . The control
system initialization produces equally spaced fuing pulses
for a specified initialization period. The SVC model
automatically sets the length of this period to U) ms, but
the length can easily be increased by the user.

Name all three-phase electrical nodes adjacent to each

power component with five-character strings, and all
single-phase nodes with six-character strings.
Name each power component with a distinct threecharacter string if the module requires it. This naming
eliminates the possibility of a duplicated EMTP node
name for two distinct variables, especially when two
similar components are connected in parallel.

MODEL APPLICATION AND TESTING

Name all TACS control signals exchanged between

the control function blocks with six-character strings.

1. Test Svstem Description

Name each control function block with a threecharacter string if the module requires it. Any number
of identical function blocks may, therefore, be used.

The test system is an existing SVC scheme installed in

a 345-kV transmission system and fed by a 345/18-kV
946

step-down transformer. The SVC is a combined

TCR/TSC type consisting of three TSCs rated 121 MVAr
each, one TCR rated 163 MVAr, and 31-MVArof 5th and
7th harmonic filters. The overall rating of the SVC is
from 125 MVAr inductive to 425 MVAr capacitive,
referred to 1.0 pu primary voltage.

BUS 3
345 kV

BUS 4
115 kV

BUS 2
345 kV
SVS BUS BUS 1
345 kV 345 kV

{LINE

11 LINE 1

ZEQl
I

The control system includes undervoltage strategies

and power modulation controls.
The undervoltage strategies take the following actions
when the voltage response signal from the measurement
circuit drops below a preset limit of 0.6 pu:

4
Tf '
T T T

Clamp the voltage regulator output (BREF) to zero

Figure 10. Equivalent transmission network

Block all TSCs

These actions are removed after a 30 ms delay when
the voltage increases above 0.69 pu.
SVC. Initially, there is 700 M W of power flowing from
Bus 1 to Bus 2.

A power modulation control block is added to the

SVC control system. This high-level control function
u t i l i s the power system response as the input and acts on
the voltage regulation to provide damping for slow electromechanical swings in the power system. The input is the
RMS current in the 345 kV transmission line. The output
is added to the voltage reference through AUREF input of
the voltage regulator. AUREF is provided for interface
with high-level control blocks. The transfer function is
shown below as an example of a typical high-level control
block

The simulated sequence of events is:

A three-phase to ground fault at Bus 1 occurring at t
= 0.1 second.
Removal of the fault at t

0.2 second.

Figure 12 shows the results of the EMTP simulation

using the detailed SVC model. Figure 13 shows the SVC
performance in the TNA. The results include the
waveforms of currents in the TSC and TCR units and two
control signals, i.e., the voltage response and the
susceptance reference.
The waveforms in Figure 12 show that the system is
initialized well within 0.1 second. The two plots show that
the SVC susceptance (BREF) is clamped to zero by the
undervoltage strategy almost immediately after the fault.
Both plots also show a similar depression in the primary
bus voltage.

Figure 10 shows the equivalent 345-kV transmission

network with the SVC located in the .middle of a 345-kV
line. The network data are provided in Appendix.
2. m

m
After the fault is cleared and the voltage is restored
above 0.69 per unit, the BREF starts to increase. Both
plots show that there is a delay between the time of
recovery and removal of the clamp on the BREF. This is
because of the 30 ms delay in the undervoltage strategy.
For a short time period of about 80 ms, both plots show
BREF in the capacitive region with TCS unit 1 operating
and the TCR unit almost fully on. After this period, the
operation slowly settles down to the original steady-state
operating point. The two plots show good agreement.

Figure 11 shows the model of the SVC. The figure

indicates the names of the electrical nodes, devices and
control signals.

3. Test Cases and Resulb

The initial operating point is 1.0 pu voltage at the
345-kV SVC bus and 14 MVAr inductive output from the
947

HUSUREA

PLIA

-JTSCPULS
TSCPULS

"REF

ALLOCATOR
I

Figure 11. Complete SVC test model

SUMMARY

ACKNOWLEDGEMENT

The EMTP is a useful tool for simulation of power

system and SVC performance. A detailed model of Static
VAr Compensators (SVC) has been implemented as a set
of EMTP data modules. The model can be applied to
various SVC configurations including the widely-used
FC/TCR type and the combined TSC/TCR type SVCs.
Extensive model validation tests have proved that the
currently available EMTP can accurately simulate the
transient behavior of SVCs in power system.

The authors wish to thank Prof. W. F. Long,

University of Wisconsin-Madison, for his review of and
comments on the functional specification of the model,
and Messrs. D. Dickmander, D. Nickel, and R. Rosenqvist
at ABB's Advanced Systems Technology Division in
Pittsburgh, for their useful advice during the model
development and testing.
REFERENCES

The paper describes a modeling technique which can

be used for the development of complex power equipment.
The paper also describes an effective initialization method
used for the SVC model. The model initialization is
significantly improved due to the calculation section of the
enhanced EDM.

[l] R.H. Lasseter, S.Y.Lee, "Digital Simulation of Static

VAr System Transients",IEEE Transactions on Power
Apparatus and Systems, Vol. PAS-109, No. 10,
October 1982.

The described SVC model will be available in the

coming version 3.0 of the DCG/EPRI-released EMTP.

[2] A.N. Vasconcelos, et al, "Detailed Modeling of an

Actual Static VAr Compensator for Electromagnetic
Transient Studies", IEEE/PES 1991Winter Meeting,
New York, New York, February 3-7,1991.
94 8

m
m

F RFSPIINSF

"

-8.00

e! :a

8'. 20

18/25/98
83.15.82
9
PLOT TYPE

5
p'?

d.33

e'. 48

$.se

d.60

1
8.70

8!B0

I
0.90

d.80

12

8
TCR # l CURRENT, PHASE BC

SVS SUSCEPTQNCE

Figure 12. EMTP simulation of the SVC performance for a three-phase to ground fault at Bus 1
949

"r

VOLTAGE RESPONSE

TCR AB CURRENT

TCR BC CURRENT

Figure 13. TNA simulation of the SVC performance for a three-phase to ground fault at Bus 1
950

[3] A.M. Gole and V.K. Sood, A Static Compensator

The lines 1and 2 are represented as PI-circuits.

Model for Use With Electromagnetic Transients

Simulation Programs, IEEE Transactions on Power
Delivery, Vol. 5, No. 3, July 1990.

Transformer: L = 110.50 mH
Capacitors at

[4] W. Scott Meyer, EMTP Data Modularization and

Sorting by Class: A Foundation Upon Which EMTP
Data Bases Can Be Built,EMTP Newsletter, Volume
4, Number 2, November 1983.

Bus 4:

3 x 67 MVAr

Sang Y. Lee (M89) Mr. Lee attended University of

Saskatchewan, Canada, receiving his BSc. and M.Sc.
degrees in Electrical Engineering. He joined the ASEA
Power Systems Center in 1985 as an engineer in the digital
computer study group. He conducted various electrical
system studies for utility and industrial power systems. In
1989, Mr. Lee transferred to ABBs Advanced Systems
Technology division, where his responsibilities include
model development and studies of power system transients
using the EMTP.

[5] User Manual: EMTP Data Module (Enhanced

Version), April 1990.

[6] Direct Current Transmission

Volume I, E.W.
Kimbark, John Wdey & Sons,Inc., 1971

[7l DCG/EPRI EMTP Rule Book for EMTP Version

2.0, March 1989.
APPENDIX
Equivalent Transmission Network Data

Subroto Bhattacharya (M81, SM90) received his B.Tech.

in Electrical Engineering from Mysore University, India,
in 1981 and his M.Tech. from the Indian Institute of
Technology in 1983. H e spent five months in 1985 at the
ASEA Power Systems Center as a visiting research
trainee. Dr. Bhattacharya earned his Ph.D. in Electrical
Engineering in 1987. After graduation he joined ABBs
Systems Study Center in Milwaukee, WI,and in 1989 he
was transferred to the Advanced Systems Technology
Division in Pittsburgh. His main expertise is in the
modeling and analysis of power system transients. He is
ABBs representative in the EMTP Development
Coordination Group (DCG).

All impedances are referred to the 345 kV side.

ZEQ1: Equivalent impedance at Bus 1.

Dr. Bhattacharya has authored and co-authored several

technical publications on digital simulation of SVC and
HVDC controls including an IETE Prize paper. He has
co-authored a reference manual on the EMTP Theory
book.

R1 = 22.00 R L1 = 95.03 mH
R2 = 80.90 R L2 = 335.10 mH
R3 = 4.87R L3 = 142.84 mH
R4 =100.80~
ZEQ2:
ZEQ3:

L = 132.60 mH
L = 789.00 mH

Line 1:
Line 2:
Line 3:

L = 164.18 mH
L = 82.09mH
L = 88.75 m H

Tommy Lejonberg received his M.Sc. in Electrical

Engineering from Chalmers University of Technology in
Goteborg, Sweden, in 1979. Since graduation in 1979, Mr.
Lejonberg has been with ASEA and now ABB in Vasterk,
Sweden. He started his career with the R&D department
for power electronics and became manager for this
department in 1983. Three years later he became
manager for the department of high power Converters,
which included the responsibility for development, design
and production of control systems and thyristor valves for

C1 = 9.43 p F
C2 = 0.75 p F
C4 = 100.80 pF

svc.

C
C

=
=

0.89pF
0.47pF

In 1988, Mr. Lejonberg joined ABB Power Systems where

he today is responsible for system design and R&D for
reactive power compensator equipment.
951

During his professional career with MEA and ABB, Mr.

Lejonberg has taken an active part in the development of
the SVC technology, especially in the areas of control
systems and thyristor valves.
Adel E. Hammad (M'76, SM'83, F89) received his B.Sc.

(hons.) and M.Sc. from Cairo University and his Ph.D.

from University of Manitoba, all in Electrical Engineering
in 1972, '74 and '78 respectively. From 1975 to '78 he was
with the system planning of Manitoba Hydro in Winnipeg,
Canada. In 1978 he was the chief electrical engineer of
UNIES Engineering Consultants in Winnipeg. Since 1979
he is with Asea Brown Boveri where he is now chief
engineer for HVDC and SVC system applicationsat ABB
Power Systems, Baden, Switzerland.
Dr. Hammad has numerous publications in his field and
is supervising research activities and giving courses at
several universities. He is a registered Professional
Engineer in the province of Manitoba and a member of
the IEEE PES Power System Engineering Committee. He
serves on the System Dynamic Performance and the DC
Transmissionsubcommitteesand is active on several IEEE
and CIGRE working groups.
Serge Lefebvre (M'76) received the B.ScA. and M.ScA.
degrees in electrical engineeringfrom Ecole Polytechnique
de Montreal, Canada in 1976 and 1977 respectively, and a
Ph.D. from Purdue University, Indiana, in 1980. He is
working at the Research Department of Hydro-QuCbec
(IREQ) since 1981 while being an invited professor at
Ecole Polytechnique de MontrCal. His research interests
are in power system analysis techniques, computer
applications, and dc systems. Dr. Lefebvre is Chairman of
the IEEE working group "Dynamic Performance and
Modeling of DC Systems".

952